1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/fdt/fdt_common.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/mmc/bridge.h> 49 #include <dev/mmc/mmcreg.h> 50 #include <dev/mmc/mmcbrvar.h> 51 52 #include <dev/sdhci/sdhci.h> 53 #include "sdhci_if.h" 54 55 #include "bcm2835_dma.h" 56 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 57 #include "bcm2835_vcbus.h" 58 59 #define BCM2835_DEFAULT_SDHCI_FREQ 50 60 61 #define BCM_SDHCI_BUFFER_SIZE 512 62 #define NUM_DMA_SEGS 2 63 64 #ifdef DEBUG 65 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define dprintf(fmt, args...) 69 #endif 70 71 /* DMA doesn't yet work with the bcm3826 */ 72 #ifdef SOC_BCM2836 73 #define PIO_MODE 1 74 #else 75 #define PIO_MODE 0 76 #endif 77 78 static int bcm2835_sdhci_hs = 1; 79 static int bcm2835_sdhci_pio_mode = PIO_MODE; 80 81 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 82 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 83 84 struct bcm_sdhci_softc { 85 device_t sc_dev; 86 struct mtx sc_mtx; 87 struct resource * sc_mem_res; 88 struct resource * sc_irq_res; 89 bus_space_tag_t sc_bst; 90 bus_space_handle_t sc_bsh; 91 void * sc_intrhand; 92 struct mmc_request * sc_req; 93 struct mmc_data * sc_data; 94 uint32_t sc_flags; 95 #define LPC_SD_FLAGS_IGNORECRC (1 << 0) 96 int sc_xfer_direction; 97 #define DIRECTION_READ 0 98 #define DIRECTION_WRITE 1 99 int sc_xfer_done; 100 int sc_bus_busy; 101 struct sdhci_slot sc_slot; 102 int sc_dma_inuse; 103 int sc_dma_ch; 104 bus_dma_tag_t sc_dma_tag; 105 bus_dmamap_t sc_dma_map; 106 vm_paddr_t sc_sdhci_buffer_phys; 107 uint32_t cmd_and_mode; 108 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 109 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 110 int dmamap_seg_count; 111 int dmamap_seg_index; 112 int dmamap_status; 113 }; 114 115 static int bcm_sdhci_probe(device_t); 116 static int bcm_sdhci_attach(device_t); 117 static int bcm_sdhci_detach(device_t); 118 static void bcm_sdhci_intr(void *); 119 120 static int bcm_sdhci_get_ro(device_t, device_t); 121 static void bcm_sdhci_dma_intr(int ch, void *arg); 122 123 #define bcm_sdhci_lock(_sc) \ 124 mtx_lock(&_sc->sc_mtx); 125 #define bcm_sdhci_unlock(_sc) \ 126 mtx_unlock(&_sc->sc_mtx); 127 128 static void 129 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 130 { 131 struct bcm_sdhci_softc *sc = arg; 132 int i; 133 134 sc->dmamap_status = err; 135 sc->dmamap_seg_count = nseg; 136 137 /* Note nseg is guaranteed to be zero if err is non-zero. */ 138 for (i = 0; i < nseg; i++) { 139 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 140 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 141 } 142 } 143 144 static int 145 bcm_sdhci_probe(device_t dev) 146 { 147 148 if (!ofw_bus_status_okay(dev)) 149 return (ENXIO); 150 151 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 152 return (ENXIO); 153 154 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 155 return (BUS_PROBE_DEFAULT); 156 } 157 158 static int 159 bcm_sdhci_attach(device_t dev) 160 { 161 struct bcm_sdhci_softc *sc = device_get_softc(dev); 162 int rid, err; 163 phandle_t node; 164 pcell_t cell; 165 u_int default_freq; 166 167 sc->sc_dev = dev; 168 sc->sc_req = NULL; 169 170 err = bcm2835_mbox_set_power_state(dev, BCM2835_MBOX_POWER_ID_EMMC, 171 TRUE); 172 if (err != 0) { 173 if (bootverbose) 174 device_printf(dev, "Unable to enable the power\n"); 175 return (err); 176 } 177 178 default_freq = 0; 179 err = bcm2835_mbox_get_clock_rate(dev, BCM2835_MBOX_CLOCK_ID_EMMC, 180 &default_freq); 181 if (err == 0) { 182 /* Convert to MHz */ 183 default_freq /= 1000000; 184 } 185 if (default_freq == 0) { 186 node = ofw_bus_get_node(sc->sc_dev); 187 if ((OF_getencprop(node, "clock-frequency", &cell, 188 sizeof(cell))) > 0) 189 default_freq = cell / 1000000; 190 } 191 if (default_freq == 0) 192 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 193 194 if (bootverbose) 195 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 196 197 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 198 199 rid = 0; 200 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 201 RF_ACTIVE); 202 if (!sc->sc_mem_res) { 203 device_printf(dev, "cannot allocate memory window\n"); 204 err = ENXIO; 205 goto fail; 206 } 207 208 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 209 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 210 211 rid = 0; 212 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 213 RF_ACTIVE); 214 if (!sc->sc_irq_res) { 215 device_printf(dev, "cannot allocate interrupt\n"); 216 err = ENXIO; 217 goto fail; 218 } 219 220 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 221 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 222 device_printf(dev, "cannot setup interrupt handler\n"); 223 err = ENXIO; 224 goto fail; 225 } 226 227 if (!bcm2835_sdhci_pio_mode) 228 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 229 230 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 231 if (bcm2835_sdhci_hs) 232 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 233 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 234 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 235 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 236 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 237 | SDHCI_QUIRK_MISSING_CAPS; 238 239 sdhci_init_slot(dev, &sc->sc_slot, 0); 240 241 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 242 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 243 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 244 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 245 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 246 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 247 goto fail; 248 249 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 250 251 /* Allocate bus_dma resources. */ 252 err = bus_dma_tag_create(bus_get_dma_tag(dev), 253 1, 0, BUS_SPACE_MAXADDR_32BIT, 254 BUS_SPACE_MAXADDR, NULL, NULL, 255 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 256 BUS_DMA_ALLOCNOW, NULL, NULL, 257 &sc->sc_dma_tag); 258 259 if (err) { 260 device_printf(dev, "failed allocate DMA tag"); 261 goto fail; 262 } 263 264 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 265 if (err) { 266 device_printf(dev, "bus_dmamap_create failed\n"); 267 goto fail; 268 } 269 270 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 271 SDHCI_BUFFER); 272 273 bus_generic_probe(dev); 274 bus_generic_attach(dev); 275 276 sdhci_start_slot(&sc->sc_slot); 277 278 return (0); 279 280 fail: 281 if (sc->sc_intrhand) 282 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 283 if (sc->sc_irq_res) 284 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 285 if (sc->sc_mem_res) 286 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 287 mtx_destroy(&sc->sc_mtx); 288 289 return (err); 290 } 291 292 static int 293 bcm_sdhci_detach(device_t dev) 294 { 295 296 return (EBUSY); 297 } 298 299 static void 300 bcm_sdhci_intr(void *arg) 301 { 302 struct bcm_sdhci_softc *sc = arg; 303 304 sdhci_generic_intr(&sc->sc_slot); 305 } 306 307 static int 308 bcm_sdhci_get_ro(device_t bus, device_t child) 309 { 310 311 return (0); 312 } 313 314 static inline uint32_t 315 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 316 { 317 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 318 return val; 319 } 320 321 static inline void 322 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 323 { 324 325 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 326 /* 327 * The Arasan HC has a bug where it may lose the content of 328 * consecutive writes to registers that are within two SD-card 329 * clock cycles of each other (a clock domain crossing problem). 330 */ 331 if (sc->sc_slot.clock > 0) 332 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 333 } 334 335 static uint8_t 336 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 337 { 338 struct bcm_sdhci_softc *sc = device_get_softc(dev); 339 uint32_t val = RD4(sc, off & ~3); 340 341 return ((val >> (off & 3)*8) & 0xff); 342 } 343 344 static uint16_t 345 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 346 { 347 struct bcm_sdhci_softc *sc = device_get_softc(dev); 348 uint32_t val = RD4(sc, off & ~3); 349 350 /* 351 * Standard 32-bit handling of command and transfer mode. 352 */ 353 if (off == SDHCI_TRANSFER_MODE) { 354 return (sc->cmd_and_mode >> 16); 355 } else if (off == SDHCI_COMMAND_FLAGS) { 356 return (sc->cmd_and_mode & 0x0000ffff); 357 } 358 return ((val >> (off & 3)*8) & 0xffff); 359 } 360 361 static uint32_t 362 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 363 { 364 struct bcm_sdhci_softc *sc = device_get_softc(dev); 365 366 return RD4(sc, off); 367 } 368 369 static void 370 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 371 uint32_t *data, bus_size_t count) 372 { 373 struct bcm_sdhci_softc *sc = device_get_softc(dev); 374 375 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 376 } 377 378 static void 379 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 380 { 381 struct bcm_sdhci_softc *sc = device_get_softc(dev); 382 uint32_t val32 = RD4(sc, off & ~3); 383 val32 &= ~(0xff << (off & 3)*8); 384 val32 |= (val << (off & 3)*8); 385 WR4(sc, off & ~3, val32); 386 } 387 388 static void 389 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 390 { 391 struct bcm_sdhci_softc *sc = device_get_softc(dev); 392 uint32_t val32; 393 if (off == SDHCI_COMMAND_FLAGS) 394 val32 = sc->cmd_and_mode; 395 else 396 val32 = RD4(sc, off & ~3); 397 val32 &= ~(0xffff << (off & 3)*8); 398 val32 |= (val << (off & 3)*8); 399 if (off == SDHCI_TRANSFER_MODE) 400 sc->cmd_and_mode = val32; 401 else { 402 WR4(sc, off & ~3, val32); 403 if (off == SDHCI_COMMAND_FLAGS) 404 sc->cmd_and_mode = val32; 405 } 406 } 407 408 static void 409 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 410 { 411 struct bcm_sdhci_softc *sc = device_get_softc(dev); 412 WR4(sc, off, val); 413 } 414 415 static void 416 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 417 uint32_t *data, bus_size_t count) 418 { 419 struct bcm_sdhci_softc *sc = device_get_softc(dev); 420 421 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 422 } 423 424 static void 425 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 426 { 427 struct sdhci_slot *slot; 428 vm_paddr_t pdst, psrc; 429 int err, idx, len, sync_op; 430 431 slot = &sc->sc_slot; 432 idx = sc->dmamap_seg_index++; 433 len = sc->dmamap_seg_sizes[idx]; 434 slot->offset += len; 435 436 if (slot->curcmd->data->flags & MMC_DATA_READ) { 437 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 438 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 439 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 440 BCM_DMA_INC_ADDR, 441 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 442 psrc = sc->sc_sdhci_buffer_phys; 443 pdst = sc->dmamap_seg_addrs[idx]; 444 sync_op = BUS_DMASYNC_PREREAD; 445 } else { 446 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 447 BCM_DMA_INC_ADDR, 448 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 449 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 450 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 451 psrc = sc->dmamap_seg_addrs[idx]; 452 pdst = sc->sc_sdhci_buffer_phys; 453 sync_op = BUS_DMASYNC_PREWRITE; 454 } 455 456 /* 457 * When starting a new DMA operation do the busdma sync operation, and 458 * disable SDCHI data interrrupts because we'll be driven by DMA 459 * interrupts (or SDHCI error interrupts) until the IO is done. 460 */ 461 if (idx == 0) { 462 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 463 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 464 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 465 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 466 slot->intmask); 467 } 468 469 /* 470 * Start the DMA transfer. Only programming errors (like failing to 471 * allocate a channel) cause a non-zero return from bcm_dma_start(). 472 */ 473 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 474 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 475 } 476 477 static void 478 bcm_sdhci_dma_intr(int ch, void *arg) 479 { 480 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 481 struct sdhci_slot *slot = &sc->sc_slot; 482 uint32_t reg, mask; 483 int left, sync_op; 484 485 mtx_lock(&slot->mtx); 486 487 /* 488 * If there are more segments for the current dma, start the next one. 489 * Otherwise unload the dma map and decide what to do next based on the 490 * status of the sdhci controller and whether there's more data left. 491 */ 492 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 493 bcm_sdhci_start_dma_seg(sc); 494 mtx_unlock(&slot->mtx); 495 return; 496 } 497 498 if (slot->curcmd->data->flags & MMC_DATA_READ) { 499 sync_op = BUS_DMASYNC_POSTREAD; 500 mask = SDHCI_INT_DATA_AVAIL; 501 } else { 502 sync_op = BUS_DMASYNC_POSTWRITE; 503 mask = SDHCI_INT_SPACE_AVAIL; 504 } 505 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 506 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 507 508 sc->dmamap_seg_count = 0; 509 sc->dmamap_seg_index = 0; 510 511 left = min(BCM_SDHCI_BUFFER_SIZE, 512 slot->curcmd->data->len - slot->offset); 513 514 /* DATA END? */ 515 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 516 517 if (reg & SDHCI_INT_DATA_END) { 518 /* ACK for all outstanding interrupts */ 519 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 520 521 /* enable INT */ 522 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 523 | SDHCI_INT_DATA_END; 524 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 525 slot->intmask); 526 527 /* finish this data */ 528 sdhci_finish_data(slot); 529 } 530 else { 531 /* already available? */ 532 if (reg & mask) { 533 534 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 535 bcm_sdhci_write_4(slot->bus, slot, 536 SDHCI_INT_STATUS, mask); 537 538 /* continue next DMA transfer */ 539 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 540 (uint8_t *)slot->curcmd->data->data + 541 slot->offset, left, bcm_sdhci_dmacb, sc, 542 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 543 slot->curcmd->error = MMC_ERR_NO_MEMORY; 544 sdhci_finish_data(slot); 545 } else { 546 bcm_sdhci_start_dma_seg(sc); 547 } 548 } else { 549 /* wait for next data by INT */ 550 551 /* enable INT */ 552 slot->intmask |= SDHCI_INT_DATA_AVAIL | 553 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 554 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 555 slot->intmask); 556 } 557 } 558 559 mtx_unlock(&slot->mtx); 560 } 561 562 static void 563 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 564 { 565 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 566 size_t left; 567 568 if (sc->dmamap_seg_count != 0) { 569 device_printf(sc->sc_dev, "DMA in use\n"); 570 return; 571 } 572 573 left = min(BCM_SDHCI_BUFFER_SIZE, 574 slot->curcmd->data->len - slot->offset); 575 576 KASSERT((left & 3) == 0, 577 ("%s: len = %d, not word-aligned", __func__, left)); 578 579 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 580 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 581 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 582 sc->dmamap_status != 0) { 583 slot->curcmd->error = MMC_ERR_NO_MEMORY; 584 return; 585 } 586 587 /* DMA start */ 588 bcm_sdhci_start_dma_seg(sc); 589 } 590 591 static void 592 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 593 { 594 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 595 size_t left; 596 597 if (sc->dmamap_seg_count != 0) { 598 device_printf(sc->sc_dev, "DMA in use\n"); 599 return; 600 } 601 602 left = min(BCM_SDHCI_BUFFER_SIZE, 603 slot->curcmd->data->len - slot->offset); 604 605 KASSERT((left & 3) == 0, 606 ("%s: len = %d, not word-aligned", __func__, left)); 607 608 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 609 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 610 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 611 sc->dmamap_status != 0) { 612 slot->curcmd->error = MMC_ERR_NO_MEMORY; 613 return; 614 } 615 616 /* DMA start */ 617 bcm_sdhci_start_dma_seg(sc); 618 } 619 620 static int 621 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 622 { 623 size_t left; 624 625 /* 626 * Do not use DMA for transfers less than block size or with a length 627 * that is not a multiple of four. 628 */ 629 left = min(BCM_DMA_BLOCK_SIZE, 630 slot->curcmd->data->len - slot->offset); 631 if (left < BCM_DMA_BLOCK_SIZE) 632 return (0); 633 if (left & 0x03) 634 return (0); 635 636 return (1); 637 } 638 639 static void 640 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 641 uint32_t *intmask) 642 { 643 644 /* DMA transfer FIFO 1KB */ 645 if (slot->curcmd->data->flags & MMC_DATA_READ) 646 bcm_sdhci_read_dma(dev, slot); 647 else 648 bcm_sdhci_write_dma(dev, slot); 649 } 650 651 static void 652 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 653 { 654 655 sdhci_finish_data(slot); 656 } 657 658 static device_method_t bcm_sdhci_methods[] = { 659 /* Device interface */ 660 DEVMETHOD(device_probe, bcm_sdhci_probe), 661 DEVMETHOD(device_attach, bcm_sdhci_attach), 662 DEVMETHOD(device_detach, bcm_sdhci_detach), 663 664 /* Bus interface */ 665 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 666 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 667 DEVMETHOD(bus_print_child, bus_generic_print_child), 668 669 /* MMC bridge interface */ 670 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 671 DEVMETHOD(mmcbr_request, sdhci_generic_request), 672 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 673 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 674 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 675 676 /* Platform transfer methods */ 677 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 678 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 679 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 680 /* SDHCI registers accessors */ 681 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 682 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 683 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 684 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 685 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 686 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 687 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 688 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 689 690 { 0, 0 } 691 }; 692 693 static devclass_t bcm_sdhci_devclass; 694 695 static driver_t bcm_sdhci_driver = { 696 "sdhci_bcm", 697 bcm_sdhci_methods, 698 sizeof(struct bcm_sdhci_softc), 699 }; 700 701 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 702 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 703