1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include <dev/sdhci/sdhci.h> 52 #include "sdhci_if.h" 53 54 #include "bcm2835_dma.h" 55 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 56 #include "bcm2835_vcbus.h" 57 58 #define BCM2835_DEFAULT_SDHCI_FREQ 50 59 60 #define BCM_SDHCI_BUFFER_SIZE 512 61 #define NUM_DMA_SEGS 2 62 63 #ifdef DEBUG 64 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 65 printf(fmt,##args); } while (0) 66 #else 67 #define dprintf(fmt, args...) 68 #endif 69 70 static int bcm2835_sdhci_hs = 1; 71 static int bcm2835_sdhci_pio_mode = 0; 72 73 static struct ofw_compat_data compat_data[] = { 74 {"broadcom,bcm2835-sdhci", 1}, 75 {"brcm,bcm2835-mmc", 1}, 76 {NULL, 0} 77 }; 78 79 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 80 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 81 82 struct bcm_sdhci_softc { 83 device_t sc_dev; 84 struct resource * sc_mem_res; 85 struct resource * sc_irq_res; 86 bus_space_tag_t sc_bst; 87 bus_space_handle_t sc_bsh; 88 void * sc_intrhand; 89 struct mmc_request * sc_req; 90 struct sdhci_slot sc_slot; 91 int sc_dma_ch; 92 bus_dma_tag_t sc_dma_tag; 93 bus_dmamap_t sc_dma_map; 94 vm_paddr_t sc_sdhci_buffer_phys; 95 uint32_t cmd_and_mode; 96 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 97 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 98 int dmamap_seg_count; 99 int dmamap_seg_index; 100 int dmamap_status; 101 }; 102 103 static int bcm_sdhci_probe(device_t); 104 static int bcm_sdhci_attach(device_t); 105 static int bcm_sdhci_detach(device_t); 106 static void bcm_sdhci_intr(void *); 107 108 static int bcm_sdhci_get_ro(device_t, device_t); 109 static void bcm_sdhci_dma_intr(int ch, void *arg); 110 111 static void 112 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 113 { 114 struct bcm_sdhci_softc *sc = arg; 115 int i; 116 117 sc->dmamap_status = err; 118 sc->dmamap_seg_count = nseg; 119 120 /* Note nseg is guaranteed to be zero if err is non-zero. */ 121 for (i = 0; i < nseg; i++) { 122 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 123 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 124 } 125 } 126 127 static int 128 bcm_sdhci_probe(device_t dev) 129 { 130 131 if (!ofw_bus_status_okay(dev)) 132 return (ENXIO); 133 134 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 135 return (ENXIO); 136 137 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 138 139 return (BUS_PROBE_DEFAULT); 140 } 141 142 static int 143 bcm_sdhci_attach(device_t dev) 144 { 145 struct bcm_sdhci_softc *sc = device_get_softc(dev); 146 int rid, err; 147 phandle_t node; 148 pcell_t cell; 149 u_int default_freq; 150 151 sc->sc_dev = dev; 152 sc->sc_req = NULL; 153 154 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, 155 TRUE); 156 if (err != 0) { 157 if (bootverbose) 158 device_printf(dev, "Unable to enable the power\n"); 159 return (err); 160 } 161 162 default_freq = 0; 163 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, 164 &default_freq); 165 if (err == 0) { 166 /* Convert to MHz */ 167 default_freq /= 1000000; 168 } 169 if (default_freq == 0) { 170 node = ofw_bus_get_node(sc->sc_dev); 171 if ((OF_getencprop(node, "clock-frequency", &cell, 172 sizeof(cell))) > 0) 173 default_freq = cell / 1000000; 174 } 175 if (default_freq == 0) 176 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 177 178 if (bootverbose) 179 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 180 181 rid = 0; 182 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 183 RF_ACTIVE); 184 if (!sc->sc_mem_res) { 185 device_printf(dev, "cannot allocate memory window\n"); 186 err = ENXIO; 187 goto fail; 188 } 189 190 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 191 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 192 193 rid = 0; 194 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 195 RF_ACTIVE); 196 if (!sc->sc_irq_res) { 197 device_printf(dev, "cannot allocate interrupt\n"); 198 err = ENXIO; 199 goto fail; 200 } 201 202 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 203 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 204 device_printf(dev, "cannot setup interrupt handler\n"); 205 err = ENXIO; 206 goto fail; 207 } 208 209 if (!bcm2835_sdhci_pio_mode) 210 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 211 212 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 213 if (bcm2835_sdhci_hs) 214 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 215 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 216 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 217 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 218 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 219 | SDHCI_QUIRK_MISSING_CAPS; 220 221 sdhci_init_slot(dev, &sc->sc_slot, 0); 222 223 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 224 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 225 goto fail; 226 227 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 228 229 /* Allocate bus_dma resources. */ 230 err = bus_dma_tag_create(bus_get_dma_tag(dev), 231 1, 0, BUS_SPACE_MAXADDR_32BIT, 232 BUS_SPACE_MAXADDR, NULL, NULL, 233 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 234 BUS_DMA_ALLOCNOW, NULL, NULL, 235 &sc->sc_dma_tag); 236 237 if (err) { 238 device_printf(dev, "failed allocate DMA tag"); 239 goto fail; 240 } 241 242 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 243 if (err) { 244 device_printf(dev, "bus_dmamap_create failed\n"); 245 goto fail; 246 } 247 248 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ 249 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + 250 SDHCI_BUFFER; 251 252 bus_generic_probe(dev); 253 bus_generic_attach(dev); 254 255 sdhci_start_slot(&sc->sc_slot); 256 257 return (0); 258 259 fail: 260 if (sc->sc_intrhand) 261 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 262 if (sc->sc_irq_res) 263 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 264 if (sc->sc_mem_res) 265 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 266 267 return (err); 268 } 269 270 static int 271 bcm_sdhci_detach(device_t dev) 272 { 273 274 return (EBUSY); 275 } 276 277 static void 278 bcm_sdhci_intr(void *arg) 279 { 280 struct bcm_sdhci_softc *sc = arg; 281 282 sdhci_generic_intr(&sc->sc_slot); 283 } 284 285 static int 286 bcm_sdhci_get_ro(device_t bus, device_t child) 287 { 288 289 return (0); 290 } 291 292 static inline uint32_t 293 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 294 { 295 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 296 return val; 297 } 298 299 static inline void 300 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 301 { 302 303 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 304 /* 305 * The Arasan HC has a bug where it may lose the content of 306 * consecutive writes to registers that are within two SD-card 307 * clock cycles of each other (a clock domain crossing problem). 308 */ 309 if (sc->sc_slot.clock > 0) 310 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 311 } 312 313 static uint8_t 314 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 315 { 316 struct bcm_sdhci_softc *sc = device_get_softc(dev); 317 uint32_t val = RD4(sc, off & ~3); 318 319 return ((val >> (off & 3)*8) & 0xff); 320 } 321 322 static uint16_t 323 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 324 { 325 struct bcm_sdhci_softc *sc = device_get_softc(dev); 326 uint32_t val = RD4(sc, off & ~3); 327 328 /* 329 * Standard 32-bit handling of command and transfer mode. 330 */ 331 if (off == SDHCI_TRANSFER_MODE) { 332 return (sc->cmd_and_mode >> 16); 333 } else if (off == SDHCI_COMMAND_FLAGS) { 334 return (sc->cmd_and_mode & 0x0000ffff); 335 } 336 return ((val >> (off & 3)*8) & 0xffff); 337 } 338 339 static uint32_t 340 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 341 { 342 struct bcm_sdhci_softc *sc = device_get_softc(dev); 343 344 return RD4(sc, off); 345 } 346 347 static void 348 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 349 uint32_t *data, bus_size_t count) 350 { 351 struct bcm_sdhci_softc *sc = device_get_softc(dev); 352 353 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 354 } 355 356 static void 357 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 358 { 359 struct bcm_sdhci_softc *sc = device_get_softc(dev); 360 uint32_t val32 = RD4(sc, off & ~3); 361 val32 &= ~(0xff << (off & 3)*8); 362 val32 |= (val << (off & 3)*8); 363 WR4(sc, off & ~3, val32); 364 } 365 366 static void 367 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 368 { 369 struct bcm_sdhci_softc *sc = device_get_softc(dev); 370 uint32_t val32; 371 if (off == SDHCI_COMMAND_FLAGS) 372 val32 = sc->cmd_and_mode; 373 else 374 val32 = RD4(sc, off & ~3); 375 val32 &= ~(0xffff << (off & 3)*8); 376 val32 |= (val << (off & 3)*8); 377 if (off == SDHCI_TRANSFER_MODE) 378 sc->cmd_and_mode = val32; 379 else { 380 WR4(sc, off & ~3, val32); 381 if (off == SDHCI_COMMAND_FLAGS) 382 sc->cmd_and_mode = val32; 383 } 384 } 385 386 static void 387 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 388 { 389 struct bcm_sdhci_softc *sc = device_get_softc(dev); 390 WR4(sc, off, val); 391 } 392 393 static void 394 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 395 uint32_t *data, bus_size_t count) 396 { 397 struct bcm_sdhci_softc *sc = device_get_softc(dev); 398 399 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 400 } 401 402 static void 403 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 404 { 405 struct sdhci_slot *slot; 406 vm_paddr_t pdst, psrc; 407 int err, idx, len, sync_op; 408 409 slot = &sc->sc_slot; 410 idx = sc->dmamap_seg_index++; 411 len = sc->dmamap_seg_sizes[idx]; 412 slot->offset += len; 413 414 if (slot->curcmd->data->flags & MMC_DATA_READ) { 415 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 416 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 417 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 418 BCM_DMA_INC_ADDR, 419 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 420 psrc = sc->sc_sdhci_buffer_phys; 421 pdst = sc->dmamap_seg_addrs[idx]; 422 sync_op = BUS_DMASYNC_PREREAD; 423 } else { 424 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 425 BCM_DMA_INC_ADDR, 426 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 427 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 428 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 429 psrc = sc->dmamap_seg_addrs[idx]; 430 pdst = sc->sc_sdhci_buffer_phys; 431 sync_op = BUS_DMASYNC_PREWRITE; 432 } 433 434 /* 435 * When starting a new DMA operation do the busdma sync operation, and 436 * disable SDCHI data interrrupts because we'll be driven by DMA 437 * interrupts (or SDHCI error interrupts) until the IO is done. 438 */ 439 if (idx == 0) { 440 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 441 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 442 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 443 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 444 slot->intmask); 445 } 446 447 /* 448 * Start the DMA transfer. Only programming errors (like failing to 449 * allocate a channel) cause a non-zero return from bcm_dma_start(). 450 */ 451 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 452 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 453 } 454 455 static void 456 bcm_sdhci_dma_intr(int ch, void *arg) 457 { 458 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 459 struct sdhci_slot *slot = &sc->sc_slot; 460 uint32_t reg, mask; 461 int left, sync_op; 462 463 mtx_lock(&slot->mtx); 464 465 /* 466 * If there are more segments for the current dma, start the next one. 467 * Otherwise unload the dma map and decide what to do next based on the 468 * status of the sdhci controller and whether there's more data left. 469 */ 470 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 471 bcm_sdhci_start_dma_seg(sc); 472 mtx_unlock(&slot->mtx); 473 return; 474 } 475 476 if (slot->curcmd->data->flags & MMC_DATA_READ) { 477 sync_op = BUS_DMASYNC_POSTREAD; 478 mask = SDHCI_INT_DATA_AVAIL; 479 } else { 480 sync_op = BUS_DMASYNC_POSTWRITE; 481 mask = SDHCI_INT_SPACE_AVAIL; 482 } 483 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 484 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 485 486 sc->dmamap_seg_count = 0; 487 sc->dmamap_seg_index = 0; 488 489 left = min(BCM_SDHCI_BUFFER_SIZE, 490 slot->curcmd->data->len - slot->offset); 491 492 /* DATA END? */ 493 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 494 495 if (reg & SDHCI_INT_DATA_END) { 496 /* ACK for all outstanding interrupts */ 497 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 498 499 /* enable INT */ 500 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 501 | SDHCI_INT_DATA_END; 502 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 503 slot->intmask); 504 505 /* finish this data */ 506 sdhci_finish_data(slot); 507 } 508 else { 509 /* already available? */ 510 if (reg & mask) { 511 512 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 513 bcm_sdhci_write_4(slot->bus, slot, 514 SDHCI_INT_STATUS, mask); 515 516 /* continue next DMA transfer */ 517 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 518 (uint8_t *)slot->curcmd->data->data + 519 slot->offset, left, bcm_sdhci_dmacb, sc, 520 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 521 slot->curcmd->error = MMC_ERR_NO_MEMORY; 522 sdhci_finish_data(slot); 523 } else { 524 bcm_sdhci_start_dma_seg(sc); 525 } 526 } else { 527 /* wait for next data by INT */ 528 529 /* enable INT */ 530 slot->intmask |= SDHCI_INT_DATA_AVAIL | 531 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 532 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 533 slot->intmask); 534 } 535 } 536 537 mtx_unlock(&slot->mtx); 538 } 539 540 static void 541 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 542 { 543 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 544 size_t left; 545 546 if (sc->dmamap_seg_count != 0) { 547 device_printf(sc->sc_dev, "DMA in use\n"); 548 return; 549 } 550 551 left = min(BCM_SDHCI_BUFFER_SIZE, 552 slot->curcmd->data->len - slot->offset); 553 554 KASSERT((left & 3) == 0, 555 ("%s: len = %zu, not word-aligned", __func__, left)); 556 557 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 558 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 559 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 560 sc->dmamap_status != 0) { 561 slot->curcmd->error = MMC_ERR_NO_MEMORY; 562 return; 563 } 564 565 /* DMA start */ 566 bcm_sdhci_start_dma_seg(sc); 567 } 568 569 static void 570 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 571 { 572 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 573 size_t left; 574 575 if (sc->dmamap_seg_count != 0) { 576 device_printf(sc->sc_dev, "DMA in use\n"); 577 return; 578 } 579 580 left = min(BCM_SDHCI_BUFFER_SIZE, 581 slot->curcmd->data->len - slot->offset); 582 583 KASSERT((left & 3) == 0, 584 ("%s: len = %zu, not word-aligned", __func__, left)); 585 586 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 587 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 588 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 589 sc->dmamap_status != 0) { 590 slot->curcmd->error = MMC_ERR_NO_MEMORY; 591 return; 592 } 593 594 /* DMA start */ 595 bcm_sdhci_start_dma_seg(sc); 596 } 597 598 static int 599 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 600 { 601 size_t left; 602 603 /* 604 * Do not use DMA for transfers less than block size or with a length 605 * that is not a multiple of four. 606 */ 607 left = min(BCM_DMA_BLOCK_SIZE, 608 slot->curcmd->data->len - slot->offset); 609 if (left < BCM_DMA_BLOCK_SIZE) 610 return (0); 611 if (left & 0x03) 612 return (0); 613 614 return (1); 615 } 616 617 static void 618 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 619 uint32_t *intmask) 620 { 621 622 /* DMA transfer FIFO 1KB */ 623 if (slot->curcmd->data->flags & MMC_DATA_READ) 624 bcm_sdhci_read_dma(dev, slot); 625 else 626 bcm_sdhci_write_dma(dev, slot); 627 } 628 629 static void 630 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 631 { 632 633 sdhci_finish_data(slot); 634 } 635 636 static device_method_t bcm_sdhci_methods[] = { 637 /* Device interface */ 638 DEVMETHOD(device_probe, bcm_sdhci_probe), 639 DEVMETHOD(device_attach, bcm_sdhci_attach), 640 DEVMETHOD(device_detach, bcm_sdhci_detach), 641 642 /* Bus interface */ 643 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 644 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 645 DEVMETHOD(bus_print_child, bus_generic_print_child), 646 647 /* MMC bridge interface */ 648 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 649 DEVMETHOD(mmcbr_request, sdhci_generic_request), 650 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 651 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 652 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 653 654 /* Platform transfer methods */ 655 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 656 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 657 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 658 /* SDHCI registers accessors */ 659 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 660 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 661 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 662 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 663 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 664 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 665 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 666 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 667 668 { 0, 0 } 669 }; 670 671 static devclass_t bcm_sdhci_devclass; 672 673 static driver_t bcm_sdhci_driver = { 674 "sdhci_bcm", 675 bcm_sdhci_methods, 676 sizeof(struct bcm_sdhci_softc), 677 }; 678 679 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 680 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 681 DRIVER_MODULE(mmc, sdhci_bcm, mmc_driver, mmc_devclass, NULL, NULL); 682 MODULE_DEPEND(sdhci_bcm, mmc, 1, 1, 1); 683