1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <sys/taskqueue.h> 43 44 #include <machine/bus.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcreg.h> 51 52 #include <dev/sdhci/sdhci.h> 53 54 #include "mmcbr_if.h" 55 #include "sdhci_if.h" 56 57 #include "opt_mmccam.h" 58 59 #include "bcm2835_dma.h" 60 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 61 #include "bcm2835_vcbus.h" 62 63 #define BCM2835_DEFAULT_SDHCI_FREQ 50 64 65 #define BCM_SDHCI_BUFFER_SIZE 512 66 #define NUM_DMA_SEGS 2 67 68 #ifdef DEBUG 69 static int bcm2835_sdhci_debug = 0; 70 71 TUNABLE_INT("hw.bcm2835.sdhci.debug", &bcm2835_sdhci_debug); 72 SYSCTL_INT(_hw_sdhci, OID_AUTO, bcm2835_sdhci_debug, CTLFLAG_RWTUN, 73 &bcm2835_sdhci_debug, 0, "bcm2835 SDHCI debug level"); 74 75 #define dprintf(fmt, args...) \ 76 do { \ 77 if (bcm2835_sdhci_debug) \ 78 printf("%s: " fmt, __func__, ##args); \ 79 } while (0) 80 #else 81 #define dprintf(fmt, args...) 82 #endif 83 84 static int bcm2835_sdhci_hs = 1; 85 static int bcm2835_sdhci_pio_mode = 0; 86 87 static struct ofw_compat_data compat_data[] = { 88 {"broadcom,bcm2835-sdhci", 1}, 89 {"brcm,bcm2835-sdhci", 1}, 90 {"brcm,bcm2835-mmc", 1}, 91 {NULL, 0} 92 }; 93 94 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 95 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 96 97 struct bcm_sdhci_softc { 98 device_t sc_dev; 99 struct resource * sc_mem_res; 100 struct resource * sc_irq_res; 101 bus_space_tag_t sc_bst; 102 bus_space_handle_t sc_bsh; 103 void * sc_intrhand; 104 struct mmc_request * sc_req; 105 struct sdhci_slot sc_slot; 106 int sc_dma_ch; 107 bus_dma_tag_t sc_dma_tag; 108 bus_dmamap_t sc_dma_map; 109 vm_paddr_t sc_sdhci_buffer_phys; 110 uint32_t cmd_and_mode; 111 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 112 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 113 int dmamap_seg_count; 114 int dmamap_seg_index; 115 int dmamap_status; 116 }; 117 118 static int bcm_sdhci_probe(device_t); 119 static int bcm_sdhci_attach(device_t); 120 static int bcm_sdhci_detach(device_t); 121 static void bcm_sdhci_intr(void *); 122 123 static int bcm_sdhci_get_ro(device_t, device_t); 124 static void bcm_sdhci_dma_intr(int ch, void *arg); 125 126 static void 127 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 128 { 129 struct bcm_sdhci_softc *sc = arg; 130 int i; 131 132 sc->dmamap_status = err; 133 sc->dmamap_seg_count = nseg; 134 135 /* Note nseg is guaranteed to be zero if err is non-zero. */ 136 for (i = 0; i < nseg; i++) { 137 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 138 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 139 } 140 } 141 142 static int 143 bcm_sdhci_probe(device_t dev) 144 { 145 146 if (!ofw_bus_status_okay(dev)) 147 return (ENXIO); 148 149 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 150 return (ENXIO); 151 152 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 153 154 return (BUS_PROBE_DEFAULT); 155 } 156 157 static int 158 bcm_sdhci_attach(device_t dev) 159 { 160 struct bcm_sdhci_softc *sc = device_get_softc(dev); 161 int rid, err; 162 phandle_t node; 163 pcell_t cell; 164 u_int default_freq; 165 166 sc->sc_dev = dev; 167 sc->sc_req = NULL; 168 169 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, 170 TRUE); 171 if (err != 0) { 172 if (bootverbose) 173 device_printf(dev, "Unable to enable the power\n"); 174 return (err); 175 } 176 177 default_freq = 0; 178 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, 179 &default_freq); 180 if (err == 0) { 181 /* Convert to MHz */ 182 default_freq /= 1000000; 183 } 184 if (default_freq == 0) { 185 node = ofw_bus_get_node(sc->sc_dev); 186 if ((OF_getencprop(node, "clock-frequency", &cell, 187 sizeof(cell))) > 0) 188 default_freq = cell / 1000000; 189 } 190 if (default_freq == 0) 191 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 192 193 if (bootverbose) 194 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 195 196 rid = 0; 197 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 198 RF_ACTIVE); 199 if (!sc->sc_mem_res) { 200 device_printf(dev, "cannot allocate memory window\n"); 201 err = ENXIO; 202 goto fail; 203 } 204 205 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 206 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 207 208 rid = 0; 209 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 210 RF_ACTIVE); 211 if (!sc->sc_irq_res) { 212 device_printf(dev, "cannot allocate interrupt\n"); 213 err = ENXIO; 214 goto fail; 215 } 216 217 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 218 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 219 device_printf(dev, "cannot setup interrupt handler\n"); 220 err = ENXIO; 221 goto fail; 222 } 223 224 if (!bcm2835_sdhci_pio_mode) 225 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 226 227 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 228 if (bcm2835_sdhci_hs) 229 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 230 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 231 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 232 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 233 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 234 | SDHCI_QUIRK_MISSING_CAPS; 235 236 sdhci_init_slot(dev, &sc->sc_slot, 0); 237 238 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 239 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 240 goto fail; 241 242 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 243 244 /* Allocate bus_dma resources. */ 245 err = bus_dma_tag_create(bus_get_dma_tag(dev), 246 1, 0, BUS_SPACE_MAXADDR_32BIT, 247 BUS_SPACE_MAXADDR, NULL, NULL, 248 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 249 BUS_DMA_ALLOCNOW, NULL, NULL, 250 &sc->sc_dma_tag); 251 252 if (err) { 253 device_printf(dev, "failed allocate DMA tag"); 254 goto fail; 255 } 256 257 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 258 if (err) { 259 device_printf(dev, "bus_dmamap_create failed\n"); 260 goto fail; 261 } 262 263 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ 264 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + 265 SDHCI_BUFFER; 266 267 bus_generic_probe(dev); 268 bus_generic_attach(dev); 269 270 sdhci_start_slot(&sc->sc_slot); 271 272 return (0); 273 274 fail: 275 if (sc->sc_intrhand) 276 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 277 if (sc->sc_irq_res) 278 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 279 if (sc->sc_mem_res) 280 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 281 282 return (err); 283 } 284 285 static int 286 bcm_sdhci_detach(device_t dev) 287 { 288 289 return (EBUSY); 290 } 291 292 static void 293 bcm_sdhci_intr(void *arg) 294 { 295 struct bcm_sdhci_softc *sc = arg; 296 297 sdhci_generic_intr(&sc->sc_slot); 298 } 299 300 static int 301 bcm_sdhci_get_ro(device_t bus, device_t child) 302 { 303 304 return (0); 305 } 306 307 static inline uint32_t 308 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 309 { 310 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 311 return val; 312 } 313 314 static inline void 315 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 316 { 317 318 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 319 /* 320 * The Arasan HC has a bug where it may lose the content of 321 * consecutive writes to registers that are within two SD-card 322 * clock cycles of each other (a clock domain crossing problem). 323 */ 324 if (sc->sc_slot.clock > 0) 325 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 326 } 327 328 static uint8_t 329 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 330 { 331 struct bcm_sdhci_softc *sc = device_get_softc(dev); 332 uint32_t val = RD4(sc, off & ~3); 333 334 return ((val >> (off & 3)*8) & 0xff); 335 } 336 337 static uint16_t 338 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 339 { 340 struct bcm_sdhci_softc *sc = device_get_softc(dev); 341 uint32_t val = RD4(sc, off & ~3); 342 343 /* 344 * Standard 32-bit handling of command and transfer mode. 345 */ 346 if (off == SDHCI_TRANSFER_MODE) { 347 return (sc->cmd_and_mode >> 16); 348 } else if (off == SDHCI_COMMAND_FLAGS) { 349 return (sc->cmd_and_mode & 0x0000ffff); 350 } 351 return ((val >> (off & 3)*8) & 0xffff); 352 } 353 354 static uint32_t 355 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 356 { 357 struct bcm_sdhci_softc *sc = device_get_softc(dev); 358 359 return RD4(sc, off); 360 } 361 362 static void 363 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 364 uint32_t *data, bus_size_t count) 365 { 366 struct bcm_sdhci_softc *sc = device_get_softc(dev); 367 368 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 369 } 370 371 static void 372 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 373 { 374 struct bcm_sdhci_softc *sc = device_get_softc(dev); 375 uint32_t val32 = RD4(sc, off & ~3); 376 val32 &= ~(0xff << (off & 3)*8); 377 val32 |= (val << (off & 3)*8); 378 WR4(sc, off & ~3, val32); 379 } 380 381 static void 382 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 383 { 384 struct bcm_sdhci_softc *sc = device_get_softc(dev); 385 uint32_t val32; 386 if (off == SDHCI_COMMAND_FLAGS) 387 val32 = sc->cmd_and_mode; 388 else 389 val32 = RD4(sc, off & ~3); 390 val32 &= ~(0xffff << (off & 3)*8); 391 val32 |= (val << (off & 3)*8); 392 if (off == SDHCI_TRANSFER_MODE) 393 sc->cmd_and_mode = val32; 394 else { 395 WR4(sc, off & ~3, val32); 396 if (off == SDHCI_COMMAND_FLAGS) 397 sc->cmd_and_mode = val32; 398 } 399 } 400 401 static void 402 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 403 { 404 struct bcm_sdhci_softc *sc = device_get_softc(dev); 405 WR4(sc, off, val); 406 } 407 408 static void 409 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 410 uint32_t *data, bus_size_t count) 411 { 412 struct bcm_sdhci_softc *sc = device_get_softc(dev); 413 414 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 415 } 416 417 static void 418 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 419 { 420 struct sdhci_slot *slot; 421 vm_paddr_t pdst, psrc; 422 int err, idx, len, sync_op; 423 424 slot = &sc->sc_slot; 425 idx = sc->dmamap_seg_index++; 426 len = sc->dmamap_seg_sizes[idx]; 427 slot->offset += len; 428 429 if (slot->curcmd->data->flags & MMC_DATA_READ) { 430 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 431 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 432 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 433 BCM_DMA_INC_ADDR, 434 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 435 psrc = sc->sc_sdhci_buffer_phys; 436 pdst = sc->dmamap_seg_addrs[idx]; 437 sync_op = BUS_DMASYNC_PREREAD; 438 } else { 439 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 440 BCM_DMA_INC_ADDR, 441 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 442 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 443 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 444 psrc = sc->dmamap_seg_addrs[idx]; 445 pdst = sc->sc_sdhci_buffer_phys; 446 sync_op = BUS_DMASYNC_PREWRITE; 447 } 448 449 /* 450 * When starting a new DMA operation do the busdma sync operation, and 451 * disable SDCHI data interrrupts because we'll be driven by DMA 452 * interrupts (or SDHCI error interrupts) until the IO is done. 453 */ 454 if (idx == 0) { 455 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 456 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 457 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 458 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 459 slot->intmask); 460 } 461 462 /* 463 * Start the DMA transfer. Only programming errors (like failing to 464 * allocate a channel) cause a non-zero return from bcm_dma_start(). 465 */ 466 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 467 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 468 } 469 470 static void 471 bcm_sdhci_dma_intr(int ch, void *arg) 472 { 473 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 474 struct sdhci_slot *slot = &sc->sc_slot; 475 uint32_t reg, mask; 476 int left, sync_op; 477 478 mtx_lock(&slot->mtx); 479 480 /* 481 * If there are more segments for the current dma, start the next one. 482 * Otherwise unload the dma map and decide what to do next based on the 483 * status of the sdhci controller and whether there's more data left. 484 */ 485 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 486 bcm_sdhci_start_dma_seg(sc); 487 mtx_unlock(&slot->mtx); 488 return; 489 } 490 491 if (slot->curcmd->data->flags & MMC_DATA_READ) { 492 sync_op = BUS_DMASYNC_POSTREAD; 493 mask = SDHCI_INT_DATA_AVAIL; 494 } else { 495 sync_op = BUS_DMASYNC_POSTWRITE; 496 mask = SDHCI_INT_SPACE_AVAIL; 497 } 498 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 499 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 500 501 sc->dmamap_seg_count = 0; 502 sc->dmamap_seg_index = 0; 503 504 left = min(BCM_SDHCI_BUFFER_SIZE, 505 slot->curcmd->data->len - slot->offset); 506 507 /* DATA END? */ 508 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 509 510 if (reg & SDHCI_INT_DATA_END) { 511 /* ACK for all outstanding interrupts */ 512 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 513 514 /* enable INT */ 515 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 516 | SDHCI_INT_DATA_END; 517 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 518 slot->intmask); 519 520 /* finish this data */ 521 sdhci_finish_data(slot); 522 } 523 else { 524 /* already available? */ 525 if (reg & mask) { 526 527 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 528 bcm_sdhci_write_4(slot->bus, slot, 529 SDHCI_INT_STATUS, mask); 530 531 /* continue next DMA transfer */ 532 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 533 (uint8_t *)slot->curcmd->data->data + 534 slot->offset, left, bcm_sdhci_dmacb, sc, 535 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 536 slot->curcmd->error = MMC_ERR_NO_MEMORY; 537 sdhci_finish_data(slot); 538 } else { 539 bcm_sdhci_start_dma_seg(sc); 540 } 541 } else { 542 /* wait for next data by INT */ 543 544 /* enable INT */ 545 slot->intmask |= SDHCI_INT_DATA_AVAIL | 546 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 547 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 548 slot->intmask); 549 } 550 } 551 552 mtx_unlock(&slot->mtx); 553 } 554 555 static void 556 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 557 { 558 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 559 size_t left; 560 561 if (sc->dmamap_seg_count != 0) { 562 device_printf(sc->sc_dev, "DMA in use\n"); 563 return; 564 } 565 566 left = min(BCM_SDHCI_BUFFER_SIZE, 567 slot->curcmd->data->len - slot->offset); 568 569 KASSERT((left & 3) == 0, 570 ("%s: len = %zu, not word-aligned", __func__, left)); 571 572 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 573 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 574 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 575 sc->dmamap_status != 0) { 576 slot->curcmd->error = MMC_ERR_NO_MEMORY; 577 return; 578 } 579 580 /* DMA start */ 581 bcm_sdhci_start_dma_seg(sc); 582 } 583 584 static void 585 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 586 { 587 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 588 size_t left; 589 590 if (sc->dmamap_seg_count != 0) { 591 device_printf(sc->sc_dev, "DMA in use\n"); 592 return; 593 } 594 595 left = min(BCM_SDHCI_BUFFER_SIZE, 596 slot->curcmd->data->len - slot->offset); 597 598 KASSERT((left & 3) == 0, 599 ("%s: len = %zu, not word-aligned", __func__, left)); 600 601 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 602 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 603 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 604 sc->dmamap_status != 0) { 605 slot->curcmd->error = MMC_ERR_NO_MEMORY; 606 return; 607 } 608 609 /* DMA start */ 610 bcm_sdhci_start_dma_seg(sc); 611 } 612 613 static int 614 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 615 { 616 size_t left; 617 618 /* 619 * Do not use DMA for transfers less than block size or with a length 620 * that is not a multiple of four. 621 */ 622 left = min(BCM_DMA_BLOCK_SIZE, 623 slot->curcmd->data->len - slot->offset); 624 if (left < BCM_DMA_BLOCK_SIZE) 625 return (0); 626 if (left & 0x03) 627 return (0); 628 629 return (1); 630 } 631 632 static void 633 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 634 uint32_t *intmask) 635 { 636 637 /* DMA transfer FIFO 1KB */ 638 if (slot->curcmd->data->flags & MMC_DATA_READ) 639 bcm_sdhci_read_dma(dev, slot); 640 else 641 bcm_sdhci_write_dma(dev, slot); 642 } 643 644 static void 645 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 646 { 647 648 sdhci_finish_data(slot); 649 } 650 651 static device_method_t bcm_sdhci_methods[] = { 652 /* Device interface */ 653 DEVMETHOD(device_probe, bcm_sdhci_probe), 654 DEVMETHOD(device_attach, bcm_sdhci_attach), 655 DEVMETHOD(device_detach, bcm_sdhci_detach), 656 657 /* Bus interface */ 658 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 659 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 660 661 /* MMC bridge interface */ 662 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 663 DEVMETHOD(mmcbr_request, sdhci_generic_request), 664 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 665 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 666 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 667 668 /* Platform transfer methods */ 669 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 670 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 671 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 672 /* SDHCI registers accessors */ 673 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 674 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 675 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 676 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 677 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 678 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 679 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 680 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 681 682 DEVMETHOD_END 683 }; 684 685 static devclass_t bcm_sdhci_devclass; 686 687 static driver_t bcm_sdhci_driver = { 688 "sdhci_bcm", 689 bcm_sdhci_methods, 690 sizeof(struct bcm_sdhci_softc), 691 }; 692 693 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 694 NULL, NULL); 695 SDHCI_DEPEND(sdhci_bcm); 696 #ifndef MMCCAM 697 MMC_DECLARE_BRIDGE(sdhci_bcm); 698 #endif 699