1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bio.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/kthread.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/queue.h> 43 #include <sys/resource.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 #include <sys/time.h> 48 #include <sys/timetc.h> 49 #include <sys/watchdog.h> 50 51 #include <sys/kdb.h> 52 53 #include <machine/bus.h> 54 #include <machine/cpu.h> 55 #include <machine/cpufunc.h> 56 #include <machine/resource.h> 57 #include <machine/intr.h> 58 59 #include <dev/fdt/fdt_common.h> 60 #include <dev/ofw/ofw_bus.h> 61 #include <dev/ofw/ofw_bus_subr.h> 62 63 #include <dev/mmc/bridge.h> 64 #include <dev/mmc/mmcreg.h> 65 #include <dev/mmc/mmcbrvar.h> 66 67 #include <dev/sdhci/sdhci.h> 68 #include "sdhci_if.h" 69 70 #include "bcm2835_dma.h" 71 #include "bcm2835_vcbus.h" 72 73 #define BCM2835_DEFAULT_SDHCI_FREQ 50 74 75 #define BCM_SDHCI_BUFFER_SIZE 512 76 #define NUM_DMA_SEGS 2 77 78 #ifdef DEBUG 79 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 80 printf(fmt,##args); } while (0) 81 #else 82 #define dprintf(fmt, args...) 83 #endif 84 85 /* 86 * Arasan HC seems to have problem with Data CRC on lower frequencies. 87 * Use this tunable to cap initialization sequence frequency at higher 88 * value. Default is standard 400kHz. 89 * HS mode brings too many problems for most of cards, so disable HS mode 90 * until a better fix comes up. 91 * HS mode still can be enabled with the tunable. 92 */ 93 static int bcm2835_sdhci_min_freq = 400000; 94 static int bcm2835_sdhci_hs = 1; 95 static int bcm2835_sdhci_pio_mode = 0; 96 97 TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); 98 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 99 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 100 101 struct bcm_sdhci_softc { 102 device_t sc_dev; 103 struct mtx sc_mtx; 104 struct resource * sc_mem_res; 105 struct resource * sc_irq_res; 106 bus_space_tag_t sc_bst; 107 bus_space_handle_t sc_bsh; 108 void * sc_intrhand; 109 struct mmc_request * sc_req; 110 struct mmc_data * sc_data; 111 uint32_t sc_flags; 112 #define LPC_SD_FLAGS_IGNORECRC (1 << 0) 113 int sc_xfer_direction; 114 #define DIRECTION_READ 0 115 #define DIRECTION_WRITE 1 116 int sc_xfer_done; 117 int sc_bus_busy; 118 struct sdhci_slot sc_slot; 119 int sc_dma_inuse; 120 int sc_dma_ch; 121 bus_dma_tag_t sc_dma_tag; 122 bus_dmamap_t sc_dma_map; 123 vm_paddr_t sc_sdhci_buffer_phys; 124 uint32_t cmd_and_mode; 125 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 126 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 127 int dmamap_seg_count; 128 int dmamap_seg_index; 129 int dmamap_status; 130 }; 131 132 static int bcm_sdhci_probe(device_t); 133 static int bcm_sdhci_attach(device_t); 134 static int bcm_sdhci_detach(device_t); 135 static void bcm_sdhci_intr(void *); 136 137 static int bcm_sdhci_get_ro(device_t, device_t); 138 static void bcm_sdhci_dma_intr(int ch, void *arg); 139 140 #define bcm_sdhci_lock(_sc) \ 141 mtx_lock(&_sc->sc_mtx); 142 #define bcm_sdhci_unlock(_sc) \ 143 mtx_unlock(&_sc->sc_mtx); 144 145 static void 146 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 147 { 148 struct bcm_sdhci_softc *sc = arg; 149 int i; 150 151 sc->dmamap_status = err; 152 sc->dmamap_seg_count = nseg; 153 154 /* Note nseg is guaranteed to be zero if err is non-zero. */ 155 for (i = 0; i < nseg; i++) { 156 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 157 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 158 } 159 } 160 161 static int 162 bcm_sdhci_probe(device_t dev) 163 { 164 165 if (!ofw_bus_status_okay(dev)) 166 return (ENXIO); 167 168 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 169 return (ENXIO); 170 171 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 172 return (BUS_PROBE_DEFAULT); 173 } 174 175 static int 176 bcm_sdhci_attach(device_t dev) 177 { 178 struct bcm_sdhci_softc *sc = device_get_softc(dev); 179 int rid, err; 180 phandle_t node; 181 pcell_t cell; 182 int default_freq; 183 184 sc->sc_dev = dev; 185 sc->sc_req = NULL; 186 err = 0; 187 188 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 189 node = ofw_bus_get_node(sc->sc_dev); 190 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) 191 default_freq = (int)fdt32_to_cpu(cell)/1000000; 192 193 dprintf("SDHCI frequency: %dMHz\n", default_freq); 194 195 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 196 197 rid = 0; 198 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 199 RF_ACTIVE); 200 if (!sc->sc_mem_res) { 201 device_printf(dev, "cannot allocate memory window\n"); 202 err = ENXIO; 203 goto fail; 204 } 205 206 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 207 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 208 209 rid = 0; 210 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 211 RF_ACTIVE); 212 if (!sc->sc_irq_res) { 213 device_printf(dev, "cannot allocate interrupt\n"); 214 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 215 err = ENXIO; 216 goto fail; 217 } 218 219 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 220 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) 221 { 222 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 223 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 224 device_printf(dev, "cannot setup interrupt handler\n"); 225 err = ENXIO; 226 goto fail; 227 } 228 229 if (!bcm2835_sdhci_pio_mode) 230 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 231 232 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 233 if (bcm2835_sdhci_hs) 234 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 235 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 236 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 237 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 238 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 239 | SDHCI_QUIRK_MISSING_CAPS; 240 241 sdhci_init_slot(dev, &sc->sc_slot, 0); 242 243 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 244 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 245 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 246 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 247 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 248 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 249 goto fail; 250 251 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 252 253 /* Allocate bus_dma resources. */ 254 err = bus_dma_tag_create(bus_get_dma_tag(dev), 255 1, 0, BUS_SPACE_MAXADDR_32BIT, 256 BUS_SPACE_MAXADDR, NULL, NULL, 257 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 258 BUS_DMA_ALLOCNOW, NULL, NULL, 259 &sc->sc_dma_tag); 260 261 if (err) { 262 device_printf(dev, "failed allocate DMA tag"); 263 goto fail; 264 } 265 266 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 267 if (err) { 268 device_printf(dev, "bus_dmamap_create failed\n"); 269 goto fail; 270 } 271 272 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 273 SDHCI_BUFFER); 274 275 bus_generic_probe(dev); 276 bus_generic_attach(dev); 277 278 sdhci_start_slot(&sc->sc_slot); 279 280 return (0); 281 282 fail: 283 if (sc->sc_intrhand) 284 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 285 if (sc->sc_irq_res) 286 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 287 if (sc->sc_mem_res) 288 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 289 290 return (err); 291 } 292 293 static int 294 bcm_sdhci_detach(device_t dev) 295 { 296 297 return (EBUSY); 298 } 299 300 static void 301 bcm_sdhci_intr(void *arg) 302 { 303 struct bcm_sdhci_softc *sc = arg; 304 305 sdhci_generic_intr(&sc->sc_slot); 306 } 307 308 static int 309 bcm_sdhci_get_ro(device_t bus, device_t child) 310 { 311 312 return (0); 313 } 314 315 static inline uint32_t 316 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 317 { 318 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 319 return val; 320 } 321 322 static inline void 323 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 324 { 325 326 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 327 /* 328 * The Arasan HC has a bug where it may lose the content of 329 * consecutive writes to registers that are within two SD-card 330 * clock cycles of each other (a clock domain crossing problem). 331 */ 332 if (sc->sc_slot.clock > 0) 333 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 334 } 335 336 static uint8_t 337 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 338 { 339 struct bcm_sdhci_softc *sc = device_get_softc(dev); 340 uint32_t val = RD4(sc, off & ~3); 341 342 return ((val >> (off & 3)*8) & 0xff); 343 } 344 345 static uint16_t 346 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 347 { 348 struct bcm_sdhci_softc *sc = device_get_softc(dev); 349 uint32_t val = RD4(sc, off & ~3); 350 351 /* 352 * Standard 32-bit handling of command and transfer mode. 353 */ 354 if (off == SDHCI_TRANSFER_MODE) { 355 return (sc->cmd_and_mode >> 16); 356 } else if (off == SDHCI_COMMAND_FLAGS) { 357 return (sc->cmd_and_mode & 0x0000ffff); 358 } 359 return ((val >> (off & 3)*8) & 0xffff); 360 } 361 362 static uint32_t 363 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 364 { 365 struct bcm_sdhci_softc *sc = device_get_softc(dev); 366 367 return RD4(sc, off); 368 } 369 370 static void 371 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 372 uint32_t *data, bus_size_t count) 373 { 374 struct bcm_sdhci_softc *sc = device_get_softc(dev); 375 376 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 377 } 378 379 static void 380 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 381 { 382 struct bcm_sdhci_softc *sc = device_get_softc(dev); 383 uint32_t val32 = RD4(sc, off & ~3); 384 val32 &= ~(0xff << (off & 3)*8); 385 val32 |= (val << (off & 3)*8); 386 WR4(sc, off & ~3, val32); 387 } 388 389 static void 390 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 391 { 392 struct bcm_sdhci_softc *sc = device_get_softc(dev); 393 uint32_t val32; 394 if (off == SDHCI_COMMAND_FLAGS) 395 val32 = sc->cmd_and_mode; 396 else 397 val32 = RD4(sc, off & ~3); 398 val32 &= ~(0xffff << (off & 3)*8); 399 val32 |= (val << (off & 3)*8); 400 if (off == SDHCI_TRANSFER_MODE) 401 sc->cmd_and_mode = val32; 402 else { 403 WR4(sc, off & ~3, val32); 404 if (off == SDHCI_COMMAND_FLAGS) 405 sc->cmd_and_mode = val32; 406 } 407 } 408 409 static void 410 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 411 { 412 struct bcm_sdhci_softc *sc = device_get_softc(dev); 413 WR4(sc, off, val); 414 } 415 416 static void 417 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 418 uint32_t *data, bus_size_t count) 419 { 420 struct bcm_sdhci_softc *sc = device_get_softc(dev); 421 422 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 423 } 424 425 static uint32_t 426 bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot) 427 { 428 429 return bcm2835_sdhci_min_freq; 430 } 431 432 static void 433 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 434 { 435 struct sdhci_slot *slot; 436 vm_paddr_t pdst, psrc; 437 int err, idx, len, sync_op; 438 439 slot = &sc->sc_slot; 440 idx = sc->dmamap_seg_index++; 441 len = sc->dmamap_seg_sizes[idx]; 442 slot->offset += len; 443 444 if (slot->curcmd->data->flags & MMC_DATA_READ) { 445 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 446 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 447 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 448 BCM_DMA_INC_ADDR, 449 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 450 psrc = sc->sc_sdhci_buffer_phys; 451 pdst = sc->dmamap_seg_addrs[idx]; 452 sync_op = BUS_DMASYNC_PREREAD; 453 } else { 454 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 455 BCM_DMA_INC_ADDR, 456 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 457 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 458 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 459 psrc = sc->dmamap_seg_addrs[idx]; 460 pdst = sc->sc_sdhci_buffer_phys; 461 sync_op = BUS_DMASYNC_PREWRITE; 462 } 463 464 /* 465 * When starting a new DMA operation do the busdma sync operation, and 466 * disable SDCHI data interrrupts because we'll be driven by DMA 467 * interrupts (or SDHCI error interrupts) until the IO is done. 468 */ 469 if (idx == 0) { 470 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 471 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 472 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 473 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 474 slot->intmask); 475 } 476 477 /* 478 * Start the DMA transfer. Only programming errors (like failing to 479 * allocate a channel) cause a non-zero return from bcm_dma_start(). 480 */ 481 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 482 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 483 } 484 485 static void 486 bcm_sdhci_dma_intr(int ch, void *arg) 487 { 488 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 489 struct sdhci_slot *slot = &sc->sc_slot; 490 uint32_t reg, mask; 491 int left, sync_op; 492 493 mtx_lock(&slot->mtx); 494 495 /* 496 * If there are more segments for the current dma, start the next one. 497 * Otherwise unload the dma map and decide what to do next based on the 498 * status of the sdhci controller and whether there's more data left. 499 */ 500 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 501 bcm_sdhci_start_dma_seg(sc); 502 mtx_unlock(&slot->mtx); 503 return; 504 } 505 506 if (slot->curcmd->data->flags & MMC_DATA_READ) { 507 sync_op = BUS_DMASYNC_POSTREAD; 508 mask = SDHCI_INT_DATA_AVAIL; 509 } else { 510 sync_op = BUS_DMASYNC_POSTWRITE; 511 mask = SDHCI_INT_SPACE_AVAIL; 512 } 513 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 514 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 515 516 sc->dmamap_seg_count = 0; 517 sc->dmamap_seg_index = 0; 518 519 left = min(BCM_SDHCI_BUFFER_SIZE, 520 slot->curcmd->data->len - slot->offset); 521 522 /* DATA END? */ 523 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 524 525 if (reg & SDHCI_INT_DATA_END) { 526 /* ACK for all outstanding interrupts */ 527 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 528 529 /* enable INT */ 530 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 531 | SDHCI_INT_DATA_END; 532 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 533 slot->intmask); 534 535 /* finish this data */ 536 sdhci_finish_data(slot); 537 } 538 else { 539 /* already available? */ 540 if (reg & mask) { 541 542 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 543 bcm_sdhci_write_4(slot->bus, slot, 544 SDHCI_INT_STATUS, mask); 545 546 /* continue next DMA transfer */ 547 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 548 (uint8_t *)slot->curcmd->data->data + 549 slot->offset, left, bcm_sdhci_dmacb, sc, 550 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 551 slot->curcmd->error = MMC_ERR_NO_MEMORY; 552 sdhci_finish_data(slot); 553 } else { 554 bcm_sdhci_start_dma_seg(sc); 555 } 556 } else { 557 /* wait for next data by INT */ 558 559 /* enable INT */ 560 slot->intmask |= SDHCI_INT_DATA_AVAIL | 561 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 562 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 563 slot->intmask); 564 } 565 } 566 567 mtx_unlock(&slot->mtx); 568 } 569 570 static void 571 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 572 { 573 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 574 size_t left; 575 576 if (sc->dmamap_seg_count != 0) { 577 device_printf(sc->sc_dev, "DMA in use\n"); 578 return; 579 } 580 581 left = min(BCM_SDHCI_BUFFER_SIZE, 582 slot->curcmd->data->len - slot->offset); 583 584 KASSERT((left & 3) == 0, 585 ("%s: len = %d, not word-aligned", __func__, left)); 586 587 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 588 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 589 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 590 sc->dmamap_status != 0) { 591 slot->curcmd->error = MMC_ERR_NO_MEMORY; 592 return; 593 } 594 595 /* DMA start */ 596 bcm_sdhci_start_dma_seg(sc); 597 } 598 599 static void 600 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 601 { 602 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 603 size_t left; 604 605 if (sc->dmamap_seg_count != 0) { 606 device_printf(sc->sc_dev, "DMA in use\n"); 607 return; 608 } 609 610 left = min(BCM_SDHCI_BUFFER_SIZE, 611 slot->curcmd->data->len - slot->offset); 612 613 KASSERT((left & 3) == 0, 614 ("%s: len = %d, not word-aligned", __func__, left)); 615 616 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 617 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 618 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 619 sc->dmamap_status != 0) { 620 slot->curcmd->error = MMC_ERR_NO_MEMORY; 621 return; 622 } 623 624 /* DMA start */ 625 bcm_sdhci_start_dma_seg(sc); 626 } 627 628 static int 629 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 630 { 631 size_t left; 632 633 /* 634 * Do not use DMA for transfers less than block size or with a length 635 * that is not a multiple of four. 636 */ 637 left = min(BCM_DMA_BLOCK_SIZE, 638 slot->curcmd->data->len - slot->offset); 639 if (left < BCM_DMA_BLOCK_SIZE) 640 return (0); 641 if (left & 0x03) 642 return (0); 643 644 return (1); 645 } 646 647 static void 648 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 649 uint32_t *intmask) 650 { 651 652 /* DMA transfer FIFO 1KB */ 653 if (slot->curcmd->data->flags & MMC_DATA_READ) 654 bcm_sdhci_read_dma(dev, slot); 655 else 656 bcm_sdhci_write_dma(dev, slot); 657 } 658 659 static void 660 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 661 { 662 663 sdhci_finish_data(slot); 664 } 665 666 static device_method_t bcm_sdhci_methods[] = { 667 /* Device interface */ 668 DEVMETHOD(device_probe, bcm_sdhci_probe), 669 DEVMETHOD(device_attach, bcm_sdhci_attach), 670 DEVMETHOD(device_detach, bcm_sdhci_detach), 671 672 /* Bus interface */ 673 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 674 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 675 DEVMETHOD(bus_print_child, bus_generic_print_child), 676 677 /* MMC bridge interface */ 678 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 679 DEVMETHOD(mmcbr_request, sdhci_generic_request), 680 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 681 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 682 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 683 684 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq), 685 /* Platform transfer methods */ 686 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 687 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 688 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 689 /* SDHCI registers accessors */ 690 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 691 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 692 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 693 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 694 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 695 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 696 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 697 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 698 699 { 0, 0 } 700 }; 701 702 static devclass_t bcm_sdhci_devclass; 703 704 static driver_t bcm_sdhci_driver = { 705 "sdhci_bcm", 706 bcm_sdhci_methods, 707 sizeof(struct bcm_sdhci_softc), 708 }; 709 710 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 711 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 712