1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <sys/taskqueue.h> 43 44 #include <machine/bus.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcreg.h> 51 52 #include <dev/sdhci/sdhci.h> 53 54 #include "mmcbr_if.h" 55 #include "sdhci_if.h" 56 57 #include "opt_mmccam.h" 58 59 #include "bcm2835_dma.h" 60 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 61 #ifdef NOTYET 62 #include <arm/broadcom/bcm2835/bcm2835_clkman.h> 63 #endif 64 65 #define BCM2835_DEFAULT_SDHCI_FREQ 50 66 #define BCM2838_DEFAULT_SDHCI_FREQ 100 67 68 #define BCM_SDHCI_BUFFER_SIZE 512 69 #define NUM_DMA_SEGS 2 70 71 #ifdef DEBUG 72 static int bcm2835_sdhci_debug = 0; 73 74 TUNABLE_INT("hw.bcm2835.sdhci.debug", &bcm2835_sdhci_debug); 75 SYSCTL_INT(_hw_sdhci, OID_AUTO, bcm2835_sdhci_debug, CTLFLAG_RWTUN, 76 &bcm2835_sdhci_debug, 0, "bcm2835 SDHCI debug level"); 77 78 #define dprintf(fmt, args...) \ 79 do { \ 80 if (bcm2835_sdhci_debug) \ 81 printf("%s: " fmt, __func__, ##args); \ 82 } while (0) 83 #else 84 #define dprintf(fmt, args...) 85 #endif 86 87 static int bcm2835_sdhci_hs = 1; 88 static int bcm2835_sdhci_pio_mode = 0; 89 90 struct bcm_mmc_conf { 91 int clock_id; 92 int clock_src; 93 int default_freq; 94 int quirks; 95 bool use_dma; 96 }; 97 98 struct bcm_mmc_conf bcm2835_sdhci_conf = { 99 .clock_id = BCM2835_MBOX_CLOCK_ID_EMMC, 100 .clock_src = -1, 101 .default_freq = BCM2835_DEFAULT_SDHCI_FREQ, 102 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 103 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DONT_SET_HISPD_BIT | 104 SDHCI_QUIRK_MISSING_CAPS, 105 .use_dma = true 106 }; 107 108 struct bcm_mmc_conf bcm2838_emmc2_conf = { 109 .clock_id = BCM2838_MBOX_CLOCK_ID_EMMC2, 110 .clock_src = -1, 111 .default_freq = BCM2838_DEFAULT_SDHCI_FREQ, 112 .quirks = 0, 113 /* XXX DMA is currently broken, but it shouldn't be. */ 114 .use_dma = false 115 }; 116 117 static struct ofw_compat_data compat_data[] = { 118 {"broadcom,bcm2835-sdhci", (uintptr_t)&bcm2835_sdhci_conf}, 119 {"brcm,bcm2835-sdhci", (uintptr_t)&bcm2835_sdhci_conf}, 120 {"brcm,bcm2835-mmc", (uintptr_t)&bcm2835_sdhci_conf}, 121 {"brcm,bcm2711-emmc2", (uintptr_t)&bcm2838_emmc2_conf}, 122 {"brcm,bcm2838-emmc2", (uintptr_t)&bcm2838_emmc2_conf}, 123 {NULL, 0} 124 }; 125 126 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 127 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 128 129 struct bcm_sdhci_softc { 130 device_t sc_dev; 131 struct resource * sc_mem_res; 132 struct resource * sc_irq_res; 133 bus_space_tag_t sc_bst; 134 bus_space_handle_t sc_bsh; 135 void * sc_intrhand; 136 struct mmc_request * sc_req; 137 struct sdhci_slot sc_slot; 138 int sc_dma_ch; 139 bus_dma_tag_t sc_dma_tag; 140 bus_dmamap_t sc_dma_map; 141 vm_paddr_t sc_sdhci_buffer_phys; 142 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 143 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 144 int dmamap_seg_count; 145 int dmamap_seg_index; 146 int dmamap_status; 147 uint32_t blksz_and_count; 148 uint32_t cmd_and_mode; 149 bool need_update_blk; 150 #ifdef NOTYET 151 device_t clkman; 152 #endif 153 struct bcm_mmc_conf * conf; 154 }; 155 156 static int bcm_sdhci_probe(device_t); 157 static int bcm_sdhci_attach(device_t); 158 static int bcm_sdhci_detach(device_t); 159 static void bcm_sdhci_intr(void *); 160 161 static int bcm_sdhci_get_ro(device_t, device_t); 162 static void bcm_sdhci_dma_intr(int ch, void *arg); 163 164 static void 165 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 166 { 167 struct bcm_sdhci_softc *sc = arg; 168 int i; 169 170 sc->dmamap_status = err; 171 sc->dmamap_seg_count = nseg; 172 173 /* Note nseg is guaranteed to be zero if err is non-zero. */ 174 for (i = 0; i < nseg; i++) { 175 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 176 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 177 } 178 } 179 180 static int 181 bcm_sdhci_probe(device_t dev) 182 { 183 184 if (!ofw_bus_status_okay(dev)) 185 return (ENXIO); 186 187 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 188 return (ENXIO); 189 190 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 191 192 return (BUS_PROBE_DEFAULT); 193 } 194 195 static int 196 bcm_sdhci_attach(device_t dev) 197 { 198 struct bcm_sdhci_softc *sc = device_get_softc(dev); 199 int rid, err; 200 phandle_t node; 201 pcell_t cell; 202 u_int default_freq; 203 204 sc->sc_dev = dev; 205 sc->sc_req = NULL; 206 207 sc->conf = (struct bcm_mmc_conf *)ofw_bus_search_compatible(dev, 208 compat_data)->ocd_data; 209 if (sc->conf == 0) 210 return (ENXIO); 211 212 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, TRUE); 213 if (err != 0) { 214 if (bootverbose) 215 device_printf(dev, "Unable to enable the power\n"); 216 return (err); 217 } 218 219 default_freq = 0; 220 err = bcm2835_mbox_get_clock_rate(sc->conf->clock_id, &default_freq); 221 if (err == 0) { 222 /* Convert to MHz */ 223 default_freq /= 1000000; 224 } 225 if (default_freq == 0) { 226 node = ofw_bus_get_node(sc->sc_dev); 227 if ((OF_getencprop(node, "clock-frequency", &cell, 228 sizeof(cell))) > 0) 229 default_freq = cell / 1000000; 230 } 231 if (default_freq == 0) 232 default_freq = sc->conf->default_freq; 233 234 if (bootverbose) 235 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 236 #ifdef NOTYET 237 if (sc->conf->clock_src > 0) { 238 uint32_t f; 239 sc->clkman = devclass_get_device(devclass_find("bcm2835_clkman"), 0); 240 if (sc->clkman == NULL) { 241 device_printf(dev, "cannot find Clock Manager\n"); 242 return (ENXIO); 243 } 244 245 f = bcm2835_clkman_set_frequency(sc->clkman, sc->conf->clock_src, default_freq); 246 if (f == 0) 247 return (EINVAL); 248 249 if (bootverbose) 250 device_printf(dev, "Clock source frequency: %dMHz\n", f); 251 } 252 #endif 253 254 rid = 0; 255 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 256 RF_ACTIVE); 257 if (!sc->sc_mem_res) { 258 device_printf(dev, "cannot allocate memory window\n"); 259 err = ENXIO; 260 goto fail; 261 } 262 263 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 264 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 265 266 rid = 0; 267 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 268 RF_ACTIVE | RF_SHAREABLE); 269 if (!sc->sc_irq_res) { 270 device_printf(dev, "cannot allocate interrupt\n"); 271 err = ENXIO; 272 goto fail; 273 } 274 275 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 276 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 277 device_printf(dev, "cannot setup interrupt handler\n"); 278 err = ENXIO; 279 goto fail; 280 } 281 282 if (!bcm2835_sdhci_pio_mode) 283 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 284 285 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 286 if (bcm2835_sdhci_hs) 287 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 288 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 289 sc->sc_slot.quirks = sc->conf->quirks; 290 291 sdhci_init_slot(dev, &sc->sc_slot, 0); 292 293 if (sc->conf->use_dma) { 294 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 295 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 296 goto fail; 297 298 if (bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc) != 0) { 299 device_printf(dev, "cannot setup dma interrupt handler\n"); 300 err = ENXIO; 301 goto fail; 302 } 303 304 /* Allocate bus_dma resources. */ 305 err = bus_dma_tag_create(bus_get_dma_tag(dev), 306 1, 0, BUS_SPACE_MAXADDR_32BIT, 307 BUS_SPACE_MAXADDR, NULL, NULL, 308 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 309 BUS_DMA_ALLOCNOW, NULL, NULL, 310 &sc->sc_dma_tag); 311 312 if (err) { 313 device_printf(dev, "failed allocate DMA tag"); 314 goto fail; 315 } 316 317 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 318 if (err) { 319 device_printf(dev, "bus_dmamap_create failed\n"); 320 goto fail; 321 } 322 } 323 324 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ 325 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + 326 SDHCI_BUFFER; 327 328 bus_generic_probe(dev); 329 bus_generic_attach(dev); 330 331 sdhci_start_slot(&sc->sc_slot); 332 333 /* Seed our copies. */ 334 sc->blksz_and_count = SDHCI_READ_4(dev, &sc->sc_slot, SDHCI_BLOCK_SIZE); 335 sc->cmd_and_mode = SDHCI_READ_4(dev, &sc->sc_slot, SDHCI_TRANSFER_MODE); 336 337 return (0); 338 339 fail: 340 if (sc->sc_intrhand) 341 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 342 if (sc->sc_irq_res) 343 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 344 if (sc->sc_mem_res) 345 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 346 347 return (err); 348 } 349 350 static int 351 bcm_sdhci_detach(device_t dev) 352 { 353 354 return (EBUSY); 355 } 356 357 static void 358 bcm_sdhci_intr(void *arg) 359 { 360 struct bcm_sdhci_softc *sc = arg; 361 362 sdhci_generic_intr(&sc->sc_slot); 363 } 364 365 static int 366 bcm_sdhci_get_ro(device_t bus, device_t child) 367 { 368 369 return (0); 370 } 371 372 static inline uint32_t 373 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 374 { 375 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 376 return val; 377 } 378 379 static inline void 380 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 381 { 382 383 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 384 /* 385 * The Arasan HC has a bug where it may lose the content of 386 * consecutive writes to registers that are within two SD-card 387 * clock cycles of each other (a clock domain crossing problem). 388 */ 389 if (sc->sc_slot.clock > 0) 390 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 391 } 392 393 static uint8_t 394 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 395 { 396 struct bcm_sdhci_softc *sc = device_get_softc(dev); 397 uint32_t val = RD4(sc, off & ~3); 398 399 return ((val >> (off & 3)*8) & 0xff); 400 } 401 402 static uint16_t 403 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 404 { 405 struct bcm_sdhci_softc *sc = device_get_softc(dev); 406 uint32_t val32; 407 408 /* 409 * Standard 32-bit handling of command and transfer mode, as 410 * well as block size and count. 411 */ 412 if ((off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) && 413 sc->need_update_blk) 414 val32 = sc->blksz_and_count; 415 else if (off == SDHCI_TRANSFER_MODE || off == SDHCI_COMMAND_FLAGS) 416 val32 = sc->cmd_and_mode; 417 else 418 val32 = RD4(sc, off & ~3); 419 420 return ((val32 >> (off & 3)*8) & 0xffff); 421 } 422 423 static uint32_t 424 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 425 { 426 struct bcm_sdhci_softc *sc = device_get_softc(dev); 427 428 return RD4(sc, off); 429 } 430 431 static void 432 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 433 uint32_t *data, bus_size_t count) 434 { 435 struct bcm_sdhci_softc *sc = device_get_softc(dev); 436 437 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 438 } 439 440 static void 441 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 442 { 443 struct bcm_sdhci_softc *sc = device_get_softc(dev); 444 uint32_t val32 = RD4(sc, off & ~3); 445 val32 &= ~(0xff << (off & 3)*8); 446 val32 |= (val << (off & 3)*8); 447 WR4(sc, off & ~3, val32); 448 } 449 450 static void 451 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 452 { 453 struct bcm_sdhci_softc *sc = device_get_softc(dev); 454 uint32_t val32; 455 456 /* 457 * If we have a queued up 16bit value for blk size or count, use and 458 * update the saved value rather than doing any real register access. 459 * If we did not touch either since the last write, then read from 460 * register as at least block count can change. 461 * Similarly, if we are about to issue a command, always use the saved 462 * value for transfer mode as we can never write that without issuing 463 * a command. 464 */ 465 if ((off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) && 466 sc->need_update_blk) 467 val32 = sc->blksz_and_count; 468 else if (off == SDHCI_COMMAND_FLAGS) 469 val32 = sc->cmd_and_mode; 470 else 471 val32 = RD4(sc, off & ~3); 472 473 val32 &= ~(0xffff << (off & 3)*8); 474 val32 |= (val << (off & 3)*8); 475 476 if (off == SDHCI_TRANSFER_MODE) 477 sc->cmd_and_mode = val32; 478 else if (off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) { 479 sc->blksz_and_count = val32; 480 sc->need_update_blk = true; 481 } else { 482 if (off == SDHCI_COMMAND_FLAGS) { 483 /* If we saved blk writes, do them now before cmd. */ 484 if (sc->need_update_blk) { 485 WR4(sc, SDHCI_BLOCK_SIZE, sc->blksz_and_count); 486 sc->need_update_blk = false; 487 } 488 /* Always save cmd and mode registers. */ 489 sc->cmd_and_mode = val32; 490 } 491 WR4(sc, off & ~3, val32); 492 } 493 } 494 495 static void 496 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 497 { 498 struct bcm_sdhci_softc *sc = device_get_softc(dev); 499 WR4(sc, off, val); 500 } 501 502 static void 503 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 504 uint32_t *data, bus_size_t count) 505 { 506 struct bcm_sdhci_softc *sc = device_get_softc(dev); 507 508 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 509 } 510 511 static void 512 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 513 { 514 struct sdhci_slot *slot; 515 vm_paddr_t pdst, psrc; 516 int err, idx, len, sync_op, width; 517 518 slot = &sc->sc_slot; 519 idx = sc->dmamap_seg_index++; 520 len = sc->dmamap_seg_sizes[idx]; 521 slot->offset += len; 522 width = (len & 0xf ? BCM_DMA_32BIT : BCM_DMA_128BIT); 523 524 if (slot->curcmd->data->flags & MMC_DATA_READ) { 525 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 526 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 527 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 528 BCM_DMA_INC_ADDR, width); 529 psrc = sc->sc_sdhci_buffer_phys; 530 pdst = sc->dmamap_seg_addrs[idx]; 531 sync_op = BUS_DMASYNC_PREREAD; 532 } else { 533 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 534 BCM_DMA_INC_ADDR, width); 535 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 536 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 537 psrc = sc->dmamap_seg_addrs[idx]; 538 pdst = sc->sc_sdhci_buffer_phys; 539 sync_op = BUS_DMASYNC_PREWRITE; 540 } 541 542 /* 543 * When starting a new DMA operation do the busdma sync operation, and 544 * disable SDCHI data interrrupts because we'll be driven by DMA 545 * interrupts (or SDHCI error interrupts) until the IO is done. 546 */ 547 if (idx == 0) { 548 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 549 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 550 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 551 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 552 slot->intmask); 553 } 554 555 /* 556 * Start the DMA transfer. Only programming errors (like failing to 557 * allocate a channel) cause a non-zero return from bcm_dma_start(). 558 */ 559 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 560 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 561 } 562 563 static void 564 bcm_sdhci_dma_intr(int ch, void *arg) 565 { 566 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 567 struct sdhci_slot *slot = &sc->sc_slot; 568 uint32_t reg, mask; 569 int left, sync_op; 570 571 mtx_lock(&slot->mtx); 572 573 if (slot->curcmd == NULL) { 574 mtx_unlock(&slot->mtx); 575 device_printf(sc->sc_dev, 576 "command aborted in the middle of DMA\n"); 577 return; 578 } 579 580 /* 581 * If there are more segments for the current dma, start the next one. 582 * Otherwise unload the dma map and decide what to do next based on the 583 * status of the sdhci controller and whether there's more data left. 584 */ 585 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 586 bcm_sdhci_start_dma_seg(sc); 587 mtx_unlock(&slot->mtx); 588 return; 589 } 590 591 if (slot->curcmd->data->flags & MMC_DATA_READ) { 592 sync_op = BUS_DMASYNC_POSTREAD; 593 mask = SDHCI_INT_DATA_AVAIL; 594 } else { 595 sync_op = BUS_DMASYNC_POSTWRITE; 596 mask = SDHCI_INT_SPACE_AVAIL; 597 } 598 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 599 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 600 601 sc->dmamap_seg_count = 0; 602 sc->dmamap_seg_index = 0; 603 604 left = min(BCM_SDHCI_BUFFER_SIZE, 605 slot->curcmd->data->len - slot->offset); 606 607 /* 608 * If there is less than buffer size outstanding, we would not handle 609 * it anymore using DMA if bcm_sdhci_will_handle_transfer() were asked. 610 * Re-enable interrupts and return and let the SDHCI state machine 611 * finish the job. 612 */ 613 if (left < BCM_SDHCI_BUFFER_SIZE) { 614 /* Re-enable data interrupts. */ 615 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 616 SDHCI_INT_DATA_END; 617 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 618 slot->intmask); 619 mtx_unlock(&slot->mtx); 620 return; 621 } 622 623 /* DATA END? */ 624 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 625 626 if (reg & SDHCI_INT_DATA_END) { 627 /* ACK for all outstanding interrupts */ 628 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 629 630 /* enable INT */ 631 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 632 | SDHCI_INT_DATA_END; 633 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 634 slot->intmask); 635 636 /* finish this data */ 637 sdhci_finish_data(slot); 638 } 639 else { 640 /* already available? */ 641 if (reg & mask) { 642 643 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 644 bcm_sdhci_write_4(slot->bus, slot, 645 SDHCI_INT_STATUS, mask); 646 647 /* continue next DMA transfer */ 648 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 649 (uint8_t *)slot->curcmd->data->data + 650 slot->offset, left, bcm_sdhci_dmacb, sc, 651 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 652 slot->curcmd->error = MMC_ERR_NO_MEMORY; 653 sdhci_finish_data(slot); 654 } else { 655 bcm_sdhci_start_dma_seg(sc); 656 } 657 } else { 658 /* wait for next data by INT */ 659 660 /* enable INT */ 661 slot->intmask |= SDHCI_INT_DATA_AVAIL | 662 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 663 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 664 slot->intmask); 665 } 666 } 667 668 mtx_unlock(&slot->mtx); 669 } 670 671 static void 672 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 673 { 674 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 675 size_t left; 676 677 if (sc->dmamap_seg_count != 0) { 678 device_printf(sc->sc_dev, "DMA in use\n"); 679 return; 680 } 681 682 left = min(BCM_SDHCI_BUFFER_SIZE, 683 slot->curcmd->data->len - slot->offset); 684 685 KASSERT((left & 3) == 0, 686 ("%s: len = %zu, not word-aligned", __func__, left)); 687 688 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 689 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 690 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 691 sc->dmamap_status != 0) { 692 slot->curcmd->error = MMC_ERR_NO_MEMORY; 693 return; 694 } 695 696 /* DMA start */ 697 bcm_sdhci_start_dma_seg(sc); 698 } 699 700 static void 701 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 702 { 703 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 704 size_t left; 705 706 if (sc->dmamap_seg_count != 0) { 707 device_printf(sc->sc_dev, "DMA in use\n"); 708 return; 709 } 710 711 left = min(BCM_SDHCI_BUFFER_SIZE, 712 slot->curcmd->data->len - slot->offset); 713 714 KASSERT((left & 3) == 0, 715 ("%s: len = %zu, not word-aligned", __func__, left)); 716 717 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 718 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 719 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 720 sc->dmamap_status != 0) { 721 slot->curcmd->error = MMC_ERR_NO_MEMORY; 722 return; 723 } 724 725 /* DMA start */ 726 bcm_sdhci_start_dma_seg(sc); 727 } 728 729 static int 730 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 731 { 732 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 733 size_t left; 734 735 if (!sc->conf->use_dma) 736 return (0); 737 738 /* 739 * Do not use DMA for transfers less than block size or with a length 740 * that is not a multiple of four. 741 */ 742 left = min(BCM_DMA_BLOCK_SIZE, 743 slot->curcmd->data->len - slot->offset); 744 if (left < BCM_DMA_BLOCK_SIZE) 745 return (0); 746 if (left & 0x03) 747 return (0); 748 749 return (1); 750 } 751 752 static void 753 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 754 uint32_t *intmask) 755 { 756 757 /* DMA transfer FIFO 1KB */ 758 if (slot->curcmd->data->flags & MMC_DATA_READ) 759 bcm_sdhci_read_dma(dev, slot); 760 else 761 bcm_sdhci_write_dma(dev, slot); 762 } 763 764 static void 765 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 766 { 767 768 sdhci_finish_data(slot); 769 } 770 771 static device_method_t bcm_sdhci_methods[] = { 772 /* Device interface */ 773 DEVMETHOD(device_probe, bcm_sdhci_probe), 774 DEVMETHOD(device_attach, bcm_sdhci_attach), 775 DEVMETHOD(device_detach, bcm_sdhci_detach), 776 777 /* Bus interface */ 778 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 779 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 780 DEVMETHOD(bus_add_child, bus_generic_add_child), 781 782 /* MMC bridge interface */ 783 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 784 DEVMETHOD(mmcbr_request, sdhci_generic_request), 785 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 786 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 787 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 788 789 /* Platform transfer methods */ 790 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 791 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 792 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 793 /* SDHCI registers accessors */ 794 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 795 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 796 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 797 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 798 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 799 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 800 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 801 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 802 803 DEVMETHOD_END 804 }; 805 806 static devclass_t bcm_sdhci_devclass; 807 808 static driver_t bcm_sdhci_driver = { 809 "sdhci_bcm", 810 bcm_sdhci_methods, 811 sizeof(struct bcm_sdhci_softc), 812 }; 813 814 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 815 NULL, NULL); 816 #ifdef NOTYET 817 MODULE_DEPEND(sdhci_bcm, bcm2835_clkman, 1, 1, 1); 818 #endif 819 SDHCI_DEPEND(sdhci_bcm); 820 #ifndef MMCCAM 821 MMC_DECLARE_BRIDGE(sdhci_bcm); 822 #endif 823