1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/fdt/fdt_common.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/mmc/bridge.h> 49 #include <dev/mmc/mmcreg.h> 50 #include <dev/mmc/mmcbrvar.h> 51 52 #include <dev/sdhci/sdhci.h> 53 #include "sdhci_if.h" 54 55 #include "bcm2835_dma.h" 56 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 57 #include "bcm2835_vcbus.h" 58 59 #define BCM2835_DEFAULT_SDHCI_FREQ 50 60 61 #define BCM_SDHCI_BUFFER_SIZE 512 62 #define NUM_DMA_SEGS 2 63 64 #ifdef DEBUG 65 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define dprintf(fmt, args...) 69 #endif 70 71 static int bcm2835_sdhci_hs = 1; 72 static int bcm2835_sdhci_pio_mode = 0; 73 74 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 75 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 76 77 struct bcm_sdhci_softc { 78 device_t sc_dev; 79 struct resource * sc_mem_res; 80 struct resource * sc_irq_res; 81 bus_space_tag_t sc_bst; 82 bus_space_handle_t sc_bsh; 83 void * sc_intrhand; 84 struct mmc_request * sc_req; 85 struct sdhci_slot sc_slot; 86 int sc_dma_ch; 87 bus_dma_tag_t sc_dma_tag; 88 bus_dmamap_t sc_dma_map; 89 vm_paddr_t sc_sdhci_buffer_phys; 90 uint32_t cmd_and_mode; 91 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 92 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 93 int dmamap_seg_count; 94 int dmamap_seg_index; 95 int dmamap_status; 96 }; 97 98 static int bcm_sdhci_probe(device_t); 99 static int bcm_sdhci_attach(device_t); 100 static int bcm_sdhci_detach(device_t); 101 static void bcm_sdhci_intr(void *); 102 103 static int bcm_sdhci_get_ro(device_t, device_t); 104 static void bcm_sdhci_dma_intr(int ch, void *arg); 105 106 static void 107 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 108 { 109 struct bcm_sdhci_softc *sc = arg; 110 int i; 111 112 sc->dmamap_status = err; 113 sc->dmamap_seg_count = nseg; 114 115 /* Note nseg is guaranteed to be zero if err is non-zero. */ 116 for (i = 0; i < nseg; i++) { 117 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 118 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 119 } 120 } 121 122 static int 123 bcm_sdhci_probe(device_t dev) 124 { 125 126 if (!ofw_bus_status_okay(dev)) 127 return (ENXIO); 128 129 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 130 return (ENXIO); 131 132 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 133 return (BUS_PROBE_DEFAULT); 134 } 135 136 static int 137 bcm_sdhci_attach(device_t dev) 138 { 139 struct bcm_sdhci_softc *sc = device_get_softc(dev); 140 int rid, err; 141 phandle_t node; 142 pcell_t cell; 143 u_int default_freq; 144 145 sc->sc_dev = dev; 146 sc->sc_req = NULL; 147 148 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, 149 TRUE); 150 if (err != 0) { 151 if (bootverbose) 152 device_printf(dev, "Unable to enable the power\n"); 153 return (err); 154 } 155 156 default_freq = 0; 157 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, 158 &default_freq); 159 if (err == 0) { 160 /* Convert to MHz */ 161 default_freq /= 1000000; 162 } 163 if (default_freq == 0) { 164 node = ofw_bus_get_node(sc->sc_dev); 165 if ((OF_getencprop(node, "clock-frequency", &cell, 166 sizeof(cell))) > 0) 167 default_freq = cell / 1000000; 168 } 169 if (default_freq == 0) 170 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 171 172 if (bootverbose) 173 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 174 175 rid = 0; 176 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 177 RF_ACTIVE); 178 if (!sc->sc_mem_res) { 179 device_printf(dev, "cannot allocate memory window\n"); 180 err = ENXIO; 181 goto fail; 182 } 183 184 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 185 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 186 187 rid = 0; 188 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 189 RF_ACTIVE); 190 if (!sc->sc_irq_res) { 191 device_printf(dev, "cannot allocate interrupt\n"); 192 err = ENXIO; 193 goto fail; 194 } 195 196 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 197 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 198 device_printf(dev, "cannot setup interrupt handler\n"); 199 err = ENXIO; 200 goto fail; 201 } 202 203 if (!bcm2835_sdhci_pio_mode) 204 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 205 206 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 207 if (bcm2835_sdhci_hs) 208 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 209 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 210 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 211 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 212 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 213 | SDHCI_QUIRK_MISSING_CAPS; 214 215 sdhci_init_slot(dev, &sc->sc_slot, 0); 216 217 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 218 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 219 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 220 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 221 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 222 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 223 goto fail; 224 225 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 226 227 /* Allocate bus_dma resources. */ 228 err = bus_dma_tag_create(bus_get_dma_tag(dev), 229 1, 0, BUS_SPACE_MAXADDR_32BIT, 230 BUS_SPACE_MAXADDR, NULL, NULL, 231 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 232 BUS_DMA_ALLOCNOW, NULL, NULL, 233 &sc->sc_dma_tag); 234 235 if (err) { 236 device_printf(dev, "failed allocate DMA tag"); 237 goto fail; 238 } 239 240 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 241 if (err) { 242 device_printf(dev, "bus_dmamap_create failed\n"); 243 goto fail; 244 } 245 246 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 247 SDHCI_BUFFER); 248 249 bus_generic_probe(dev); 250 bus_generic_attach(dev); 251 252 sdhci_start_slot(&sc->sc_slot); 253 254 return (0); 255 256 fail: 257 if (sc->sc_intrhand) 258 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 259 if (sc->sc_irq_res) 260 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 261 if (sc->sc_mem_res) 262 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 263 264 return (err); 265 } 266 267 static int 268 bcm_sdhci_detach(device_t dev) 269 { 270 271 return (EBUSY); 272 } 273 274 static void 275 bcm_sdhci_intr(void *arg) 276 { 277 struct bcm_sdhci_softc *sc = arg; 278 279 sdhci_generic_intr(&sc->sc_slot); 280 } 281 282 static int 283 bcm_sdhci_get_ro(device_t bus, device_t child) 284 { 285 286 return (0); 287 } 288 289 static inline uint32_t 290 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 291 { 292 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 293 return val; 294 } 295 296 static inline void 297 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 298 { 299 300 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 301 /* 302 * The Arasan HC has a bug where it may lose the content of 303 * consecutive writes to registers that are within two SD-card 304 * clock cycles of each other (a clock domain crossing problem). 305 */ 306 if (sc->sc_slot.clock > 0) 307 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 308 } 309 310 static uint8_t 311 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 312 { 313 struct bcm_sdhci_softc *sc = device_get_softc(dev); 314 uint32_t val = RD4(sc, off & ~3); 315 316 return ((val >> (off & 3)*8) & 0xff); 317 } 318 319 static uint16_t 320 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 321 { 322 struct bcm_sdhci_softc *sc = device_get_softc(dev); 323 uint32_t val = RD4(sc, off & ~3); 324 325 /* 326 * Standard 32-bit handling of command and transfer mode. 327 */ 328 if (off == SDHCI_TRANSFER_MODE) { 329 return (sc->cmd_and_mode >> 16); 330 } else if (off == SDHCI_COMMAND_FLAGS) { 331 return (sc->cmd_and_mode & 0x0000ffff); 332 } 333 return ((val >> (off & 3)*8) & 0xffff); 334 } 335 336 static uint32_t 337 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 338 { 339 struct bcm_sdhci_softc *sc = device_get_softc(dev); 340 341 return RD4(sc, off); 342 } 343 344 static void 345 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 346 uint32_t *data, bus_size_t count) 347 { 348 struct bcm_sdhci_softc *sc = device_get_softc(dev); 349 350 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 351 } 352 353 static void 354 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 355 { 356 struct bcm_sdhci_softc *sc = device_get_softc(dev); 357 uint32_t val32 = RD4(sc, off & ~3); 358 val32 &= ~(0xff << (off & 3)*8); 359 val32 |= (val << (off & 3)*8); 360 WR4(sc, off & ~3, val32); 361 } 362 363 static void 364 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 365 { 366 struct bcm_sdhci_softc *sc = device_get_softc(dev); 367 uint32_t val32; 368 if (off == SDHCI_COMMAND_FLAGS) 369 val32 = sc->cmd_and_mode; 370 else 371 val32 = RD4(sc, off & ~3); 372 val32 &= ~(0xffff << (off & 3)*8); 373 val32 |= (val << (off & 3)*8); 374 if (off == SDHCI_TRANSFER_MODE) 375 sc->cmd_and_mode = val32; 376 else { 377 WR4(sc, off & ~3, val32); 378 if (off == SDHCI_COMMAND_FLAGS) 379 sc->cmd_and_mode = val32; 380 } 381 } 382 383 static void 384 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 385 { 386 struct bcm_sdhci_softc *sc = device_get_softc(dev); 387 WR4(sc, off, val); 388 } 389 390 static void 391 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 392 uint32_t *data, bus_size_t count) 393 { 394 struct bcm_sdhci_softc *sc = device_get_softc(dev); 395 396 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 397 } 398 399 static void 400 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 401 { 402 struct sdhci_slot *slot; 403 vm_paddr_t pdst, psrc; 404 int err, idx, len, sync_op; 405 406 slot = &sc->sc_slot; 407 idx = sc->dmamap_seg_index++; 408 len = sc->dmamap_seg_sizes[idx]; 409 slot->offset += len; 410 411 if (slot->curcmd->data->flags & MMC_DATA_READ) { 412 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 413 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 414 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 415 BCM_DMA_INC_ADDR, 416 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 417 psrc = sc->sc_sdhci_buffer_phys; 418 pdst = sc->dmamap_seg_addrs[idx]; 419 sync_op = BUS_DMASYNC_PREREAD; 420 } else { 421 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 422 BCM_DMA_INC_ADDR, 423 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 424 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 425 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 426 psrc = sc->dmamap_seg_addrs[idx]; 427 pdst = sc->sc_sdhci_buffer_phys; 428 sync_op = BUS_DMASYNC_PREWRITE; 429 } 430 431 /* 432 * When starting a new DMA operation do the busdma sync operation, and 433 * disable SDCHI data interrrupts because we'll be driven by DMA 434 * interrupts (or SDHCI error interrupts) until the IO is done. 435 */ 436 if (idx == 0) { 437 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 438 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 439 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 440 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 441 slot->intmask); 442 } 443 444 /* 445 * Start the DMA transfer. Only programming errors (like failing to 446 * allocate a channel) cause a non-zero return from bcm_dma_start(). 447 */ 448 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 449 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 450 } 451 452 static void 453 bcm_sdhci_dma_intr(int ch, void *arg) 454 { 455 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 456 struct sdhci_slot *slot = &sc->sc_slot; 457 uint32_t reg, mask; 458 int left, sync_op; 459 460 mtx_lock(&slot->mtx); 461 462 /* 463 * If there are more segments for the current dma, start the next one. 464 * Otherwise unload the dma map and decide what to do next based on the 465 * status of the sdhci controller and whether there's more data left. 466 */ 467 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 468 bcm_sdhci_start_dma_seg(sc); 469 mtx_unlock(&slot->mtx); 470 return; 471 } 472 473 if (slot->curcmd->data->flags & MMC_DATA_READ) { 474 sync_op = BUS_DMASYNC_POSTREAD; 475 mask = SDHCI_INT_DATA_AVAIL; 476 } else { 477 sync_op = BUS_DMASYNC_POSTWRITE; 478 mask = SDHCI_INT_SPACE_AVAIL; 479 } 480 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 481 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 482 483 sc->dmamap_seg_count = 0; 484 sc->dmamap_seg_index = 0; 485 486 left = min(BCM_SDHCI_BUFFER_SIZE, 487 slot->curcmd->data->len - slot->offset); 488 489 /* DATA END? */ 490 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 491 492 if (reg & SDHCI_INT_DATA_END) { 493 /* ACK for all outstanding interrupts */ 494 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 495 496 /* enable INT */ 497 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 498 | SDHCI_INT_DATA_END; 499 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 500 slot->intmask); 501 502 /* finish this data */ 503 sdhci_finish_data(slot); 504 } 505 else { 506 /* already available? */ 507 if (reg & mask) { 508 509 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 510 bcm_sdhci_write_4(slot->bus, slot, 511 SDHCI_INT_STATUS, mask); 512 513 /* continue next DMA transfer */ 514 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 515 (uint8_t *)slot->curcmd->data->data + 516 slot->offset, left, bcm_sdhci_dmacb, sc, 517 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 518 slot->curcmd->error = MMC_ERR_NO_MEMORY; 519 sdhci_finish_data(slot); 520 } else { 521 bcm_sdhci_start_dma_seg(sc); 522 } 523 } else { 524 /* wait for next data by INT */ 525 526 /* enable INT */ 527 slot->intmask |= SDHCI_INT_DATA_AVAIL | 528 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 529 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 530 slot->intmask); 531 } 532 } 533 534 mtx_unlock(&slot->mtx); 535 } 536 537 static void 538 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 539 { 540 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 541 size_t left; 542 543 if (sc->dmamap_seg_count != 0) { 544 device_printf(sc->sc_dev, "DMA in use\n"); 545 return; 546 } 547 548 left = min(BCM_SDHCI_BUFFER_SIZE, 549 slot->curcmd->data->len - slot->offset); 550 551 KASSERT((left & 3) == 0, 552 ("%s: len = %d, not word-aligned", __func__, left)); 553 554 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 555 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 556 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 557 sc->dmamap_status != 0) { 558 slot->curcmd->error = MMC_ERR_NO_MEMORY; 559 return; 560 } 561 562 /* DMA start */ 563 bcm_sdhci_start_dma_seg(sc); 564 } 565 566 static void 567 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 568 { 569 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 570 size_t left; 571 572 if (sc->dmamap_seg_count != 0) { 573 device_printf(sc->sc_dev, "DMA in use\n"); 574 return; 575 } 576 577 left = min(BCM_SDHCI_BUFFER_SIZE, 578 slot->curcmd->data->len - slot->offset); 579 580 KASSERT((left & 3) == 0, 581 ("%s: len = %d, not word-aligned", __func__, left)); 582 583 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 584 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 585 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 586 sc->dmamap_status != 0) { 587 slot->curcmd->error = MMC_ERR_NO_MEMORY; 588 return; 589 } 590 591 /* DMA start */ 592 bcm_sdhci_start_dma_seg(sc); 593 } 594 595 static int 596 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 597 { 598 size_t left; 599 600 /* 601 * Do not use DMA for transfers less than block size or with a length 602 * that is not a multiple of four. 603 */ 604 left = min(BCM_DMA_BLOCK_SIZE, 605 slot->curcmd->data->len - slot->offset); 606 if (left < BCM_DMA_BLOCK_SIZE) 607 return (0); 608 if (left & 0x03) 609 return (0); 610 611 return (1); 612 } 613 614 static void 615 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 616 uint32_t *intmask) 617 { 618 619 /* DMA transfer FIFO 1KB */ 620 if (slot->curcmd->data->flags & MMC_DATA_READ) 621 bcm_sdhci_read_dma(dev, slot); 622 else 623 bcm_sdhci_write_dma(dev, slot); 624 } 625 626 static void 627 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 628 { 629 630 sdhci_finish_data(slot); 631 } 632 633 static device_method_t bcm_sdhci_methods[] = { 634 /* Device interface */ 635 DEVMETHOD(device_probe, bcm_sdhci_probe), 636 DEVMETHOD(device_attach, bcm_sdhci_attach), 637 DEVMETHOD(device_detach, bcm_sdhci_detach), 638 639 /* Bus interface */ 640 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 641 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 642 DEVMETHOD(bus_print_child, bus_generic_print_child), 643 644 /* MMC bridge interface */ 645 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 646 DEVMETHOD(mmcbr_request, sdhci_generic_request), 647 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 648 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 649 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 650 651 /* Platform transfer methods */ 652 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 653 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 654 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 655 /* SDHCI registers accessors */ 656 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 657 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 658 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 659 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 660 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 661 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 662 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 663 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 664 665 { 0, 0 } 666 }; 667 668 static devclass_t bcm_sdhci_devclass; 669 670 static driver_t bcm_sdhci_driver = { 671 "sdhci_bcm", 672 bcm_sdhci_methods, 673 sizeof(struct bcm_sdhci_softc), 674 }; 675 676 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 677 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 678 DRIVER_MODULE(mmc, sdhci_bcm, mmc_driver, mmc_devclass, NULL, NULL); 679