1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bio.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/kthread.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/queue.h> 43 #include <sys/resource.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 #include <sys/time.h> 48 #include <sys/timetc.h> 49 #include <sys/watchdog.h> 50 51 #include <sys/kdb.h> 52 53 #include <machine/bus.h> 54 #include <machine/cpu.h> 55 #include <machine/cpufunc.h> 56 #include <machine/resource.h> 57 #include <machine/intr.h> 58 59 #include <dev/fdt/fdt_common.h> 60 #include <dev/ofw/ofw_bus.h> 61 #include <dev/ofw/ofw_bus_subr.h> 62 63 #include <dev/mmc/bridge.h> 64 #include <dev/mmc/mmcreg.h> 65 #include <dev/mmc/mmcbrvar.h> 66 67 #include <dev/sdhci/sdhci.h> 68 #include "sdhci_if.h" 69 70 #include "bcm2835_dma.h" 71 #include "bcm2835_vcbus.h" 72 73 #define BCM2835_DEFAULT_SDHCI_FREQ 50 74 75 #define BCM_SDHCI_BUFFER_SIZE 512 76 #define NUM_DMA_SEGS 2 77 78 #ifdef DEBUG 79 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 80 printf(fmt,##args); } while (0) 81 #else 82 #define dprintf(fmt, args...) 83 #endif 84 85 /* 86 * Arasan HC seems to have problem with Data CRC on lower frequencies. 87 * Use this tunable to cap initialization sequence frequency at higher 88 * value. Default is standard 400kHz. 89 * HS mode brings too many problems for most of cards, so disable HS mode 90 * until a better fix comes up. 91 * HS mode still can be enabled with the tunable. 92 */ 93 static int bcm2835_sdhci_min_freq = 400000; 94 static int bcm2835_sdhci_hs = 0; 95 static int bcm2835_sdhci_pio_mode = 0; 96 97 TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); 98 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 99 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 100 101 struct bcm_sdhci_softc { 102 device_t sc_dev; 103 struct mtx sc_mtx; 104 struct resource * sc_mem_res; 105 struct resource * sc_irq_res; 106 bus_space_tag_t sc_bst; 107 bus_space_handle_t sc_bsh; 108 void * sc_intrhand; 109 struct mmc_request * sc_req; 110 struct mmc_data * sc_data; 111 uint32_t sc_flags; 112 #define LPC_SD_FLAGS_IGNORECRC (1 << 0) 113 int sc_xfer_direction; 114 #define DIRECTION_READ 0 115 #define DIRECTION_WRITE 1 116 int sc_xfer_done; 117 int sc_bus_busy; 118 struct sdhci_slot sc_slot; 119 int sc_dma_inuse; 120 int sc_dma_ch; 121 bus_dma_tag_t sc_dma_tag; 122 bus_dmamap_t sc_dma_map; 123 vm_paddr_t sc_sdhci_buffer_phys; 124 uint32_t cmd_and_mode; 125 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 126 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 127 int dmamap_seg_count; 128 int dmamap_seg_index; 129 int dmamap_status; 130 }; 131 132 static int bcm_sdhci_probe(device_t); 133 static int bcm_sdhci_attach(device_t); 134 static int bcm_sdhci_detach(device_t); 135 static void bcm_sdhci_intr(void *); 136 137 static int bcm_sdhci_get_ro(device_t, device_t); 138 static void bcm_sdhci_dma_intr(int ch, void *arg); 139 140 #define bcm_sdhci_lock(_sc) \ 141 mtx_lock(&_sc->sc_mtx); 142 #define bcm_sdhci_unlock(_sc) \ 143 mtx_unlock(&_sc->sc_mtx); 144 145 static void 146 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 147 { 148 struct bcm_sdhci_softc *sc = arg; 149 int i; 150 151 sc->dmamap_status = err; 152 sc->dmamap_seg_count = nseg; 153 154 /* Note nseg is guaranteed to be zero if err is non-zero. */ 155 for (i = 0; i < nseg; i++) { 156 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 157 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 158 } 159 } 160 161 static int 162 bcm_sdhci_probe(device_t dev) 163 { 164 165 if (!ofw_bus_status_okay(dev)) 166 return (ENXIO); 167 168 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 169 return (ENXIO); 170 171 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 172 return (BUS_PROBE_DEFAULT); 173 } 174 175 static int 176 bcm_sdhci_attach(device_t dev) 177 { 178 struct bcm_sdhci_softc *sc = device_get_softc(dev); 179 int rid, err; 180 phandle_t node; 181 pcell_t cell; 182 int default_freq; 183 184 sc->sc_dev = dev; 185 sc->sc_req = NULL; 186 err = 0; 187 188 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 189 node = ofw_bus_get_node(sc->sc_dev); 190 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) 191 default_freq = (int)fdt32_to_cpu(cell)/1000000; 192 193 dprintf("SDHCI frequency: %dMHz\n", default_freq); 194 195 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 196 197 rid = 0; 198 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 199 RF_ACTIVE); 200 if (!sc->sc_mem_res) { 201 device_printf(dev, "cannot allocate memory window\n"); 202 err = ENXIO; 203 goto fail; 204 } 205 206 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 207 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 208 209 rid = 0; 210 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 211 RF_ACTIVE); 212 if (!sc->sc_irq_res) { 213 device_printf(dev, "cannot allocate interrupt\n"); 214 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 215 err = ENXIO; 216 goto fail; 217 } 218 219 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 220 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) 221 { 222 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 223 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 224 device_printf(dev, "cannot setup interrupt handler\n"); 225 err = ENXIO; 226 goto fail; 227 } 228 229 if (!bcm2835_sdhci_pio_mode) 230 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 231 232 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 233 if (bcm2835_sdhci_hs) 234 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 235 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 236 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 237 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 238 | SDHCI_QUIRK_MISSING_CAPS; 239 240 sdhci_init_slot(dev, &sc->sc_slot, 0); 241 242 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 243 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 244 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 245 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 246 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 247 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 248 goto fail; 249 250 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 251 252 /* Allocate bus_dma resources. */ 253 err = bus_dma_tag_create(bus_get_dma_tag(dev), 254 1, 0, BUS_SPACE_MAXADDR_32BIT, 255 BUS_SPACE_MAXADDR, NULL, NULL, 256 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 257 BUS_DMA_ALLOCNOW, NULL, NULL, 258 &sc->sc_dma_tag); 259 260 if (err) { 261 device_printf(dev, "failed allocate DMA tag"); 262 goto fail; 263 } 264 265 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 266 if (err) { 267 device_printf(dev, "bus_dmamap_create failed\n"); 268 goto fail; 269 } 270 271 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 272 SDHCI_BUFFER); 273 274 bus_generic_probe(dev); 275 bus_generic_attach(dev); 276 277 sdhci_start_slot(&sc->sc_slot); 278 279 return (0); 280 281 fail: 282 if (sc->sc_intrhand) 283 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 284 if (sc->sc_irq_res) 285 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 286 if (sc->sc_mem_res) 287 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 288 289 return (err); 290 } 291 292 static int 293 bcm_sdhci_detach(device_t dev) 294 { 295 296 return (EBUSY); 297 } 298 299 static void 300 bcm_sdhci_intr(void *arg) 301 { 302 struct bcm_sdhci_softc *sc = arg; 303 304 sdhci_generic_intr(&sc->sc_slot); 305 } 306 307 static int 308 bcm_sdhci_get_ro(device_t bus, device_t child) 309 { 310 311 return (0); 312 } 313 314 static inline uint32_t 315 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 316 { 317 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 318 return val; 319 } 320 321 static inline void 322 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 323 { 324 325 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 326 /* 327 * The Arasan HC has a bug where it may lose the content of 328 * consecutive writes to registers that are within two SD-card 329 * clock cycles of each other (a clock domain crossing problem). 330 */ 331 if (sc->sc_slot.clock > 0) 332 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 333 } 334 335 static uint8_t 336 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 337 { 338 struct bcm_sdhci_softc *sc = device_get_softc(dev); 339 uint32_t val = RD4(sc, off & ~3); 340 341 return ((val >> (off & 3)*8) & 0xff); 342 } 343 344 static uint16_t 345 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 346 { 347 struct bcm_sdhci_softc *sc = device_get_softc(dev); 348 uint32_t val = RD4(sc, off & ~3); 349 350 /* 351 * Standard 32-bit handling of command and transfer mode. 352 */ 353 if (off == SDHCI_TRANSFER_MODE) { 354 return (sc->cmd_and_mode >> 16); 355 } else if (off == SDHCI_COMMAND_FLAGS) { 356 return (sc->cmd_and_mode & 0x0000ffff); 357 } 358 return ((val >> (off & 3)*8) & 0xffff); 359 } 360 361 static uint32_t 362 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 363 { 364 struct bcm_sdhci_softc *sc = device_get_softc(dev); 365 366 return RD4(sc, off); 367 } 368 369 static void 370 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 371 uint32_t *data, bus_size_t count) 372 { 373 struct bcm_sdhci_softc *sc = device_get_softc(dev); 374 375 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 376 } 377 378 static void 379 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 380 { 381 struct bcm_sdhci_softc *sc = device_get_softc(dev); 382 uint32_t val32 = RD4(sc, off & ~3); 383 val32 &= ~(0xff << (off & 3)*8); 384 val32 |= (val << (off & 3)*8); 385 WR4(sc, off & ~3, val32); 386 } 387 388 static void 389 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 390 { 391 struct bcm_sdhci_softc *sc = device_get_softc(dev); 392 uint32_t val32; 393 if (off == SDHCI_COMMAND_FLAGS) 394 val32 = sc->cmd_and_mode; 395 else 396 val32 = RD4(sc, off & ~3); 397 val32 &= ~(0xffff << (off & 3)*8); 398 val32 |= (val << (off & 3)*8); 399 if (off == SDHCI_TRANSFER_MODE) 400 sc->cmd_and_mode = val32; 401 else 402 WR4(sc, off & ~3, val32); 403 } 404 405 static void 406 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 407 { 408 struct bcm_sdhci_softc *sc = device_get_softc(dev); 409 WR4(sc, off, val); 410 } 411 412 static void 413 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 414 uint32_t *data, bus_size_t count) 415 { 416 struct bcm_sdhci_softc *sc = device_get_softc(dev); 417 418 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 419 } 420 421 static uint32_t 422 bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot) 423 { 424 425 return bcm2835_sdhci_min_freq; 426 } 427 428 static void 429 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 430 { 431 struct sdhci_slot *slot; 432 vm_paddr_t pdst, psrc; 433 int err, idx, len, sync_op; 434 435 slot = &sc->sc_slot; 436 idx = sc->dmamap_seg_index++; 437 len = sc->dmamap_seg_sizes[idx]; 438 slot->offset += len; 439 440 if (slot->curcmd->data->flags & MMC_DATA_READ) { 441 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 442 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 443 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 444 BCM_DMA_INC_ADDR, 445 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 446 psrc = sc->sc_sdhci_buffer_phys; 447 pdst = sc->dmamap_seg_addrs[idx]; 448 sync_op = BUS_DMASYNC_PREREAD; 449 } else { 450 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 451 BCM_DMA_INC_ADDR, 452 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 453 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 454 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 455 psrc = sc->dmamap_seg_addrs[idx]; 456 pdst = sc->sc_sdhci_buffer_phys; 457 sync_op = BUS_DMASYNC_PREWRITE; 458 } 459 460 /* 461 * When starting a new DMA operation do the busdma sync operation, and 462 * disable SDCHI data interrrupts because we'll be driven by DMA 463 * interrupts (or SDHCI error interrupts) until the IO is done. 464 */ 465 if (idx == 0) { 466 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 467 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 468 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 469 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 470 slot->intmask); 471 } 472 473 /* 474 * Start the DMA transfer. Only programming errors (like failing to 475 * allocate a channel) cause a non-zero return from bcm_dma_start(). 476 */ 477 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 478 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 479 } 480 481 static void 482 bcm_sdhci_dma_intr(int ch, void *arg) 483 { 484 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 485 struct sdhci_slot *slot = &sc->sc_slot; 486 uint32_t reg, mask; 487 int left, sync_op; 488 489 mtx_lock(&slot->mtx); 490 491 /* 492 * If there are more segments for the current dma, start the next one. 493 * Otherwise unload the dma map and decide what to do next based on the 494 * status of the sdhci controller and whether there's more data left. 495 */ 496 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 497 bcm_sdhci_start_dma_seg(sc); 498 mtx_unlock(&slot->mtx); 499 return; 500 } 501 502 if (slot->curcmd->data->flags & MMC_DATA_READ) { 503 sync_op = BUS_DMASYNC_POSTREAD; 504 mask = SDHCI_INT_DATA_AVAIL; 505 } else { 506 sync_op = BUS_DMASYNC_POSTWRITE; 507 mask = SDHCI_INT_SPACE_AVAIL; 508 } 509 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 510 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 511 512 sc->dmamap_seg_count = 0; 513 sc->dmamap_seg_index = 0; 514 515 left = min(BCM_SDHCI_BUFFER_SIZE, 516 slot->curcmd->data->len - slot->offset); 517 518 /* DATA END? */ 519 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 520 521 if (reg & SDHCI_INT_DATA_END) { 522 /* ACK for all outstanding interrupts */ 523 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 524 525 /* enable INT */ 526 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 527 | SDHCI_INT_DATA_END; 528 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 529 slot->intmask); 530 531 /* finish this data */ 532 sdhci_finish_data(slot); 533 } 534 else { 535 /* already available? */ 536 if (reg & mask) { 537 538 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 539 bcm_sdhci_write_4(slot->bus, slot, 540 SDHCI_INT_STATUS, mask); 541 542 /* continue next DMA transfer */ 543 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 544 (uint8_t *)slot->curcmd->data->data + 545 slot->offset, left, bcm_sdhci_dmacb, sc, 546 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 547 slot->curcmd->error = MMC_ERR_NO_MEMORY; 548 sdhci_finish_data(slot); 549 } else { 550 bcm_sdhci_start_dma_seg(sc); 551 } 552 } else { 553 /* wait for next data by INT */ 554 555 /* enable INT */ 556 slot->intmask |= SDHCI_INT_DATA_AVAIL | 557 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 558 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 559 slot->intmask); 560 } 561 } 562 563 mtx_unlock(&slot->mtx); 564 } 565 566 static void 567 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 568 { 569 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 570 size_t left; 571 572 if (sc->dmamap_seg_count != 0) { 573 device_printf(sc->sc_dev, "DMA in use\n"); 574 return; 575 } 576 577 left = min(BCM_SDHCI_BUFFER_SIZE, 578 slot->curcmd->data->len - slot->offset); 579 580 KASSERT((left & 3) == 0, 581 ("%s: len = %d, not word-aligned", __func__, left)); 582 583 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 584 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 585 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 586 sc->dmamap_status != 0) { 587 slot->curcmd->error = MMC_ERR_NO_MEMORY; 588 return; 589 } 590 591 /* DMA start */ 592 bcm_sdhci_start_dma_seg(sc); 593 } 594 595 static void 596 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 597 { 598 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 599 size_t left; 600 601 if (sc->dmamap_seg_count != 0) { 602 device_printf(sc->sc_dev, "DMA in use\n"); 603 return; 604 } 605 606 left = min(BCM_SDHCI_BUFFER_SIZE, 607 slot->curcmd->data->len - slot->offset); 608 609 KASSERT((left & 3) == 0, 610 ("%s: len = %d, not word-aligned", __func__, left)); 611 612 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 613 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 614 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 615 sc->dmamap_status != 0) { 616 slot->curcmd->error = MMC_ERR_NO_MEMORY; 617 return; 618 } 619 620 /* DMA start */ 621 bcm_sdhci_start_dma_seg(sc); 622 } 623 624 static int 625 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 626 { 627 size_t left; 628 629 /* 630 * Do not use DMA for transfers less than block size or with a length 631 * that is not a multiple of four. 632 */ 633 left = min(BCM_DMA_BLOCK_SIZE, 634 slot->curcmd->data->len - slot->offset); 635 if (left < BCM_DMA_BLOCK_SIZE) 636 return (0); 637 if (left & 0x03) 638 return (0); 639 640 return (1); 641 } 642 643 static void 644 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 645 uint32_t *intmask) 646 { 647 648 /* DMA transfer FIFO 1KB */ 649 if (slot->curcmd->data->flags & MMC_DATA_READ) 650 bcm_sdhci_read_dma(dev, slot); 651 else 652 bcm_sdhci_write_dma(dev, slot); 653 } 654 655 static void 656 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 657 { 658 659 sdhci_finish_data(slot); 660 } 661 662 static device_method_t bcm_sdhci_methods[] = { 663 /* Device interface */ 664 DEVMETHOD(device_probe, bcm_sdhci_probe), 665 DEVMETHOD(device_attach, bcm_sdhci_attach), 666 DEVMETHOD(device_detach, bcm_sdhci_detach), 667 668 /* Bus interface */ 669 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 670 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 671 DEVMETHOD(bus_print_child, bus_generic_print_child), 672 673 /* MMC bridge interface */ 674 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 675 DEVMETHOD(mmcbr_request, sdhci_generic_request), 676 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 677 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 678 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 679 680 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq), 681 /* Platform transfer methods */ 682 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 683 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 684 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 685 /* SDHCI registers accessors */ 686 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 687 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 688 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 689 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 690 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 691 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 692 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 693 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 694 695 { 0, 0 } 696 }; 697 698 static devclass_t bcm_sdhci_devclass; 699 700 static driver_t bcm_sdhci_driver = { 701 "sdhci_bcm", 702 bcm_sdhci_methods, 703 sizeof(struct bcm_sdhci_softc), 704 }; 705 706 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 707 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 708