1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <sys/taskqueue.h> 43 44 #include <machine/bus.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcreg.h> 51 52 #include <dev/sdhci/sdhci.h> 53 54 #include "mmcbr_if.h" 55 #include "sdhci_if.h" 56 57 #include "opt_mmccam.h" 58 59 #include "bcm2835_dma.h" 60 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 61 #include "bcm2835_vcbus.h" 62 63 #define BCM2835_DEFAULT_SDHCI_FREQ 50 64 65 #define BCM_SDHCI_BUFFER_SIZE 512 66 #define NUM_DMA_SEGS 2 67 68 #ifdef DEBUG 69 static int bcm2835_sdhci_debug = 0; 70 71 TUNABLE_INT("hw.bcm2835.sdhci.debug", &bcm2835_sdhci_debug); 72 SYSCTL_INT(_hw_sdhci, OID_AUTO, bcm2835_sdhci_debug, CTLFLAG_RWTUN, 73 &bcm2835_sdhci_debug, 0, "bcm2835 SDHCI debug level"); 74 75 #define dprintf(fmt, args...) \ 76 do { \ 77 if (bcm2835_sdhci_debug) \ 78 printf("%s: " fmt, __func__, ##args); \ 79 } while (0) 80 #else 81 #define dprintf(fmt, args...) 82 #endif 83 84 static int bcm2835_sdhci_hs = 1; 85 static int bcm2835_sdhci_pio_mode = 0; 86 87 static struct ofw_compat_data compat_data[] = { 88 {"broadcom,bcm2835-sdhci", 1}, 89 {"brcm,bcm2835-sdhci", 1}, 90 {"brcm,bcm2835-mmc", 1}, 91 {NULL, 0} 92 }; 93 94 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 95 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 96 97 struct bcm_sdhci_softc { 98 device_t sc_dev; 99 struct resource * sc_mem_res; 100 struct resource * sc_irq_res; 101 bus_space_tag_t sc_bst; 102 bus_space_handle_t sc_bsh; 103 void * sc_intrhand; 104 struct mmc_request * sc_req; 105 struct sdhci_slot sc_slot; 106 int sc_dma_ch; 107 bus_dma_tag_t sc_dma_tag; 108 bus_dmamap_t sc_dma_map; 109 vm_paddr_t sc_sdhci_buffer_phys; 110 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 111 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 112 int dmamap_seg_count; 113 int dmamap_seg_index; 114 int dmamap_status; 115 uint32_t blksz_and_count; 116 uint32_t cmd_and_mode; 117 bool need_update_blk; 118 }; 119 120 static int bcm_sdhci_probe(device_t); 121 static int bcm_sdhci_attach(device_t); 122 static int bcm_sdhci_detach(device_t); 123 static void bcm_sdhci_intr(void *); 124 125 static int bcm_sdhci_get_ro(device_t, device_t); 126 static void bcm_sdhci_dma_intr(int ch, void *arg); 127 128 static void 129 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 130 { 131 struct bcm_sdhci_softc *sc = arg; 132 int i; 133 134 sc->dmamap_status = err; 135 sc->dmamap_seg_count = nseg; 136 137 /* Note nseg is guaranteed to be zero if err is non-zero. */ 138 for (i = 0; i < nseg; i++) { 139 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 140 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 141 } 142 } 143 144 static int 145 bcm_sdhci_probe(device_t dev) 146 { 147 148 if (!ofw_bus_status_okay(dev)) 149 return (ENXIO); 150 151 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 152 return (ENXIO); 153 154 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 155 156 return (BUS_PROBE_DEFAULT); 157 } 158 159 static int 160 bcm_sdhci_attach(device_t dev) 161 { 162 struct bcm_sdhci_softc *sc = device_get_softc(dev); 163 int rid, err; 164 phandle_t node; 165 pcell_t cell; 166 u_int default_freq; 167 168 sc->sc_dev = dev; 169 sc->sc_req = NULL; 170 171 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, 172 TRUE); 173 if (err != 0) { 174 if (bootverbose) 175 device_printf(dev, "Unable to enable the power\n"); 176 return (err); 177 } 178 179 default_freq = 0; 180 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, 181 &default_freq); 182 if (err == 0) { 183 /* Convert to MHz */ 184 default_freq /= 1000000; 185 } 186 if (default_freq == 0) { 187 node = ofw_bus_get_node(sc->sc_dev); 188 if ((OF_getencprop(node, "clock-frequency", &cell, 189 sizeof(cell))) > 0) 190 default_freq = cell / 1000000; 191 } 192 if (default_freq == 0) 193 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 194 195 if (bootverbose) 196 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 197 198 rid = 0; 199 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 200 RF_ACTIVE); 201 if (!sc->sc_mem_res) { 202 device_printf(dev, "cannot allocate memory window\n"); 203 err = ENXIO; 204 goto fail; 205 } 206 207 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 208 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 209 210 rid = 0; 211 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 212 RF_ACTIVE); 213 if (!sc->sc_irq_res) { 214 device_printf(dev, "cannot allocate interrupt\n"); 215 err = ENXIO; 216 goto fail; 217 } 218 219 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 220 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 221 device_printf(dev, "cannot setup interrupt handler\n"); 222 err = ENXIO; 223 goto fail; 224 } 225 226 if (!bcm2835_sdhci_pio_mode) 227 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 228 229 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 230 if (bcm2835_sdhci_hs) 231 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 232 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 233 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 234 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 235 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 236 | SDHCI_QUIRK_MISSING_CAPS; 237 238 sdhci_init_slot(dev, &sc->sc_slot, 0); 239 240 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 241 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 242 goto fail; 243 244 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 245 246 /* Allocate bus_dma resources. */ 247 err = bus_dma_tag_create(bus_get_dma_tag(dev), 248 1, 0, BUS_SPACE_MAXADDR_32BIT, 249 BUS_SPACE_MAXADDR, NULL, NULL, 250 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 251 BUS_DMA_ALLOCNOW, NULL, NULL, 252 &sc->sc_dma_tag); 253 254 if (err) { 255 device_printf(dev, "failed allocate DMA tag"); 256 goto fail; 257 } 258 259 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 260 if (err) { 261 device_printf(dev, "bus_dmamap_create failed\n"); 262 goto fail; 263 } 264 265 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ 266 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + 267 SDHCI_BUFFER; 268 269 bus_generic_probe(dev); 270 bus_generic_attach(dev); 271 272 sdhci_start_slot(&sc->sc_slot); 273 274 /* Seed our copies. */ 275 sc->blksz_and_count = SDHCI_READ_4(dev, &sc->sc_slot, SDHCI_BLOCK_SIZE); 276 sc->cmd_and_mode = SDHCI_READ_4(dev, &sc->sc_slot, SDHCI_TRANSFER_MODE); 277 278 return (0); 279 280 fail: 281 if (sc->sc_intrhand) 282 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 283 if (sc->sc_irq_res) 284 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 285 if (sc->sc_mem_res) 286 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 287 288 return (err); 289 } 290 291 static int 292 bcm_sdhci_detach(device_t dev) 293 { 294 295 return (EBUSY); 296 } 297 298 static void 299 bcm_sdhci_intr(void *arg) 300 { 301 struct bcm_sdhci_softc *sc = arg; 302 303 sdhci_generic_intr(&sc->sc_slot); 304 } 305 306 static int 307 bcm_sdhci_get_ro(device_t bus, device_t child) 308 { 309 310 return (0); 311 } 312 313 static inline uint32_t 314 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 315 { 316 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 317 return val; 318 } 319 320 static inline void 321 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 322 { 323 324 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 325 /* 326 * The Arasan HC has a bug where it may lose the content of 327 * consecutive writes to registers that are within two SD-card 328 * clock cycles of each other (a clock domain crossing problem). 329 */ 330 if (sc->sc_slot.clock > 0) 331 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 332 } 333 334 static uint8_t 335 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 336 { 337 struct bcm_sdhci_softc *sc = device_get_softc(dev); 338 uint32_t val = RD4(sc, off & ~3); 339 340 return ((val >> (off & 3)*8) & 0xff); 341 } 342 343 static uint16_t 344 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 345 { 346 struct bcm_sdhci_softc *sc = device_get_softc(dev); 347 uint32_t val32; 348 349 /* 350 * Standard 32-bit handling of command and transfer mode, as 351 * well as block size and count. 352 */ 353 if ((off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) && 354 sc->need_update_blk) 355 val32 = sc->blksz_and_count; 356 else if (off == SDHCI_TRANSFER_MODE || off == SDHCI_COMMAND_FLAGS) 357 val32 = sc->cmd_and_mode; 358 else 359 val32 = RD4(sc, off & ~3); 360 361 return ((val32 >> (off & 3)*8) & 0xffff); 362 } 363 364 static uint32_t 365 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 366 { 367 struct bcm_sdhci_softc *sc = device_get_softc(dev); 368 369 return RD4(sc, off); 370 } 371 372 static void 373 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 374 uint32_t *data, bus_size_t count) 375 { 376 struct bcm_sdhci_softc *sc = device_get_softc(dev); 377 378 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 379 } 380 381 static void 382 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 383 { 384 struct bcm_sdhci_softc *sc = device_get_softc(dev); 385 uint32_t val32 = RD4(sc, off & ~3); 386 val32 &= ~(0xff << (off & 3)*8); 387 val32 |= (val << (off & 3)*8); 388 WR4(sc, off & ~3, val32); 389 } 390 391 static void 392 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 393 { 394 struct bcm_sdhci_softc *sc = device_get_softc(dev); 395 uint32_t val32; 396 397 /* 398 * If we have a queued up 16bit value for blk size or count, use and 399 * update the saved value rather than doing any real register access. 400 * If we did not touch either since the last write, then read from 401 * register as at least block count can change. 402 * Similarly, if we are about to issue a command, always use the saved 403 * value for transfer mode as we can never write that without issuing 404 * a command. 405 */ 406 if ((off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) && 407 sc->need_update_blk) 408 val32 = sc->blksz_and_count; 409 else if (off == SDHCI_COMMAND_FLAGS) 410 val32 = sc->cmd_and_mode; 411 else 412 val32 = RD4(sc, off & ~3); 413 414 val32 &= ~(0xffff << (off & 3)*8); 415 val32 |= (val << (off & 3)*8); 416 417 if (off == SDHCI_TRANSFER_MODE) 418 sc->cmd_and_mode = val32; 419 else if (off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) { 420 sc->blksz_and_count = val32; 421 sc->need_update_blk = true; 422 } else { 423 if (off == SDHCI_COMMAND_FLAGS) { 424 /* If we saved blk writes, do them now before cmd. */ 425 if (sc->need_update_blk) { 426 WR4(sc, SDHCI_BLOCK_SIZE, sc->blksz_and_count); 427 sc->need_update_blk = false; 428 } 429 /* Always save cmd and mode registers. */ 430 sc->cmd_and_mode = val32; 431 } 432 WR4(sc, off & ~3, val32); 433 } 434 } 435 436 static void 437 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 438 { 439 struct bcm_sdhci_softc *sc = device_get_softc(dev); 440 WR4(sc, off, val); 441 } 442 443 static void 444 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 445 uint32_t *data, bus_size_t count) 446 { 447 struct bcm_sdhci_softc *sc = device_get_softc(dev); 448 449 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 450 } 451 452 static void 453 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 454 { 455 struct sdhci_slot *slot; 456 vm_paddr_t pdst, psrc; 457 int err, idx, len, sync_op; 458 459 slot = &sc->sc_slot; 460 idx = sc->dmamap_seg_index++; 461 len = sc->dmamap_seg_sizes[idx]; 462 slot->offset += len; 463 464 if (slot->curcmd->data->flags & MMC_DATA_READ) { 465 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 466 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 467 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 468 BCM_DMA_INC_ADDR, 469 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 470 psrc = sc->sc_sdhci_buffer_phys; 471 pdst = sc->dmamap_seg_addrs[idx]; 472 sync_op = BUS_DMASYNC_PREREAD; 473 } else { 474 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 475 BCM_DMA_INC_ADDR, 476 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 477 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 478 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 479 psrc = sc->dmamap_seg_addrs[idx]; 480 pdst = sc->sc_sdhci_buffer_phys; 481 sync_op = BUS_DMASYNC_PREWRITE; 482 } 483 484 /* 485 * When starting a new DMA operation do the busdma sync operation, and 486 * disable SDCHI data interrrupts because we'll be driven by DMA 487 * interrupts (or SDHCI error interrupts) until the IO is done. 488 */ 489 if (idx == 0) { 490 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 491 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 492 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 493 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 494 slot->intmask); 495 } 496 497 /* 498 * Start the DMA transfer. Only programming errors (like failing to 499 * allocate a channel) cause a non-zero return from bcm_dma_start(). 500 */ 501 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 502 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 503 } 504 505 static void 506 bcm_sdhci_dma_intr(int ch, void *arg) 507 { 508 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 509 struct sdhci_slot *slot = &sc->sc_slot; 510 uint32_t reg, mask; 511 int left, sync_op; 512 513 mtx_lock(&slot->mtx); 514 515 /* 516 * If there are more segments for the current dma, start the next one. 517 * Otherwise unload the dma map and decide what to do next based on the 518 * status of the sdhci controller and whether there's more data left. 519 */ 520 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 521 bcm_sdhci_start_dma_seg(sc); 522 mtx_unlock(&slot->mtx); 523 return; 524 } 525 526 if (slot->curcmd->data->flags & MMC_DATA_READ) { 527 sync_op = BUS_DMASYNC_POSTREAD; 528 mask = SDHCI_INT_DATA_AVAIL; 529 } else { 530 sync_op = BUS_DMASYNC_POSTWRITE; 531 mask = SDHCI_INT_SPACE_AVAIL; 532 } 533 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 534 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 535 536 sc->dmamap_seg_count = 0; 537 sc->dmamap_seg_index = 0; 538 539 left = min(BCM_SDHCI_BUFFER_SIZE, 540 slot->curcmd->data->len - slot->offset); 541 542 /* 543 * If there is less than buffer size outstanding, we would not handle 544 * it anymore using DMA if bcm_sdhci_will_handle_transfer() were asked. 545 * Re-enable interrupts and return and let the SDHCI state machine 546 * finish the job. 547 */ 548 if (left < BCM_SDHCI_BUFFER_SIZE) { 549 /* Re-enable data interrupts. */ 550 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 551 SDHCI_INT_DATA_END; 552 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 553 slot->intmask); 554 mtx_unlock(&slot->mtx); 555 return; 556 } 557 558 /* DATA END? */ 559 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 560 561 if (reg & SDHCI_INT_DATA_END) { 562 /* ACK for all outstanding interrupts */ 563 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 564 565 /* enable INT */ 566 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 567 | SDHCI_INT_DATA_END; 568 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 569 slot->intmask); 570 571 /* finish this data */ 572 sdhci_finish_data(slot); 573 } 574 else { 575 /* already available? */ 576 if (reg & mask) { 577 578 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 579 bcm_sdhci_write_4(slot->bus, slot, 580 SDHCI_INT_STATUS, mask); 581 582 /* continue next DMA transfer */ 583 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 584 (uint8_t *)slot->curcmd->data->data + 585 slot->offset, left, bcm_sdhci_dmacb, sc, 586 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 587 slot->curcmd->error = MMC_ERR_NO_MEMORY; 588 sdhci_finish_data(slot); 589 } else { 590 bcm_sdhci_start_dma_seg(sc); 591 } 592 } else { 593 /* wait for next data by INT */ 594 595 /* enable INT */ 596 slot->intmask |= SDHCI_INT_DATA_AVAIL | 597 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 598 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 599 slot->intmask); 600 } 601 } 602 603 mtx_unlock(&slot->mtx); 604 } 605 606 static void 607 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 608 { 609 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 610 size_t left; 611 612 if (sc->dmamap_seg_count != 0) { 613 device_printf(sc->sc_dev, "DMA in use\n"); 614 return; 615 } 616 617 left = min(BCM_SDHCI_BUFFER_SIZE, 618 slot->curcmd->data->len - slot->offset); 619 620 KASSERT((left & 3) == 0, 621 ("%s: len = %zu, not word-aligned", __func__, left)); 622 623 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 624 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 625 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 626 sc->dmamap_status != 0) { 627 slot->curcmd->error = MMC_ERR_NO_MEMORY; 628 return; 629 } 630 631 /* DMA start */ 632 bcm_sdhci_start_dma_seg(sc); 633 } 634 635 static void 636 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 637 { 638 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 639 size_t left; 640 641 if (sc->dmamap_seg_count != 0) { 642 device_printf(sc->sc_dev, "DMA in use\n"); 643 return; 644 } 645 646 left = min(BCM_SDHCI_BUFFER_SIZE, 647 slot->curcmd->data->len - slot->offset); 648 649 KASSERT((left & 3) == 0, 650 ("%s: len = %zu, not word-aligned", __func__, left)); 651 652 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 653 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 654 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 655 sc->dmamap_status != 0) { 656 slot->curcmd->error = MMC_ERR_NO_MEMORY; 657 return; 658 } 659 660 /* DMA start */ 661 bcm_sdhci_start_dma_seg(sc); 662 } 663 664 static int 665 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 666 { 667 size_t left; 668 669 /* 670 * Do not use DMA for transfers less than block size or with a length 671 * that is not a multiple of four. 672 */ 673 left = min(BCM_DMA_BLOCK_SIZE, 674 slot->curcmd->data->len - slot->offset); 675 if (left < BCM_DMA_BLOCK_SIZE) 676 return (0); 677 if (left & 0x03) 678 return (0); 679 680 return (1); 681 } 682 683 static void 684 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 685 uint32_t *intmask) 686 { 687 688 /* DMA transfer FIFO 1KB */ 689 if (slot->curcmd->data->flags & MMC_DATA_READ) 690 bcm_sdhci_read_dma(dev, slot); 691 else 692 bcm_sdhci_write_dma(dev, slot); 693 } 694 695 static void 696 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 697 { 698 699 sdhci_finish_data(slot); 700 } 701 702 static device_method_t bcm_sdhci_methods[] = { 703 /* Device interface */ 704 DEVMETHOD(device_probe, bcm_sdhci_probe), 705 DEVMETHOD(device_attach, bcm_sdhci_attach), 706 DEVMETHOD(device_detach, bcm_sdhci_detach), 707 708 /* Bus interface */ 709 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 710 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 711 DEVMETHOD(bus_add_child, bus_generic_add_child), 712 713 /* MMC bridge interface */ 714 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 715 DEVMETHOD(mmcbr_request, sdhci_generic_request), 716 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 717 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 718 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 719 720 /* Platform transfer methods */ 721 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 722 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 723 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 724 /* SDHCI registers accessors */ 725 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 726 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 727 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 728 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 729 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 730 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 731 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 732 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 733 734 DEVMETHOD_END 735 }; 736 737 static devclass_t bcm_sdhci_devclass; 738 739 static driver_t bcm_sdhci_driver = { 740 "sdhci_bcm", 741 bcm_sdhci_methods, 742 sizeof(struct bcm_sdhci_softc), 743 }; 744 745 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 746 NULL, NULL); 747 SDHCI_DEPEND(sdhci_bcm); 748 #ifndef MMCCAM 749 MMC_DECLARE_BRIDGE(sdhci_bcm); 750 #endif 751