19eec64c0SPoul-Henning Kamp /*- 29eec64c0SPoul-Henning Kamp * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 39eec64c0SPoul-Henning Kamp * 42b7d9db4SPoul-Henning Kamp * Copyright (c) 2017 Poul-Henning Kamp <phk@FreeBSD.org> 59eec64c0SPoul-Henning Kamp * All rights reserved. 69eec64c0SPoul-Henning Kamp * 79eec64c0SPoul-Henning Kamp * Redistribution and use in source and binary forms, with or without 89eec64c0SPoul-Henning Kamp * modification, are permitted provided that the following conditions 99eec64c0SPoul-Henning Kamp * are met: 109eec64c0SPoul-Henning Kamp * 1. Redistributions of source code must retain the above copyright 119eec64c0SPoul-Henning Kamp * notice, this list of conditions and the following disclaimer. 129eec64c0SPoul-Henning Kamp * 2. Redistributions in binary form must reproduce the above copyright 139eec64c0SPoul-Henning Kamp * notice, this list of conditions and the following disclaimer in the 149eec64c0SPoul-Henning Kamp * documentation and/or other materials provided with the distribution. 159eec64c0SPoul-Henning Kamp * 169eec64c0SPoul-Henning Kamp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 179eec64c0SPoul-Henning Kamp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 189eec64c0SPoul-Henning Kamp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 199eec64c0SPoul-Henning Kamp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 209eec64c0SPoul-Henning Kamp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 219eec64c0SPoul-Henning Kamp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 229eec64c0SPoul-Henning Kamp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 239eec64c0SPoul-Henning Kamp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 249eec64c0SPoul-Henning Kamp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 259eec64c0SPoul-Henning Kamp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 269eec64c0SPoul-Henning Kamp * SUCH DAMAGE. 279eec64c0SPoul-Henning Kamp * 289eec64c0SPoul-Henning Kamp */ 299eec64c0SPoul-Henning Kamp 309eec64c0SPoul-Henning Kamp #include <sys/cdefs.h> 319eec64c0SPoul-Henning Kamp __FBSDID("$FreeBSD$"); 329eec64c0SPoul-Henning Kamp 339eec64c0SPoul-Henning Kamp #include <sys/param.h> 349eec64c0SPoul-Henning Kamp #include <sys/systm.h> 359eec64c0SPoul-Henning Kamp #include <sys/bus.h> 369eec64c0SPoul-Henning Kamp 379eec64c0SPoul-Henning Kamp #include <sys/kernel.h> 389eec64c0SPoul-Henning Kamp #include <sys/module.h> 399eec64c0SPoul-Henning Kamp #include <sys/rman.h> 409eec64c0SPoul-Henning Kamp #include <sys/lock.h> 419eec64c0SPoul-Henning Kamp #include <sys/sysctl.h> 429eec64c0SPoul-Henning Kamp 439eec64c0SPoul-Henning Kamp #include <machine/bus.h> 449eec64c0SPoul-Henning Kamp #include <machine/resource.h> 459eec64c0SPoul-Henning Kamp 469eec64c0SPoul-Henning Kamp #include <dev/ofw/ofw_bus.h> 479eec64c0SPoul-Henning Kamp #include <dev/ofw/ofw_bus_subr.h> 489eec64c0SPoul-Henning Kamp 49fc62b7e5SPoul-Henning Kamp #include <arm/broadcom/bcm2835/bcm2835_clkman.h> 509eec64c0SPoul-Henning Kamp 519eec64c0SPoul-Henning Kamp static struct ofw_compat_data compat_data[] = { 529eec64c0SPoul-Henning Kamp {"broadcom,bcm2835-pwm", 1}, 539eec64c0SPoul-Henning Kamp {"brcm,bcm2835-pwm", 1}, 549eec64c0SPoul-Henning Kamp {NULL, 0} 559eec64c0SPoul-Henning Kamp }; 569eec64c0SPoul-Henning Kamp 579eec64c0SPoul-Henning Kamp struct bcm_pwm_softc { 589eec64c0SPoul-Henning Kamp device_t sc_dev; 599eec64c0SPoul-Henning Kamp 609eec64c0SPoul-Henning Kamp struct resource * sc_mem_res; 619eec64c0SPoul-Henning Kamp bus_space_tag_t sc_m_bst; 629eec64c0SPoul-Henning Kamp bus_space_handle_t sc_m_bsh; 639eec64c0SPoul-Henning Kamp 64fc62b7e5SPoul-Henning Kamp device_t clkman; 659eec64c0SPoul-Henning Kamp 66*3f9b72b6SOleksandr Tymoshenko uint32_t freq; /* shared between channels 1 and 2 */ 67*3f9b72b6SOleksandr Tymoshenko uint32_t period; /* channel 1 */ 689eec64c0SPoul-Henning Kamp uint32_t ratio; 699eec64c0SPoul-Henning Kamp uint32_t mode; 70*3f9b72b6SOleksandr Tymoshenko uint32_t period2; /* channel 2 */ 71*3f9b72b6SOleksandr Tymoshenko uint32_t ratio2; 72*3f9b72b6SOleksandr Tymoshenko uint32_t mode2; 739eec64c0SPoul-Henning Kamp }; 749eec64c0SPoul-Henning Kamp 759eec64c0SPoul-Henning Kamp #define BCM_PWM_MEM_WRITE(_sc, _off, _val) \ 769eec64c0SPoul-Henning Kamp bus_space_write_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off, _val) 779eec64c0SPoul-Henning Kamp #define BCM_PWM_MEM_READ(_sc, _off) \ 789eec64c0SPoul-Henning Kamp bus_space_read_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off) 799eec64c0SPoul-Henning Kamp #define BCM_PWM_CLK_WRITE(_sc, _off, _val) \ 809eec64c0SPoul-Henning Kamp bus_space_write_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off, _val) 819eec64c0SPoul-Henning Kamp #define BCM_PWM_CLK_READ(_sc, _off) \ 829eec64c0SPoul-Henning Kamp bus_space_read_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off) 839eec64c0SPoul-Henning Kamp 849eec64c0SPoul-Henning Kamp #define W_CTL(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x00, _val) 859eec64c0SPoul-Henning Kamp #define R_CTL(_sc) BCM_PWM_MEM_READ(_sc, 0x00) 869eec64c0SPoul-Henning Kamp #define W_STA(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x04, _val) 879eec64c0SPoul-Henning Kamp #define R_STA(_sc) BCM_PWM_MEM_READ(_sc, 0x04) 889eec64c0SPoul-Henning Kamp #define W_RNG(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x10, _val) 899eec64c0SPoul-Henning Kamp #define R_RNG(_sc) BCM_PWM_MEM_READ(_sc, 0x10) 909eec64c0SPoul-Henning Kamp #define W_DAT(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x14, _val) 919eec64c0SPoul-Henning Kamp #define R_DAT(_sc) BCM_PWM_MEM_READ(_sc, 0x14) 92*3f9b72b6SOleksandr Tymoshenko #define W_RNG2(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x20, _val) 93*3f9b72b6SOleksandr Tymoshenko #define R_RNG2(_sc) BCM_PWM_MEM_READ(_sc, 0x20) 94*3f9b72b6SOleksandr Tymoshenko #define W_DAT2(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x24, _val) 95*3f9b72b6SOleksandr Tymoshenko #define R_DAT2(_sc) BCM_PWM_MEM_READ(_sc, 0x24) 969eec64c0SPoul-Henning Kamp 979eec64c0SPoul-Henning Kamp static int 989eec64c0SPoul-Henning Kamp bcm_pwm_reconf(struct bcm_pwm_softc *sc) 999eec64c0SPoul-Henning Kamp { 100*3f9b72b6SOleksandr Tymoshenko uint32_t u, ctlr; 1019eec64c0SPoul-Henning Kamp 1029eec64c0SPoul-Henning Kamp /* Disable PWM */ 1039eec64c0SPoul-Henning Kamp W_CTL(sc, 0); 1049eec64c0SPoul-Henning Kamp 1059eec64c0SPoul-Henning Kamp /* Stop PWM clock */ 106fc62b7e5SPoul-Henning Kamp (void)bcm2835_clkman_set_frequency(sc->clkman, BCM_PWM_CLKSRC, 0); 1079eec64c0SPoul-Henning Kamp 108*3f9b72b6SOleksandr Tymoshenko ctlr = 0; /* pre-assign zero, enable bits, write to CTL at end */ 1099eec64c0SPoul-Henning Kamp 110*3f9b72b6SOleksandr Tymoshenko if (sc->mode == 0 && sc->mode2 == 0) /* both modes are zero */ 111*3f9b72b6SOleksandr Tymoshenko return 0; /* device is now off - return */ 112*3f9b72b6SOleksandr Tymoshenko 113*3f9b72b6SOleksandr Tymoshenko /* set the PWM clock frequency */ 114*3f9b72b6SOleksandr Tymoshenko /* TODO: should I only do this if it changes and not stop it first? */ 115fc62b7e5SPoul-Henning Kamp u = bcm2835_clkman_set_frequency(sc->clkman, BCM_PWM_CLKSRC, sc->freq); 116fc62b7e5SPoul-Henning Kamp if (u == 0) 1179eec64c0SPoul-Henning Kamp return (EINVAL); 118fc62b7e5SPoul-Henning Kamp sc->freq = u; 1199eec64c0SPoul-Henning Kamp 120*3f9b72b6SOleksandr Tymoshenko /* control register CTL bits: 121*3f9b72b6SOleksandr Tymoshenko * (from BCM2835 ARM Peripherals manual, section 9.6) 122*3f9b72b6SOleksandr Tymoshenko * 123*3f9b72b6SOleksandr Tymoshenko * 15 MSEN2 chan 2 M/S enable; 0 for PWM algo, 1 for M/S transmission 124*3f9b72b6SOleksandr Tymoshenko * 14 unused; always reads as 0 125*3f9b72b6SOleksandr Tymoshenko * 13 USEF2 chan 2 use FIFO (0 uses data; 1 uses FIFO) 126*3f9b72b6SOleksandr Tymoshenko * 12 POLA2 chan 2 invert polarity (0 normal, 1 inverted polarity) 127*3f9b72b6SOleksandr Tymoshenko * 11 SBIT2 chan 2 'Silence' bit (when not transmitting data) 128*3f9b72b6SOleksandr Tymoshenko * 10 RPTL2 chan 2 FIFO repeat last data (1 repeats, 0 interrupts) 129*3f9b72b6SOleksandr Tymoshenko * 9 MODE2 chan 2 PWM/Serializer mode (0 PWM, 1 Serializer) 130*3f9b72b6SOleksandr Tymoshenko * 8 PWEN2 chan 2 enable (0 disable, 1 enable) 131*3f9b72b6SOleksandr Tymoshenko * 7 MSEN1 chan 1 M/S enable; 0 for PWM algo, 1 for M/S transmission 132*3f9b72b6SOleksandr Tymoshenko * 6 CLRF1 chan 1 clear FIFO (set 1 to clear; always reads as 0) 133*3f9b72b6SOleksandr Tymoshenko * 5 USEF1 chan 1 use FIFO (0 uses data; 1 uses FIFO) 134*3f9b72b6SOleksandr Tymoshenko * 4 POLA1 chan 1 invert polarity (0 normal, 1 inverted polarity) 135*3f9b72b6SOleksandr Tymoshenko * 3 SBIT1 chan 1 'Silence' bit (when not transmitting data) 136*3f9b72b6SOleksandr Tymoshenko * 2 RTPL1 chan 1 FIFO repeat last data (1 repeats, 0 interrupts) 137*3f9b72b6SOleksandr Tymoshenko * 1 MODE1 chan 1 PWM/Serializer mode (0 PWM, 1 Serializer) 138*3f9b72b6SOleksandr Tymoshenko * 0 PWMEN1 chan 1 enable (0 disable, 1 enable) 139*3f9b72b6SOleksandr Tymoshenko * 140*3f9b72b6SOleksandr Tymoshenko * Notes on M/S enable: when this bit is '1', a simple M/S ratio is used. In short, 141*3f9b72b6SOleksandr Tymoshenko * the value of 'ratio' is the number of 'on' bits, and the total length of the data is 142*3f9b72b6SOleksandr Tymoshenko * defined by 'period'. So if 'ratio' is 2500 and 'period' is 10000, then the output 143*3f9b72b6SOleksandr Tymoshenko * remains 'on' for 2500 clocks, and goes 'off' for the remaining 7500 clocks. 144*3f9b72b6SOleksandr Tymoshenko * When the M/S enable is '0', a more complicated algorithm effectively 'dithers' the 145*3f9b72b6SOleksandr Tymoshenko * pulses in order to obtain the desired ratio. For details, see section 9.3 of the 146*3f9b72b6SOleksandr Tymoshenko * BCM2835 ARM Peripherals manual. 147*3f9b72b6SOleksandr Tymoshenko */ 148*3f9b72b6SOleksandr Tymoshenko 149*3f9b72b6SOleksandr Tymoshenko if (sc->mode != 0) { 150*3f9b72b6SOleksandr Tymoshenko /* Config PWM Channel 1 */ 1519eec64c0SPoul-Henning Kamp W_RNG(sc, sc->period); 152137a344cSPoul-Henning Kamp if (sc->ratio > sc->period) 153137a344cSPoul-Henning Kamp sc->ratio = sc->period; 1549eec64c0SPoul-Henning Kamp W_DAT(sc, sc->ratio); 1559eec64c0SPoul-Henning Kamp 156*3f9b72b6SOleksandr Tymoshenko /* Start PWM Channel 1 */ 1579eec64c0SPoul-Henning Kamp if (sc->mode == 1) 158*3f9b72b6SOleksandr Tymoshenko ctlr |= 0x81; /* chan 1 enable + chan 1 M/S enable */ 1599eec64c0SPoul-Henning Kamp else 160*3f9b72b6SOleksandr Tymoshenko ctlr |= 0x1; /* chan 1 enable */ 161*3f9b72b6SOleksandr Tymoshenko } 162*3f9b72b6SOleksandr Tymoshenko 163*3f9b72b6SOleksandr Tymoshenko if (sc->mode2 != 0) { 164*3f9b72b6SOleksandr Tymoshenko /* Config PWM Channel 2 */ 165*3f9b72b6SOleksandr Tymoshenko W_RNG2(sc, sc->period2); 166*3f9b72b6SOleksandr Tymoshenko if (sc->ratio2 > sc->period2) 167*3f9b72b6SOleksandr Tymoshenko sc->ratio2 = sc->period2; 168*3f9b72b6SOleksandr Tymoshenko W_DAT2(sc, sc->ratio2); 169*3f9b72b6SOleksandr Tymoshenko 170*3f9b72b6SOleksandr Tymoshenko /* Start PWM Channel 2 */ 171*3f9b72b6SOleksandr Tymoshenko if (sc->mode2 == 1) 172*3f9b72b6SOleksandr Tymoshenko ctlr |= 0x8100; /* chan 2 enable + chan 2 M/S enable */ 173*3f9b72b6SOleksandr Tymoshenko else 174*3f9b72b6SOleksandr Tymoshenko ctlr |= 0x100; /* chan 2 enable */ 175*3f9b72b6SOleksandr Tymoshenko } 176*3f9b72b6SOleksandr Tymoshenko 177*3f9b72b6SOleksandr Tymoshenko /* write CTL register with updated value */ 178*3f9b72b6SOleksandr Tymoshenko W_CTL(sc, ctlr); 1799eec64c0SPoul-Henning Kamp 1809eec64c0SPoul-Henning Kamp return (0); 1819eec64c0SPoul-Henning Kamp } 1829eec64c0SPoul-Henning Kamp 1839eec64c0SPoul-Henning Kamp static int 1849eec64c0SPoul-Henning Kamp bcm_pwm_pwm_freq_proc(SYSCTL_HANDLER_ARGS) 1859eec64c0SPoul-Henning Kamp { 1869eec64c0SPoul-Henning Kamp struct bcm_pwm_softc *sc; 1879eec64c0SPoul-Henning Kamp uint32_t r; 1889eec64c0SPoul-Henning Kamp int error; 1899eec64c0SPoul-Henning Kamp 1909eec64c0SPoul-Henning Kamp sc = (struct bcm_pwm_softc *)arg1; 1919eec64c0SPoul-Henning Kamp if (sc->mode == 1) 1929eec64c0SPoul-Henning Kamp r = sc->freq / sc->period; 1939eec64c0SPoul-Henning Kamp else 1949eec64c0SPoul-Henning Kamp r = 0; 1959eec64c0SPoul-Henning Kamp error = sysctl_handle_int(oidp, &r, sizeof(r), req); 1969eec64c0SPoul-Henning Kamp return (error); 1979eec64c0SPoul-Henning Kamp } 1989eec64c0SPoul-Henning Kamp 1999eec64c0SPoul-Henning Kamp static int 2009eec64c0SPoul-Henning Kamp bcm_pwm_mode_proc(SYSCTL_HANDLER_ARGS) 2019eec64c0SPoul-Henning Kamp { 2029eec64c0SPoul-Henning Kamp struct bcm_pwm_softc *sc; 2039eec64c0SPoul-Henning Kamp uint32_t r; 2049eec64c0SPoul-Henning Kamp int error; 2059eec64c0SPoul-Henning Kamp 2069eec64c0SPoul-Henning Kamp sc = (struct bcm_pwm_softc *)arg1; 2079eec64c0SPoul-Henning Kamp r = sc->mode; 2089eec64c0SPoul-Henning Kamp error = sysctl_handle_int(oidp, &r, sizeof(r), req); 2099eec64c0SPoul-Henning Kamp if (error != 0 || req->newptr == NULL) 2109eec64c0SPoul-Henning Kamp return (error); 2119eec64c0SPoul-Henning Kamp if (r > 2) 2129eec64c0SPoul-Henning Kamp return (EINVAL); 2139eec64c0SPoul-Henning Kamp sc->mode = r; 2149eec64c0SPoul-Henning Kamp return (bcm_pwm_reconf(sc)); 2159eec64c0SPoul-Henning Kamp } 2169eec64c0SPoul-Henning Kamp 2179eec64c0SPoul-Henning Kamp static int 2189eec64c0SPoul-Henning Kamp bcm_pwm_freq_proc(SYSCTL_HANDLER_ARGS) 2199eec64c0SPoul-Henning Kamp { 2209eec64c0SPoul-Henning Kamp struct bcm_pwm_softc *sc; 2219eec64c0SPoul-Henning Kamp uint32_t r; 2229eec64c0SPoul-Henning Kamp int error; 2239eec64c0SPoul-Henning Kamp 2249eec64c0SPoul-Henning Kamp sc = (struct bcm_pwm_softc *)arg1; 2259eec64c0SPoul-Henning Kamp r = sc->freq; 2269eec64c0SPoul-Henning Kamp error = sysctl_handle_int(oidp, &r, sizeof(r), req); 2279eec64c0SPoul-Henning Kamp if (error != 0 || req->newptr == NULL) 2289eec64c0SPoul-Henning Kamp return (error); 2299eec64c0SPoul-Henning Kamp if (r > 125000000) 2309eec64c0SPoul-Henning Kamp return (EINVAL); 2319eec64c0SPoul-Henning Kamp sc->freq = r; 2329eec64c0SPoul-Henning Kamp return (bcm_pwm_reconf(sc)); 2339eec64c0SPoul-Henning Kamp } 2349eec64c0SPoul-Henning Kamp 2359eec64c0SPoul-Henning Kamp static int 2369eec64c0SPoul-Henning Kamp bcm_pwm_period_proc(SYSCTL_HANDLER_ARGS) 2379eec64c0SPoul-Henning Kamp { 2389eec64c0SPoul-Henning Kamp struct bcm_pwm_softc *sc; 2399eec64c0SPoul-Henning Kamp int error; 2409eec64c0SPoul-Henning Kamp 2419eec64c0SPoul-Henning Kamp sc = (struct bcm_pwm_softc *)arg1; 2429eec64c0SPoul-Henning Kamp error = sysctl_handle_int(oidp, &sc->period, sizeof(sc->period), req); 2439eec64c0SPoul-Henning Kamp if (error != 0 || req->newptr == NULL) 2449eec64c0SPoul-Henning Kamp return (error); 2459eec64c0SPoul-Henning Kamp return (bcm_pwm_reconf(sc)); 2469eec64c0SPoul-Henning Kamp } 2479eec64c0SPoul-Henning Kamp 2489eec64c0SPoul-Henning Kamp static int 2499eec64c0SPoul-Henning Kamp bcm_pwm_ratio_proc(SYSCTL_HANDLER_ARGS) 2509eec64c0SPoul-Henning Kamp { 2519eec64c0SPoul-Henning Kamp struct bcm_pwm_softc *sc; 2529eec64c0SPoul-Henning Kamp uint32_t r; 2539eec64c0SPoul-Henning Kamp int error; 2549eec64c0SPoul-Henning Kamp 2559eec64c0SPoul-Henning Kamp sc = (struct bcm_pwm_softc *)arg1; 2569eec64c0SPoul-Henning Kamp r = sc->ratio; 2579eec64c0SPoul-Henning Kamp error = sysctl_handle_int(oidp, &r, sizeof(r), req); 2589eec64c0SPoul-Henning Kamp if (error != 0 || req->newptr == NULL) 2599eec64c0SPoul-Henning Kamp return (error); 2609eec64c0SPoul-Henning Kamp if (r > sc->period) // XXX >= ? 2619eec64c0SPoul-Henning Kamp return (EINVAL); 2629eec64c0SPoul-Henning Kamp sc->ratio = r; 263*3f9b72b6SOleksandr Tymoshenko W_DAT(sc, sc->ratio); 264*3f9b72b6SOleksandr Tymoshenko return (0); 265*3f9b72b6SOleksandr Tymoshenko } 266*3f9b72b6SOleksandr Tymoshenko 267*3f9b72b6SOleksandr Tymoshenko static int 268*3f9b72b6SOleksandr Tymoshenko bcm_pwm_pwm_freq2_proc(SYSCTL_HANDLER_ARGS) 269*3f9b72b6SOleksandr Tymoshenko { 270*3f9b72b6SOleksandr Tymoshenko struct bcm_pwm_softc *sc; 271*3f9b72b6SOleksandr Tymoshenko uint32_t r; 272*3f9b72b6SOleksandr Tymoshenko int error; 273*3f9b72b6SOleksandr Tymoshenko 274*3f9b72b6SOleksandr Tymoshenko sc = (struct bcm_pwm_softc *)arg1; 275*3f9b72b6SOleksandr Tymoshenko if (sc->mode2 == 1) 276*3f9b72b6SOleksandr Tymoshenko r = sc->freq / sc->period2; 277*3f9b72b6SOleksandr Tymoshenko else 278*3f9b72b6SOleksandr Tymoshenko r = 0; 279*3f9b72b6SOleksandr Tymoshenko error = sysctl_handle_int(oidp, &r, sizeof(r), req); 280*3f9b72b6SOleksandr Tymoshenko return (error); 281*3f9b72b6SOleksandr Tymoshenko } 282*3f9b72b6SOleksandr Tymoshenko 283*3f9b72b6SOleksandr Tymoshenko static int 284*3f9b72b6SOleksandr Tymoshenko bcm_pwm_mode2_proc(SYSCTL_HANDLER_ARGS) 285*3f9b72b6SOleksandr Tymoshenko { 286*3f9b72b6SOleksandr Tymoshenko struct bcm_pwm_softc *sc; 287*3f9b72b6SOleksandr Tymoshenko uint32_t r; 288*3f9b72b6SOleksandr Tymoshenko int error; 289*3f9b72b6SOleksandr Tymoshenko 290*3f9b72b6SOleksandr Tymoshenko sc = (struct bcm_pwm_softc *)arg1; 291*3f9b72b6SOleksandr Tymoshenko r = sc->mode2; 292*3f9b72b6SOleksandr Tymoshenko error = sysctl_handle_int(oidp, &r, sizeof(r), req); 293*3f9b72b6SOleksandr Tymoshenko if (error != 0 || req->newptr == NULL) 294*3f9b72b6SOleksandr Tymoshenko return (error); 295*3f9b72b6SOleksandr Tymoshenko if (r > 2) 296*3f9b72b6SOleksandr Tymoshenko return (EINVAL); 297*3f9b72b6SOleksandr Tymoshenko sc->mode2 = r; 298*3f9b72b6SOleksandr Tymoshenko return (bcm_pwm_reconf(sc)); 299*3f9b72b6SOleksandr Tymoshenko } 300*3f9b72b6SOleksandr Tymoshenko 301*3f9b72b6SOleksandr Tymoshenko static int 302*3f9b72b6SOleksandr Tymoshenko bcm_pwm_period2_proc(SYSCTL_HANDLER_ARGS) 303*3f9b72b6SOleksandr Tymoshenko { 304*3f9b72b6SOleksandr Tymoshenko struct bcm_pwm_softc *sc; 305*3f9b72b6SOleksandr Tymoshenko int error; 306*3f9b72b6SOleksandr Tymoshenko 307*3f9b72b6SOleksandr Tymoshenko sc = (struct bcm_pwm_softc *)arg1; 308*3f9b72b6SOleksandr Tymoshenko error = sysctl_handle_int(oidp, &sc->period2, sizeof(sc->period2), req); 309*3f9b72b6SOleksandr Tymoshenko if (error != 0 || req->newptr == NULL) 310*3f9b72b6SOleksandr Tymoshenko return (error); 311*3f9b72b6SOleksandr Tymoshenko return (bcm_pwm_reconf(sc)); 312*3f9b72b6SOleksandr Tymoshenko } 313*3f9b72b6SOleksandr Tymoshenko 314*3f9b72b6SOleksandr Tymoshenko static int 315*3f9b72b6SOleksandr Tymoshenko bcm_pwm_ratio2_proc(SYSCTL_HANDLER_ARGS) 316*3f9b72b6SOleksandr Tymoshenko { 317*3f9b72b6SOleksandr Tymoshenko struct bcm_pwm_softc *sc; 318*3f9b72b6SOleksandr Tymoshenko uint32_t r; 319*3f9b72b6SOleksandr Tymoshenko int error; 320*3f9b72b6SOleksandr Tymoshenko 321*3f9b72b6SOleksandr Tymoshenko sc = (struct bcm_pwm_softc *)arg1; 322*3f9b72b6SOleksandr Tymoshenko r = sc->ratio2; 323*3f9b72b6SOleksandr Tymoshenko error = sysctl_handle_int(oidp, &r, sizeof(r), req); 324*3f9b72b6SOleksandr Tymoshenko if (error != 0 || req->newptr == NULL) 325*3f9b72b6SOleksandr Tymoshenko return (error); 326*3f9b72b6SOleksandr Tymoshenko if (r > sc->period2) // XXX >= ? 327*3f9b72b6SOleksandr Tymoshenko return (EINVAL); 328*3f9b72b6SOleksandr Tymoshenko sc->ratio2 = r; 329*3f9b72b6SOleksandr Tymoshenko W_DAT(sc, sc->ratio2); 3309eec64c0SPoul-Henning Kamp return (0); 3319eec64c0SPoul-Henning Kamp } 3329eec64c0SPoul-Henning Kamp 3339eec64c0SPoul-Henning Kamp static int 3349eec64c0SPoul-Henning Kamp bcm_pwm_reg_proc(SYSCTL_HANDLER_ARGS) 3359eec64c0SPoul-Henning Kamp { 3369eec64c0SPoul-Henning Kamp struct bcm_pwm_softc *sc; 3379eec64c0SPoul-Henning Kamp uint32_t reg; 3389eec64c0SPoul-Henning Kamp int error; 3399eec64c0SPoul-Henning Kamp 3409eec64c0SPoul-Henning Kamp sc = (struct bcm_pwm_softc *)arg1; 3419eec64c0SPoul-Henning Kamp reg = BCM_PWM_MEM_READ(sc, arg2 & 0xff); 3429eec64c0SPoul-Henning Kamp 3439eec64c0SPoul-Henning Kamp error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 3449eec64c0SPoul-Henning Kamp if (error != 0 || req->newptr == NULL) 3459eec64c0SPoul-Henning Kamp return (error); 3469eec64c0SPoul-Henning Kamp 3479eec64c0SPoul-Henning Kamp BCM_PWM_MEM_WRITE(sc, arg2, reg); 3489eec64c0SPoul-Henning Kamp return (0); 3499eec64c0SPoul-Henning Kamp } 3509eec64c0SPoul-Henning Kamp 3519eec64c0SPoul-Henning Kamp static void 3529eec64c0SPoul-Henning Kamp bcm_pwm_sysctl_init(struct bcm_pwm_softc *sc) 3539eec64c0SPoul-Henning Kamp { 3549eec64c0SPoul-Henning Kamp struct sysctl_ctx_list *ctx; 3559eec64c0SPoul-Henning Kamp struct sysctl_oid *tree_node; 3569eec64c0SPoul-Henning Kamp struct sysctl_oid_list *tree; 3579eec64c0SPoul-Henning Kamp 3589eec64c0SPoul-Henning Kamp /* 3599eec64c0SPoul-Henning Kamp * Add system sysctl tree/handlers. 3609eec64c0SPoul-Henning Kamp */ 3619eec64c0SPoul-Henning Kamp ctx = device_get_sysctl_ctx(sc->sc_dev); 3629eec64c0SPoul-Henning Kamp tree_node = device_get_sysctl_tree(sc->sc_dev); 3639eec64c0SPoul-Henning Kamp tree = SYSCTL_CHILDREN(tree_node); 3649eec64c0SPoul-Henning Kamp if (bootverbose) { 3659eec64c0SPoul-Henning Kamp #define RR(x,y) \ 3669eec64c0SPoul-Henning Kamp SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, y, \ 3679eec64c0SPoul-Henning Kamp CTLFLAG_RW | CTLTYPE_UINT, sc, 0x##x, \ 3689eec64c0SPoul-Henning Kamp bcm_pwm_reg_proc, "IU", "Register 0x" #x " " y); 3699eec64c0SPoul-Henning Kamp 3709eec64c0SPoul-Henning Kamp RR(24, "DAT2") 3719eec64c0SPoul-Henning Kamp RR(20, "RNG2") 3729eec64c0SPoul-Henning Kamp RR(18, "FIF1") 3739eec64c0SPoul-Henning Kamp RR(14, "DAT1") 3749eec64c0SPoul-Henning Kamp RR(10, "RNG1") 3759eec64c0SPoul-Henning Kamp RR(08, "DMAC") 3769eec64c0SPoul-Henning Kamp RR(04, "STA") 3779eec64c0SPoul-Henning Kamp RR(00, "CTL") 3789eec64c0SPoul-Henning Kamp #undef RR 3799eec64c0SPoul-Henning Kamp } 3809eec64c0SPoul-Henning Kamp 3819eec64c0SPoul-Henning Kamp SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "pwm_freq", 3829eec64c0SPoul-Henning Kamp CTLFLAG_RD | CTLTYPE_UINT, sc, 0, 383*3f9b72b6SOleksandr Tymoshenko bcm_pwm_pwm_freq_proc, "IU", "PWM frequency ch 1 (Hz)"); 3849eec64c0SPoul-Henning Kamp SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "period", 3859eec64c0SPoul-Henning Kamp CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 386*3f9b72b6SOleksandr Tymoshenko bcm_pwm_period_proc, "IU", "PWM period ch 1 (#clocks)"); 3879eec64c0SPoul-Henning Kamp SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "ratio", 3889eec64c0SPoul-Henning Kamp CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 389*3f9b72b6SOleksandr Tymoshenko bcm_pwm_ratio_proc, "IU", "PWM ratio ch 1 (0...period)"); 3909eec64c0SPoul-Henning Kamp SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "freq", 3919eec64c0SPoul-Henning Kamp CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 3929eec64c0SPoul-Henning Kamp bcm_pwm_freq_proc, "IU", "PWM clock (Hz)"); 3939eec64c0SPoul-Henning Kamp SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "mode", 3949eec64c0SPoul-Henning Kamp CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 395*3f9b72b6SOleksandr Tymoshenko bcm_pwm_mode_proc, "IU", "PWM mode ch 1 (0=off, 1=pwm, 2=dither)"); 396*3f9b72b6SOleksandr Tymoshenko SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "pwm_freq2", 397*3f9b72b6SOleksandr Tymoshenko CTLFLAG_RD | CTLTYPE_UINT, sc, 0, 398*3f9b72b6SOleksandr Tymoshenko bcm_pwm_pwm_freq2_proc, "IU", "PWM frequency ch 2 (Hz)"); 399*3f9b72b6SOleksandr Tymoshenko SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "period2", 400*3f9b72b6SOleksandr Tymoshenko CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 401*3f9b72b6SOleksandr Tymoshenko bcm_pwm_period2_proc, "IU", "PWM period ch 2 (#clocks)"); 402*3f9b72b6SOleksandr Tymoshenko SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "ratio2", 403*3f9b72b6SOleksandr Tymoshenko CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 404*3f9b72b6SOleksandr Tymoshenko bcm_pwm_ratio2_proc, "IU", "PWM ratio ch 2 (0...period)"); 405*3f9b72b6SOleksandr Tymoshenko SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "mode2", 406*3f9b72b6SOleksandr Tymoshenko CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 407*3f9b72b6SOleksandr Tymoshenko bcm_pwm_mode2_proc, "IU", "PWM mode ch 2 (0=off, 1=pwm, 2=dither)"); 4089eec64c0SPoul-Henning Kamp } 4099eec64c0SPoul-Henning Kamp 4109eec64c0SPoul-Henning Kamp static int 4119eec64c0SPoul-Henning Kamp bcm_pwm_probe(device_t dev) 4129eec64c0SPoul-Henning Kamp { 4139eec64c0SPoul-Henning Kamp 4149eec64c0SPoul-Henning Kamp if (!ofw_bus_status_okay(dev)) 4159eec64c0SPoul-Henning Kamp return (ENXIO); 4169eec64c0SPoul-Henning Kamp 4179eec64c0SPoul-Henning Kamp if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 4189eec64c0SPoul-Henning Kamp return (ENXIO); 4199eec64c0SPoul-Henning Kamp 4209eec64c0SPoul-Henning Kamp device_set_desc(dev, "BCM2708/2835 PWM controller"); 4219eec64c0SPoul-Henning Kamp 4229eec64c0SPoul-Henning Kamp return (BUS_PROBE_DEFAULT); 4239eec64c0SPoul-Henning Kamp } 4249eec64c0SPoul-Henning Kamp 4259eec64c0SPoul-Henning Kamp static int 4269eec64c0SPoul-Henning Kamp bcm_pwm_attach(device_t dev) 4279eec64c0SPoul-Henning Kamp { 4289eec64c0SPoul-Henning Kamp struct bcm_pwm_softc *sc; 4299eec64c0SPoul-Henning Kamp int rid; 4309eec64c0SPoul-Henning Kamp 4319eec64c0SPoul-Henning Kamp if (device_get_unit(dev) != 0) { 4329eec64c0SPoul-Henning Kamp device_printf(dev, "only one PWM controller supported\n"); 4339eec64c0SPoul-Henning Kamp return (ENXIO); 4349eec64c0SPoul-Henning Kamp } 4359eec64c0SPoul-Henning Kamp 4369eec64c0SPoul-Henning Kamp sc = device_get_softc(dev); 4379eec64c0SPoul-Henning Kamp sc->sc_dev = dev; 4389eec64c0SPoul-Henning Kamp 439fc62b7e5SPoul-Henning Kamp sc->clkman = devclass_get_device(devclass_find("bcm2835_clkman"), 0); 440fc62b7e5SPoul-Henning Kamp if (sc->clkman == NULL) { 441fc62b7e5SPoul-Henning Kamp device_printf(dev, "cannot find Clock Manager\n"); 442fc62b7e5SPoul-Henning Kamp return (ENXIO); 443fc62b7e5SPoul-Henning Kamp } 444fc62b7e5SPoul-Henning Kamp 4459eec64c0SPoul-Henning Kamp rid = 0; 4469eec64c0SPoul-Henning Kamp sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 4479eec64c0SPoul-Henning Kamp RF_ACTIVE); 4489eec64c0SPoul-Henning Kamp if (!sc->sc_mem_res) { 4499eec64c0SPoul-Henning Kamp device_printf(dev, "cannot allocate memory window\n"); 4509eec64c0SPoul-Henning Kamp return (ENXIO); 4519eec64c0SPoul-Henning Kamp } 4529eec64c0SPoul-Henning Kamp 4539eec64c0SPoul-Henning Kamp sc->sc_m_bst = rman_get_bustag(sc->sc_mem_res); 4549eec64c0SPoul-Henning Kamp sc->sc_m_bsh = rman_get_bushandle(sc->sc_mem_res); 4559eec64c0SPoul-Henning Kamp 4569eec64c0SPoul-Henning Kamp /* Add sysctl nodes. */ 4579eec64c0SPoul-Henning Kamp bcm_pwm_sysctl_init(sc); 4589eec64c0SPoul-Henning Kamp 459*3f9b72b6SOleksandr Tymoshenko sc->freq = 125000000; /* 125 Mhz */ 460*3f9b72b6SOleksandr Tymoshenko sc->period = 10000; /* 12.5 khz */ 461*3f9b72b6SOleksandr Tymoshenko sc->ratio = 2500; /* 25% */ 462*3f9b72b6SOleksandr Tymoshenko sc->period2 = 10000; /* 12.5 khz */ 463*3f9b72b6SOleksandr Tymoshenko sc->ratio2 = 2500; /* 25% */ 4649eec64c0SPoul-Henning Kamp 4659eec64c0SPoul-Henning Kamp return (bus_generic_attach(dev)); 4669eec64c0SPoul-Henning Kamp } 4679eec64c0SPoul-Henning Kamp 4689eec64c0SPoul-Henning Kamp static int 4699eec64c0SPoul-Henning Kamp bcm_pwm_detach(device_t dev) 4709eec64c0SPoul-Henning Kamp { 4719eec64c0SPoul-Henning Kamp struct bcm_pwm_softc *sc; 4729eec64c0SPoul-Henning Kamp 4739eec64c0SPoul-Henning Kamp bus_generic_detach(dev); 4749eec64c0SPoul-Henning Kamp 4759eec64c0SPoul-Henning Kamp sc = device_get_softc(dev); 4769eec64c0SPoul-Henning Kamp sc->mode = 0; 477*3f9b72b6SOleksandr Tymoshenko sc->mode2 = 0; 4789eec64c0SPoul-Henning Kamp (void)bcm_pwm_reconf(sc); 4799eec64c0SPoul-Henning Kamp if (sc->sc_mem_res) 4809eec64c0SPoul-Henning Kamp bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 4819eec64c0SPoul-Henning Kamp 4829eec64c0SPoul-Henning Kamp return (0); 4839eec64c0SPoul-Henning Kamp } 4849eec64c0SPoul-Henning Kamp 4859eec64c0SPoul-Henning Kamp static phandle_t 4869eec64c0SPoul-Henning Kamp bcm_pwm_get_node(device_t bus, device_t dev) 4879eec64c0SPoul-Henning Kamp { 4889eec64c0SPoul-Henning Kamp 4899eec64c0SPoul-Henning Kamp return (ofw_bus_get_node(bus)); 4909eec64c0SPoul-Henning Kamp } 4919eec64c0SPoul-Henning Kamp 492fc62b7e5SPoul-Henning Kamp 4939eec64c0SPoul-Henning Kamp static device_method_t bcm_pwm_methods[] = { 4949eec64c0SPoul-Henning Kamp /* Device interface */ 4959eec64c0SPoul-Henning Kamp DEVMETHOD(device_probe, bcm_pwm_probe), 4969eec64c0SPoul-Henning Kamp DEVMETHOD(device_attach, bcm_pwm_attach), 4979eec64c0SPoul-Henning Kamp DEVMETHOD(device_detach, bcm_pwm_detach), 4989eec64c0SPoul-Henning Kamp DEVMETHOD(ofw_bus_get_node, bcm_pwm_get_node), 4999eec64c0SPoul-Henning Kamp 5009eec64c0SPoul-Henning Kamp DEVMETHOD_END 5019eec64c0SPoul-Henning Kamp }; 5029eec64c0SPoul-Henning Kamp 5039eec64c0SPoul-Henning Kamp static devclass_t bcm_pwm_devclass; 5049eec64c0SPoul-Henning Kamp 5059eec64c0SPoul-Henning Kamp static driver_t bcm_pwm_driver = { 5069eec64c0SPoul-Henning Kamp "pwm", 5079eec64c0SPoul-Henning Kamp bcm_pwm_methods, 5089eec64c0SPoul-Henning Kamp sizeof(struct bcm_pwm_softc), 5099eec64c0SPoul-Henning Kamp }; 5109eec64c0SPoul-Henning Kamp 5119eec64c0SPoul-Henning Kamp DRIVER_MODULE(bcm2835_pwm, simplebus, bcm_pwm_driver, bcm_pwm_devclass, 0, 0); 512fc62b7e5SPoul-Henning Kamp MODULE_DEPEND(bcm2835_pwm, bcm2835_clkman, 1, 1, 1); 513