1 /*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Based on OMAP3 INTC code by Ben Gray 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_platform.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/ktr.h> 40 #include <sys/module.h> 41 #include <sys/proc.h> 42 #include <sys/rman.h> 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/fdt/fdt_common.h> 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include "pic_if.h" 52 53 #define INTC_PENDING_BASIC 0x00 54 #define INTC_PENDING_BANK1 0x04 55 #define INTC_PENDING_BANK2 0x08 56 #define INTC_FIQ_CONTROL 0x0C 57 #define INTC_ENABLE_BANK1 0x10 58 #define INTC_ENABLE_BANK2 0x14 59 #define INTC_ENABLE_BASIC 0x18 60 #define INTC_DISABLE_BANK1 0x1C 61 #define INTC_DISABLE_BANK2 0x20 62 #define INTC_DISABLE_BASIC 0x24 63 64 #define INTC_PENDING_BASIC_ARM 0x0000FF 65 #define INTC_PENDING_BASIC_GPU1_PEND 0x000100 66 #define INTC_PENDING_BASIC_GPU2_PEND 0x000200 67 #define INTC_PENDING_BASIC_GPU1_7 0x000400 68 #define INTC_PENDING_BASIC_GPU1_9 0x000800 69 #define INTC_PENDING_BASIC_GPU1_10 0x001000 70 #define INTC_PENDING_BASIC_GPU1_18 0x002000 71 #define INTC_PENDING_BASIC_GPU1_19 0x004000 72 #define INTC_PENDING_BASIC_GPU2_21 0x008000 73 #define INTC_PENDING_BASIC_GPU2_22 0x010000 74 #define INTC_PENDING_BASIC_GPU2_23 0x020000 75 #define INTC_PENDING_BASIC_GPU2_24 0x040000 76 #define INTC_PENDING_BASIC_GPU2_25 0x080000 77 #define INTC_PENDING_BASIC_GPU2_30 0x100000 78 #define INTC_PENDING_BASIC_MASK 0x1FFFFF 79 80 #define INTC_PENDING_BASIC_GPU1_MASK (INTC_PENDING_BASIC_GPU1_7 | \ 81 INTC_PENDING_BASIC_GPU1_9 | \ 82 INTC_PENDING_BASIC_GPU1_10 | \ 83 INTC_PENDING_BASIC_GPU1_18 | \ 84 INTC_PENDING_BASIC_GPU1_19) 85 86 #define INTC_PENDING_BASIC_GPU2_MASK (INTC_PENDING_BASIC_GPU2_21 | \ 87 INTC_PENDING_BASIC_GPU2_22 | \ 88 INTC_PENDING_BASIC_GPU2_23 | \ 89 INTC_PENDING_BASIC_GPU2_24 | \ 90 INTC_PENDING_BASIC_GPU2_25 | \ 91 INTC_PENDING_BASIC_GPU2_30) 92 93 #define INTC_PENDING_BANK1_MASK (~((1 << 7) | (1 << 9) | (1 << 10) | \ 94 (1 << 18) | (1 << 19))) 95 #define INTC_PENDING_BANK2_MASK (~((1 << 21) | (1 << 22) | (1 << 23) | \ 96 (1 << 24) | (1 << 25) | (1 << 30))) 97 98 #define BANK1_START 8 99 #define BANK1_END (BANK1_START + 32 - 1) 100 #define BANK2_START (BANK1_START + 32) 101 #define BANK2_END (BANK2_START + 32 - 1) 102 103 #define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START)) 104 #define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END)) 105 #define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END)) 106 #define IRQ_BANK1(n) ((n) - BANK1_START) 107 #define IRQ_BANK2(n) ((n) - BANK2_START) 108 109 #ifdef DEBUG 110 #define dprintf(fmt, args...) printf(fmt, ##args) 111 #else 112 #define dprintf(fmt, args...) 113 #endif 114 115 #define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */ 116 117 struct bcm_intc_irqsrc { 118 struct intr_irqsrc bii_isrc; 119 u_int bii_irq; 120 uint16_t bii_disable_reg; 121 uint16_t bii_enable_reg; 122 uint32_t bii_mask; 123 }; 124 125 struct bcm_intc_softc { 126 device_t sc_dev; 127 struct resource * intc_res; 128 bus_space_tag_t intc_bst; 129 bus_space_handle_t intc_bsh; 130 struct resource * intc_irq_res; 131 void * intc_irq_hdl; 132 struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS]; 133 }; 134 135 static struct bcm_intc_softc *bcm_intc_sc = NULL; 136 137 #define intc_read_4(_sc, reg) \ 138 bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg)) 139 #define intc_write_4(_sc, reg, val) \ 140 bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val)) 141 142 static inline void 143 bcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 144 { 145 146 intc_write_4(sc, bii->bii_disable_reg, bii->bii_mask); 147 } 148 149 static inline void 150 bcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 151 { 152 153 intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask); 154 } 155 156 static inline int 157 bcm2835_intc_active_intr(struct bcm_intc_softc *sc) 158 { 159 uint32_t pending, pending_gpu; 160 161 pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK; 162 if (pending == 0) 163 return (-1); 164 if (pending & INTC_PENDING_BASIC_ARM) 165 return (ffs(pending) - 1); 166 if (pending & INTC_PENDING_BASIC_GPU1_MASK) { 167 if (pending & INTC_PENDING_BASIC_GPU1_7) 168 return (BANK1_START + 7); 169 if (pending & INTC_PENDING_BASIC_GPU1_9) 170 return (BANK1_START + 9); 171 if (pending & INTC_PENDING_BASIC_GPU1_10) 172 return (BANK1_START + 10); 173 if (pending & INTC_PENDING_BASIC_GPU1_18) 174 return (BANK1_START + 18); 175 if (pending & INTC_PENDING_BASIC_GPU1_19) 176 return (BANK1_START + 19); 177 } 178 if (pending & INTC_PENDING_BASIC_GPU2_MASK) { 179 if (pending & INTC_PENDING_BASIC_GPU2_21) 180 return (BANK2_START + 21); 181 if (pending & INTC_PENDING_BASIC_GPU2_22) 182 return (BANK2_START + 22); 183 if (pending & INTC_PENDING_BASIC_GPU2_23) 184 return (BANK2_START + 23); 185 if (pending & INTC_PENDING_BASIC_GPU2_24) 186 return (BANK2_START + 24); 187 if (pending & INTC_PENDING_BASIC_GPU2_25) 188 return (BANK2_START + 25); 189 if (pending & INTC_PENDING_BASIC_GPU2_30) 190 return (BANK2_START + 30); 191 } 192 if (pending & INTC_PENDING_BASIC_GPU1_PEND) { 193 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1); 194 pending_gpu &= INTC_PENDING_BANK1_MASK; 195 if (pending_gpu != 0) 196 return (BANK1_START + ffs(pending_gpu) - 1); 197 } 198 if (pending & INTC_PENDING_BASIC_GPU2_PEND) { 199 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2); 200 pending_gpu &= INTC_PENDING_BANK2_MASK; 201 if (pending_gpu != 0) 202 return (BANK2_START + ffs(pending_gpu) - 1); 203 } 204 return (-1); /* It shouldn't end here, but it's hardware. */ 205 } 206 207 static int 208 bcm2835_intc_intr(void *arg) 209 { 210 int irq, num; 211 struct bcm_intc_softc *sc = arg; 212 213 for (num = 0; ; num++) { 214 irq = bcm2835_intc_active_intr(sc); 215 if (irq == -1) 216 break; 217 if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc, 218 curthread->td_intr_frame) != 0) { 219 bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]); 220 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 221 irq); 222 } 223 arm_irq_memory_barrier(0); /* XXX */ 224 } 225 if (num == 0) 226 device_printf(sc->sc_dev, "Spurious interrupt detected\n"); 227 228 return (FILTER_HANDLED); 229 } 230 231 static void 232 bcm_intc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 233 { 234 struct bcm_intc_irqsrc *bii = (struct bcm_intc_irqsrc *)isrc; 235 236 arm_irq_memory_barrier(bii->bii_irq); 237 bcm_intc_isrc_unmask(device_get_softc(dev), bii); 238 } 239 240 static void 241 bcm_intc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 242 { 243 244 bcm_intc_isrc_mask(device_get_softc(dev), 245 (struct bcm_intc_irqsrc *)isrc); 246 } 247 248 static int 249 bcm_intc_map_intr(device_t dev, struct intr_map_data *data, 250 struct intr_irqsrc **isrcp) 251 { 252 u_int irq; 253 struct intr_map_data_fdt *daf; 254 struct bcm_intc_softc *sc; 255 bool valid; 256 257 if (data->type != INTR_MAP_DATA_FDT) 258 return (ENOTSUP); 259 260 daf = (struct intr_map_data_fdt *)data; 261 if (daf->ncells == 1) 262 irq = daf->cells[0]; 263 else if (daf->ncells == 2) { 264 valid = true; 265 switch (daf->cells[0]) { 266 case 0: 267 irq = daf->cells[1]; 268 if (irq >= BANK1_START) 269 valid = false; 270 break; 271 case 1: 272 irq = daf->cells[1] + BANK1_START; 273 if (irq > BANK1_END) 274 valid = false; 275 break; 276 case 2: 277 irq = daf->cells[1] + BANK2_START; 278 if (irq > BANK2_END) 279 valid = false; 280 break; 281 default: 282 valid = false; 283 break; 284 } 285 286 if (!valid) { 287 device_printf(dev, 288 "invalid IRQ config: bank=%d, irq=%d\n", 289 daf->cells[0], daf->cells[1]); 290 return (EINVAL); 291 } 292 } 293 else 294 return (EINVAL); 295 296 if (irq >= BCM_INTC_NIRQS) 297 return (EINVAL); 298 299 sc = device_get_softc(dev); 300 *isrcp = &sc->intc_isrcs[irq].bii_isrc; 301 return (0); 302 } 303 304 static void 305 bcm_intc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 306 { 307 308 bcm_intc_disable_intr(dev, isrc); 309 } 310 311 static void 312 bcm_intc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 313 { 314 315 bcm_intc_enable_intr(dev, isrc); 316 } 317 318 static void 319 bcm_intc_post_filter(device_t dev, struct intr_irqsrc *isrc) 320 { 321 } 322 323 static int 324 bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref) 325 { 326 struct bcm_intc_irqsrc *bii; 327 int error; 328 uint32_t irq; 329 const char *name; 330 331 name = device_get_nameunit(sc->sc_dev); 332 for (irq = 0; irq < BCM_INTC_NIRQS; irq++) { 333 bii = &sc->intc_isrcs[irq]; 334 bii->bii_irq = irq; 335 if (IS_IRQ_BASIC(irq)) { 336 bii->bii_disable_reg = INTC_DISABLE_BASIC; 337 bii->bii_enable_reg = INTC_ENABLE_BASIC; 338 bii->bii_mask = 1 << irq; 339 } else if (IS_IRQ_BANK1(irq)) { 340 bii->bii_disable_reg = INTC_DISABLE_BANK1; 341 bii->bii_enable_reg = INTC_ENABLE_BANK1; 342 bii->bii_mask = 1 << IRQ_BANK1(irq); 343 } else if (IS_IRQ_BANK2(irq)) { 344 bii->bii_disable_reg = INTC_DISABLE_BANK2; 345 bii->bii_enable_reg = INTC_ENABLE_BANK2; 346 bii->bii_mask = 1 << IRQ_BANK2(irq); 347 } else 348 return (ENXIO); 349 350 error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0, 351 "%s,%u", name, irq); 352 if (error != 0) 353 return (error); 354 } 355 if (intr_pic_register(sc->sc_dev, xref) == NULL) 356 return (ENXIO); 357 358 return (0); 359 } 360 361 static int 362 bcm_intc_probe(device_t dev) 363 { 364 365 if (!ofw_bus_status_okay(dev)) 366 return (ENXIO); 367 368 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-armctrl-ic") && 369 !ofw_bus_is_compatible(dev, "brcm,bcm2836-armctrl-ic")) 370 return (ENXIO); 371 device_set_desc(dev, "BCM2835 Interrupt Controller"); 372 return (BUS_PROBE_DEFAULT); 373 } 374 375 static int 376 bcm_intc_attach(device_t dev) 377 { 378 struct bcm_intc_softc *sc = device_get_softc(dev); 379 int rid = 0; 380 intptr_t xref; 381 sc->sc_dev = dev; 382 383 if (bcm_intc_sc) 384 return (ENXIO); 385 386 sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 387 if (sc->intc_res == NULL) { 388 device_printf(dev, "could not allocate memory resource\n"); 389 return (ENXIO); 390 } 391 392 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 393 if (bcm_intc_pic_register(sc, xref) != 0) { 394 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res); 395 device_printf(dev, "could not register PIC\n"); 396 return (ENXIO); 397 } 398 399 rid = 0; 400 sc->intc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 401 RF_ACTIVE); 402 if (sc->intc_irq_res == NULL) { 403 if (intr_pic_claim_root(dev, xref, bcm2835_intc_intr, sc, 0) != 0) { 404 /* XXX clean up */ 405 device_printf(dev, "could not set PIC as a root\n"); 406 return (ENXIO); 407 } 408 } else { 409 if (bus_setup_intr(dev, sc->intc_irq_res, INTR_TYPE_CLK, 410 bcm2835_intc_intr, NULL, sc, &sc->intc_irq_hdl)) { 411 /* XXX clean up */ 412 device_printf(dev, "could not setup irq handler\n"); 413 return (ENXIO); 414 } 415 } 416 sc->intc_bst = rman_get_bustag(sc->intc_res); 417 sc->intc_bsh = rman_get_bushandle(sc->intc_res); 418 419 bcm_intc_sc = sc; 420 421 return (0); 422 } 423 424 static device_method_t bcm_intc_methods[] = { 425 DEVMETHOD(device_probe, bcm_intc_probe), 426 DEVMETHOD(device_attach, bcm_intc_attach), 427 428 DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr), 429 DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr), 430 DEVMETHOD(pic_map_intr, bcm_intc_map_intr), 431 DEVMETHOD(pic_post_filter, bcm_intc_post_filter), 432 DEVMETHOD(pic_post_ithread, bcm_intc_post_ithread), 433 DEVMETHOD(pic_pre_ithread, bcm_intc_pre_ithread), 434 435 { 0, 0 } 436 }; 437 438 static driver_t bcm_intc_driver = { 439 "intc", 440 bcm_intc_methods, 441 sizeof(struct bcm_intc_softc), 442 }; 443 444 static devclass_t bcm_intc_devclass; 445 446 EARLY_DRIVER_MODULE(intc, simplebus, bcm_intc_driver, bcm_intc_devclass, 447 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 448