1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 5 * All rights reserved. 6 * 7 * Based on OMAP3 INTC code by Ben Gray 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_platform.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/ktr.h> 42 #include <sys/module.h> 43 #include <sys/proc.h> 44 #include <sys/rman.h> 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include "pic_if.h" 53 54 #define INTC_PENDING_BASIC 0x00 55 #define INTC_PENDING_BANK1 0x04 56 #define INTC_PENDING_BANK2 0x08 57 #define INTC_FIQ_CONTROL 0x0C 58 #define INTC_ENABLE_BANK1 0x10 59 #define INTC_ENABLE_BANK2 0x14 60 #define INTC_ENABLE_BASIC 0x18 61 #define INTC_DISABLE_BANK1 0x1C 62 #define INTC_DISABLE_BANK2 0x20 63 #define INTC_DISABLE_BASIC 0x24 64 65 #define INTC_PENDING_BASIC_ARM 0x0000FF 66 #define INTC_PENDING_BASIC_GPU1_PEND 0x000100 67 #define INTC_PENDING_BASIC_GPU2_PEND 0x000200 68 #define INTC_PENDING_BASIC_GPU1_7 0x000400 69 #define INTC_PENDING_BASIC_GPU1_9 0x000800 70 #define INTC_PENDING_BASIC_GPU1_10 0x001000 71 #define INTC_PENDING_BASIC_GPU1_18 0x002000 72 #define INTC_PENDING_BASIC_GPU1_19 0x004000 73 #define INTC_PENDING_BASIC_GPU2_21 0x008000 74 #define INTC_PENDING_BASIC_GPU2_22 0x010000 75 #define INTC_PENDING_BASIC_GPU2_23 0x020000 76 #define INTC_PENDING_BASIC_GPU2_24 0x040000 77 #define INTC_PENDING_BASIC_GPU2_25 0x080000 78 #define INTC_PENDING_BASIC_GPU2_30 0x100000 79 #define INTC_PENDING_BASIC_MASK 0x1FFFFF 80 81 #define INTC_PENDING_BASIC_GPU1_MASK (INTC_PENDING_BASIC_GPU1_7 | \ 82 INTC_PENDING_BASIC_GPU1_9 | \ 83 INTC_PENDING_BASIC_GPU1_10 | \ 84 INTC_PENDING_BASIC_GPU1_18 | \ 85 INTC_PENDING_BASIC_GPU1_19) 86 87 #define INTC_PENDING_BASIC_GPU2_MASK (INTC_PENDING_BASIC_GPU2_21 | \ 88 INTC_PENDING_BASIC_GPU2_22 | \ 89 INTC_PENDING_BASIC_GPU2_23 | \ 90 INTC_PENDING_BASIC_GPU2_24 | \ 91 INTC_PENDING_BASIC_GPU2_25 | \ 92 INTC_PENDING_BASIC_GPU2_30) 93 94 #define INTC_PENDING_BANK1_MASK (~((1 << 7) | (1 << 9) | (1 << 10) | \ 95 (1 << 18) | (1 << 19))) 96 #define INTC_PENDING_BANK2_MASK (~((1 << 21) | (1 << 22) | (1 << 23) | \ 97 (1 << 24) | (1 << 25) | (1 << 30))) 98 99 #define BANK1_START 8 100 #define BANK1_END (BANK1_START + 32 - 1) 101 #define BANK2_START (BANK1_START + 32) 102 #define BANK2_END (BANK2_START + 32 - 1) 103 104 #define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START)) 105 #define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END)) 106 #define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END)) 107 #define IRQ_BANK1(n) ((n) - BANK1_START) 108 #define IRQ_BANK2(n) ((n) - BANK2_START) 109 110 #ifdef DEBUG 111 #define dprintf(fmt, args...) printf(fmt, ##args) 112 #else 113 #define dprintf(fmt, args...) 114 #endif 115 116 #define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */ 117 118 struct bcm_intc_irqsrc { 119 struct intr_irqsrc bii_isrc; 120 u_int bii_irq; 121 uint16_t bii_disable_reg; 122 uint16_t bii_enable_reg; 123 uint32_t bii_mask; 124 }; 125 126 struct bcm_intc_softc { 127 device_t sc_dev; 128 struct resource * intc_res; 129 bus_space_tag_t intc_bst; 130 bus_space_handle_t intc_bsh; 131 struct resource * intc_irq_res; 132 void * intc_irq_hdl; 133 struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS]; 134 }; 135 136 static struct bcm_intc_softc *bcm_intc_sc = NULL; 137 138 #define intc_read_4(_sc, reg) \ 139 bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg)) 140 #define intc_write_4(_sc, reg, val) \ 141 bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val)) 142 143 static inline void 144 bcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 145 { 146 147 intc_write_4(sc, bii->bii_disable_reg, bii->bii_mask); 148 } 149 150 static inline void 151 bcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 152 { 153 154 intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask); 155 } 156 157 static inline int 158 bcm2835_intc_active_intr(struct bcm_intc_softc *sc) 159 { 160 uint32_t pending, pending_gpu; 161 162 pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK; 163 if (pending == 0) 164 return (-1); 165 if (pending & INTC_PENDING_BASIC_ARM) 166 return (ffs(pending) - 1); 167 if (pending & INTC_PENDING_BASIC_GPU1_MASK) { 168 if (pending & INTC_PENDING_BASIC_GPU1_7) 169 return (BANK1_START + 7); 170 if (pending & INTC_PENDING_BASIC_GPU1_9) 171 return (BANK1_START + 9); 172 if (pending & INTC_PENDING_BASIC_GPU1_10) 173 return (BANK1_START + 10); 174 if (pending & INTC_PENDING_BASIC_GPU1_18) 175 return (BANK1_START + 18); 176 if (pending & INTC_PENDING_BASIC_GPU1_19) 177 return (BANK1_START + 19); 178 } 179 if (pending & INTC_PENDING_BASIC_GPU2_MASK) { 180 if (pending & INTC_PENDING_BASIC_GPU2_21) 181 return (BANK2_START + 21); 182 if (pending & INTC_PENDING_BASIC_GPU2_22) 183 return (BANK2_START + 22); 184 if (pending & INTC_PENDING_BASIC_GPU2_23) 185 return (BANK2_START + 23); 186 if (pending & INTC_PENDING_BASIC_GPU2_24) 187 return (BANK2_START + 24); 188 if (pending & INTC_PENDING_BASIC_GPU2_25) 189 return (BANK2_START + 25); 190 if (pending & INTC_PENDING_BASIC_GPU2_30) 191 return (BANK2_START + 30); 192 } 193 if (pending & INTC_PENDING_BASIC_GPU1_PEND) { 194 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1); 195 pending_gpu &= INTC_PENDING_BANK1_MASK; 196 if (pending_gpu != 0) 197 return (BANK1_START + ffs(pending_gpu) - 1); 198 } 199 if (pending & INTC_PENDING_BASIC_GPU2_PEND) { 200 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2); 201 pending_gpu &= INTC_PENDING_BANK2_MASK; 202 if (pending_gpu != 0) 203 return (BANK2_START + ffs(pending_gpu) - 1); 204 } 205 return (-1); /* It shouldn't end here, but it's hardware. */ 206 } 207 208 static int 209 bcm2835_intc_intr(void *arg) 210 { 211 int irq, num; 212 struct bcm_intc_softc *sc = arg; 213 214 for (num = 0; ; num++) { 215 irq = bcm2835_intc_active_intr(sc); 216 if (irq == -1) 217 break; 218 if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc, 219 curthread->td_intr_frame) != 0) { 220 bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]); 221 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 222 irq); 223 } 224 arm_irq_memory_barrier(0); /* XXX */ 225 } 226 if (num == 0) 227 device_printf(sc->sc_dev, "Spurious interrupt detected\n"); 228 229 return (FILTER_HANDLED); 230 } 231 232 static void 233 bcm_intc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 234 { 235 struct bcm_intc_irqsrc *bii = (struct bcm_intc_irqsrc *)isrc; 236 237 arm_irq_memory_barrier(bii->bii_irq); 238 bcm_intc_isrc_unmask(device_get_softc(dev), bii); 239 } 240 241 static void 242 bcm_intc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 243 { 244 245 bcm_intc_isrc_mask(device_get_softc(dev), 246 (struct bcm_intc_irqsrc *)isrc); 247 } 248 249 static int 250 bcm_intc_map_intr(device_t dev, struct intr_map_data *data, 251 struct intr_irqsrc **isrcp) 252 { 253 u_int irq; 254 struct intr_map_data_fdt *daf; 255 struct bcm_intc_softc *sc; 256 bool valid; 257 258 if (data->type != INTR_MAP_DATA_FDT) 259 return (ENOTSUP); 260 261 daf = (struct intr_map_data_fdt *)data; 262 if (daf->ncells == 1) 263 irq = daf->cells[0]; 264 else if (daf->ncells == 2) { 265 valid = true; 266 switch (daf->cells[0]) { 267 case 0: 268 irq = daf->cells[1]; 269 if (irq >= BANK1_START) 270 valid = false; 271 break; 272 case 1: 273 irq = daf->cells[1] + BANK1_START; 274 if (irq > BANK1_END) 275 valid = false; 276 break; 277 case 2: 278 irq = daf->cells[1] + BANK2_START; 279 if (irq > BANK2_END) 280 valid = false; 281 break; 282 default: 283 valid = false; 284 break; 285 } 286 287 if (!valid) { 288 device_printf(dev, 289 "invalid IRQ config: bank=%d, irq=%d\n", 290 daf->cells[0], daf->cells[1]); 291 return (EINVAL); 292 } 293 } 294 else 295 return (EINVAL); 296 297 if (irq >= BCM_INTC_NIRQS) 298 return (EINVAL); 299 300 sc = device_get_softc(dev); 301 *isrcp = &sc->intc_isrcs[irq].bii_isrc; 302 return (0); 303 } 304 305 static void 306 bcm_intc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 307 { 308 309 bcm_intc_disable_intr(dev, isrc); 310 } 311 312 static void 313 bcm_intc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 314 { 315 316 bcm_intc_enable_intr(dev, isrc); 317 } 318 319 static void 320 bcm_intc_post_filter(device_t dev, struct intr_irqsrc *isrc) 321 { 322 } 323 324 static int 325 bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref) 326 { 327 struct bcm_intc_irqsrc *bii; 328 int error; 329 uint32_t irq; 330 const char *name; 331 332 name = device_get_nameunit(sc->sc_dev); 333 for (irq = 0; irq < BCM_INTC_NIRQS; irq++) { 334 bii = &sc->intc_isrcs[irq]; 335 bii->bii_irq = irq; 336 if (IS_IRQ_BASIC(irq)) { 337 bii->bii_disable_reg = INTC_DISABLE_BASIC; 338 bii->bii_enable_reg = INTC_ENABLE_BASIC; 339 bii->bii_mask = 1 << irq; 340 } else if (IS_IRQ_BANK1(irq)) { 341 bii->bii_disable_reg = INTC_DISABLE_BANK1; 342 bii->bii_enable_reg = INTC_ENABLE_BANK1; 343 bii->bii_mask = 1 << IRQ_BANK1(irq); 344 } else if (IS_IRQ_BANK2(irq)) { 345 bii->bii_disable_reg = INTC_DISABLE_BANK2; 346 bii->bii_enable_reg = INTC_ENABLE_BANK2; 347 bii->bii_mask = 1 << IRQ_BANK2(irq); 348 } else 349 return (ENXIO); 350 351 error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0, 352 "%s,%u", name, irq); 353 if (error != 0) 354 return (error); 355 } 356 if (intr_pic_register(sc->sc_dev, xref) == NULL) 357 return (ENXIO); 358 359 return (0); 360 } 361 362 static int 363 bcm_intc_probe(device_t dev) 364 { 365 366 if (!ofw_bus_status_okay(dev)) 367 return (ENXIO); 368 369 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-armctrl-ic") && 370 !ofw_bus_is_compatible(dev, "brcm,bcm2836-armctrl-ic")) 371 return (ENXIO); 372 device_set_desc(dev, "BCM2835 Interrupt Controller"); 373 return (BUS_PROBE_DEFAULT); 374 } 375 376 static int 377 bcm_intc_attach(device_t dev) 378 { 379 struct bcm_intc_softc *sc = device_get_softc(dev); 380 int rid = 0; 381 intptr_t xref; 382 sc->sc_dev = dev; 383 384 if (bcm_intc_sc) 385 return (ENXIO); 386 387 sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 388 if (sc->intc_res == NULL) { 389 device_printf(dev, "could not allocate memory resource\n"); 390 return (ENXIO); 391 } 392 393 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 394 if (bcm_intc_pic_register(sc, xref) != 0) { 395 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res); 396 device_printf(dev, "could not register PIC\n"); 397 return (ENXIO); 398 } 399 400 rid = 0; 401 sc->intc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 402 RF_ACTIVE); 403 if (sc->intc_irq_res == NULL) { 404 if (intr_pic_claim_root(dev, xref, bcm2835_intc_intr, sc, 0) != 0) { 405 /* XXX clean up */ 406 device_printf(dev, "could not set PIC as a root\n"); 407 return (ENXIO); 408 } 409 } else { 410 if (bus_setup_intr(dev, sc->intc_irq_res, INTR_TYPE_CLK, 411 bcm2835_intc_intr, NULL, sc, &sc->intc_irq_hdl)) { 412 /* XXX clean up */ 413 device_printf(dev, "could not setup irq handler\n"); 414 return (ENXIO); 415 } 416 } 417 sc->intc_bst = rman_get_bustag(sc->intc_res); 418 sc->intc_bsh = rman_get_bushandle(sc->intc_res); 419 420 bcm_intc_sc = sc; 421 422 return (0); 423 } 424 425 static device_method_t bcm_intc_methods[] = { 426 DEVMETHOD(device_probe, bcm_intc_probe), 427 DEVMETHOD(device_attach, bcm_intc_attach), 428 429 DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr), 430 DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr), 431 DEVMETHOD(pic_map_intr, bcm_intc_map_intr), 432 DEVMETHOD(pic_post_filter, bcm_intc_post_filter), 433 DEVMETHOD(pic_post_ithread, bcm_intc_post_ithread), 434 DEVMETHOD(pic_pre_ithread, bcm_intc_pre_ithread), 435 436 { 0, 0 } 437 }; 438 439 static driver_t bcm_intc_driver = { 440 "intc", 441 bcm_intc_methods, 442 sizeof(struct bcm_intc_softc), 443 }; 444 445 static devclass_t bcm_intc_devclass; 446 447 EARLY_DRIVER_MODULE(intc, simplebus, bcm_intc_driver, bcm_intc_devclass, 448 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 449