1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #include <sys/cdefs.h> 31 #include "opt_platform.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/gpio.h> 37 #include <sys/interrupt.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/fdt/fdt_pinctrl.h> 50 #include <dev/gpio/gpiobusvar.h> 51 #include <dev/ofw/ofw_bus.h> 52 53 #include "gpio_if.h" 54 55 #include "pic_if.h" 56 57 #ifdef DEBUG 58 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 59 printf(fmt,##args); } while (0) 60 #else 61 #define dprintf(fmt, args...) 62 #endif 63 64 #define BCM_GPIO_IRQS 4 65 #define BCM_GPIO_PINS_PER_BANK 32 66 #define BCM2835_GPIO_PINS 54 67 #define BCM2711_GPIO_PINS 58 68 #define BCM_GPIO_PINS BCM2711_GPIO_PINS 69 70 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 71 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | \ 72 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 73 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 74 75 #define BCM2835_FSEL_GPIO_IN 0 76 #define BCM2835_FSEL_GPIO_OUT 1 77 #define BCM2835_FSEL_ALT5 2 78 #define BCM2835_FSEL_ALT4 3 79 #define BCM2835_FSEL_ALT0 4 80 #define BCM2835_FSEL_ALT1 5 81 #define BCM2835_FSEL_ALT2 6 82 #define BCM2835_FSEL_ALT3 7 83 84 #define BCM2835_PUD_OFF 0 85 #define BCM2835_PUD_DOWN 1 86 #define BCM2835_PUD_UP 2 87 88 #define BCM2711_PUD_OFF 0 89 #define BCM2711_PUD_DOWN 2 90 #define BCM2711_PUD_UP 1 91 92 static struct resource_spec bcm_gpio_res_spec[] = { 93 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 94 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */ 95 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */ 96 { -1, 0, 0 } 97 }; 98 99 struct bcm_gpio_sysctl { 100 struct bcm_gpio_softc *sc; 101 uint32_t pin; 102 }; 103 104 struct bcm_gpio_irqsrc { 105 struct intr_irqsrc bgi_isrc; 106 uint32_t bgi_irq; 107 uint32_t bgi_mode; 108 uint32_t bgi_mask; 109 }; 110 111 struct bcm_gpio_softc { 112 device_t sc_dev; 113 device_t sc_busdev; 114 struct mtx sc_mtx; 115 struct resource * sc_res[BCM_GPIO_IRQS + 1]; 116 bus_space_tag_t sc_bst; 117 bus_space_handle_t sc_bsh; 118 void * sc_intrhand[BCM_GPIO_IRQS]; 119 bool sc_is2711; 120 u_int sc_maxpins; 121 int sc_gpio_npins; 122 int sc_ro_npins; 123 int sc_ro_pins[BCM_GPIO_PINS]; 124 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS]; 125 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS]; 126 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS]; 127 }; 128 129 enum bcm_gpio_pud { 130 BCM_GPIO_NONE, 131 BCM_GPIO_PULLDOWN, 132 BCM_GPIO_PULLUP, 133 }; 134 135 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 136 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 137 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 138 #define BCM_GPIO_WRITE(_sc, _off, _val) \ 139 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val) 140 #define BCM_GPIO_READ(_sc, _off) \ 141 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off) 142 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \ 143 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits)) 144 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \ 145 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits) 146 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK) 147 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK)) 148 149 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */ 150 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */ 151 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */ 152 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */ 153 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */ 154 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */ 155 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */ 156 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */ 157 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */ 158 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */ 159 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */ 160 #define BCM2835_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */ 161 #define BCM2835_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */ 162 163 #define BCM2711_GPIO_GPPUD(x) (0x0e4 + (x) * sizeof(uint32_t)) /* Pin Pull up/down */ 164 #define BCM2711_GPIO_MASK (0x3) 165 #define BCM2711_GPIO_SHIFT(n) (((n) % 16) * 2) 166 #define BCM2711_GPIO_REGID(n) ((n) / 16) 167 168 static struct ofw_compat_data compat_data[] = { 169 {"broadcom,bcm2835-gpio", 1}, 170 {"brcm,bcm2835-gpio", 1}, 171 {"brcm,bcm2711-gpio", 1}, 172 {NULL, 0} 173 }; 174 175 static struct bcm_gpio_softc *bcm_gpio_sc = NULL; 176 177 static int bcm_gpio_intr_bank0(void *arg); 178 static int bcm_gpio_intr_bank1(void *arg); 179 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc); 180 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc); 181 182 static int 183 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin) 184 { 185 int i; 186 187 for (i = 0; i < sc->sc_ro_npins; i++) 188 if (pin == sc->sc_ro_pins[i]) 189 return (1); 190 return (0); 191 } 192 193 static uint32_t 194 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin) 195 { 196 uint32_t bank, func, offset; 197 198 /* Five banks, 10 pins per bank, 3 bits per pin. */ 199 bank = pin / 10; 200 offset = (pin - bank * 10) * 3; 201 202 BCM_GPIO_LOCK(sc); 203 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7; 204 BCM_GPIO_UNLOCK(sc); 205 206 return (func); 207 } 208 209 static void 210 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize) 211 { 212 213 switch (nfunc) { 214 case BCM2835_FSEL_GPIO_IN: 215 strncpy(buf, "input", bufsize); 216 break; 217 case BCM2835_FSEL_GPIO_OUT: 218 strncpy(buf, "output", bufsize); 219 break; 220 case BCM2835_FSEL_ALT0: 221 strncpy(buf, "alt0", bufsize); 222 break; 223 case BCM2835_FSEL_ALT1: 224 strncpy(buf, "alt1", bufsize); 225 break; 226 case BCM2835_FSEL_ALT2: 227 strncpy(buf, "alt2", bufsize); 228 break; 229 case BCM2835_FSEL_ALT3: 230 strncpy(buf, "alt3", bufsize); 231 break; 232 case BCM2835_FSEL_ALT4: 233 strncpy(buf, "alt4", bufsize); 234 break; 235 case BCM2835_FSEL_ALT5: 236 strncpy(buf, "alt5", bufsize); 237 break; 238 default: 239 strncpy(buf, "invalid", bufsize); 240 } 241 } 242 243 static int 244 bcm_gpio_str_func(char *func, uint32_t *nfunc) 245 { 246 247 if (strcasecmp(func, "input") == 0) 248 *nfunc = BCM2835_FSEL_GPIO_IN; 249 else if (strcasecmp(func, "output") == 0) 250 *nfunc = BCM2835_FSEL_GPIO_OUT; 251 else if (strcasecmp(func, "alt0") == 0) 252 *nfunc = BCM2835_FSEL_ALT0; 253 else if (strcasecmp(func, "alt1") == 0) 254 *nfunc = BCM2835_FSEL_ALT1; 255 else if (strcasecmp(func, "alt2") == 0) 256 *nfunc = BCM2835_FSEL_ALT2; 257 else if (strcasecmp(func, "alt3") == 0) 258 *nfunc = BCM2835_FSEL_ALT3; 259 else if (strcasecmp(func, "alt4") == 0) 260 *nfunc = BCM2835_FSEL_ALT4; 261 else if (strcasecmp(func, "alt5") == 0) 262 *nfunc = BCM2835_FSEL_ALT5; 263 else 264 return (-1); 265 266 return (0); 267 } 268 269 static uint32_t 270 bcm_gpio_func_flag(uint32_t nfunc) 271 { 272 273 switch (nfunc) { 274 case BCM2835_FSEL_GPIO_IN: 275 return (GPIO_PIN_INPUT); 276 case BCM2835_FSEL_GPIO_OUT: 277 return (GPIO_PIN_OUTPUT); 278 } 279 return (0); 280 } 281 282 static void 283 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f) 284 { 285 uint32_t bank, data, offset; 286 287 /* Must be called with lock held. */ 288 BCM_GPIO_LOCK_ASSERT(sc); 289 290 /* Five banks, 10 pins per bank, 3 bits per pin. */ 291 bank = pin / 10; 292 offset = (pin - bank * 10) * 3; 293 294 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)); 295 data &= ~(7 << offset); 296 data |= (f << offset); 297 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data); 298 } 299 300 static void 301 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state) 302 { 303 /* Must be called with lock held. */ 304 BCM_GPIO_LOCK_ASSERT(sc); 305 306 if (sc->sc_is2711) { /* BCM2711 */ 307 u_int regid = BCM2711_GPIO_REGID(pin); 308 u_int shift = BCM2711_GPIO_SHIFT(pin); 309 uint32_t reg; 310 311 switch (state) { 312 case BCM2835_PUD_OFF: 313 state = BCM2711_PUD_OFF; 314 break; 315 case BCM2835_PUD_DOWN: 316 state = BCM2711_PUD_DOWN; 317 break; 318 case BCM2835_PUD_UP: 319 state = BCM2711_PUD_UP; 320 break; 321 } 322 323 reg = BCM_GPIO_READ(sc, BCM2711_GPIO_GPPUD(regid)); 324 reg &= ~(BCM2711_GPIO_MASK << shift); 325 reg |= (state << shift); 326 BCM_GPIO_WRITE(sc, BCM2711_GPIO_GPPUD(regid), reg); 327 } else { /* BCM2835 */ 328 uint32_t bank; 329 330 bank = BCM_GPIO_BANK(pin); 331 BCM_GPIO_WRITE(sc, BCM2835_GPIO_GPPUD(0), state); 332 BCM_GPIO_WRITE(sc, BCM2835_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin)); 333 BCM_GPIO_WRITE(sc, BCM2835_GPIO_GPPUD(0), 0); 334 BCM_GPIO_WRITE(sc, BCM2835_GPIO_GPPUDCLK(bank), 0); 335 } 336 } 337 338 static void 339 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc) 340 { 341 struct bcm_gpio_softc *sc; 342 int i; 343 344 sc = device_get_softc(dev); 345 BCM_GPIO_LOCK(sc); 346 347 /* Set the pin function. */ 348 bcm_gpio_set_function(sc, pin, nfunc); 349 350 /* Update the pin flags. */ 351 for (i = 0; i < sc->sc_gpio_npins; i++) { 352 if (sc->sc_gpio_pins[i].gp_pin == pin) 353 break; 354 } 355 if (i < sc->sc_gpio_npins) 356 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc); 357 358 BCM_GPIO_UNLOCK(sc); 359 } 360 361 static void 362 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin, 363 unsigned int flags) 364 { 365 366 BCM_GPIO_LOCK(sc); 367 368 /* 369 * Manage input/output. 370 */ 371 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 372 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); 373 if (flags & GPIO_PIN_OUTPUT) { 374 pin->gp_flags |= GPIO_PIN_OUTPUT; 375 bcm_gpio_set_function(sc, pin->gp_pin, 376 BCM2835_FSEL_GPIO_OUT); 377 } else { 378 pin->gp_flags |= GPIO_PIN_INPUT; 379 bcm_gpio_set_function(sc, pin->gp_pin, 380 BCM2835_FSEL_GPIO_IN); 381 } 382 } 383 384 /* Manage Pull-up/pull-down. */ 385 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN); 386 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 387 if (flags & GPIO_PIN_PULLUP) { 388 pin->gp_flags |= GPIO_PIN_PULLUP; 389 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP); 390 } else { 391 pin->gp_flags |= GPIO_PIN_PULLDOWN; 392 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN); 393 } 394 } else 395 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE); 396 397 BCM_GPIO_UNLOCK(sc); 398 } 399 400 static device_t 401 bcm_gpio_get_bus(device_t dev) 402 { 403 struct bcm_gpio_softc *sc; 404 405 sc = device_get_softc(dev); 406 407 return (sc->sc_busdev); 408 } 409 410 static int 411 bcm_gpio_pin_max(device_t dev, int *maxpin) 412 { 413 struct bcm_gpio_softc *sc; 414 415 sc = device_get_softc(dev); 416 *maxpin = sc->sc_maxpins - 1; 417 return (0); 418 } 419 420 static int 421 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 422 { 423 struct bcm_gpio_softc *sc = device_get_softc(dev); 424 int i; 425 426 for (i = 0; i < sc->sc_gpio_npins; i++) { 427 if (sc->sc_gpio_pins[i].gp_pin == pin) 428 break; 429 } 430 431 if (i >= sc->sc_gpio_npins) 432 return (EINVAL); 433 434 BCM_GPIO_LOCK(sc); 435 *caps = sc->sc_gpio_pins[i].gp_caps; 436 BCM_GPIO_UNLOCK(sc); 437 438 return (0); 439 } 440 441 static int 442 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 443 { 444 struct bcm_gpio_softc *sc = device_get_softc(dev); 445 int i; 446 447 for (i = 0; i < sc->sc_gpio_npins; i++) { 448 if (sc->sc_gpio_pins[i].gp_pin == pin) 449 break; 450 } 451 452 if (i >= sc->sc_gpio_npins) 453 return (EINVAL); 454 455 BCM_GPIO_LOCK(sc); 456 *flags = sc->sc_gpio_pins[i].gp_flags; 457 BCM_GPIO_UNLOCK(sc); 458 459 return (0); 460 } 461 462 static int 463 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 464 { 465 struct bcm_gpio_softc *sc = device_get_softc(dev); 466 int i; 467 468 for (i = 0; i < sc->sc_gpio_npins; i++) { 469 if (sc->sc_gpio_pins[i].gp_pin == pin) 470 break; 471 } 472 473 if (i >= sc->sc_gpio_npins) 474 return (EINVAL); 475 476 BCM_GPIO_LOCK(sc); 477 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME); 478 BCM_GPIO_UNLOCK(sc); 479 480 return (0); 481 } 482 483 static int 484 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 485 { 486 struct bcm_gpio_softc *sc = device_get_softc(dev); 487 int i; 488 489 for (i = 0; i < sc->sc_gpio_npins; i++) { 490 if (sc->sc_gpio_pins[i].gp_pin == pin) 491 break; 492 } 493 494 if (i >= sc->sc_gpio_npins) 495 return (EINVAL); 496 497 /* We never touch on read-only/reserved pins. */ 498 if (bcm_gpio_pin_is_ro(sc, pin)) 499 return (EINVAL); 500 501 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags); 502 503 return (0); 504 } 505 506 static int 507 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 508 { 509 struct bcm_gpio_softc *sc = device_get_softc(dev); 510 uint32_t bank, reg; 511 int i; 512 513 for (i = 0; i < sc->sc_gpio_npins; i++) { 514 if (sc->sc_gpio_pins[i].gp_pin == pin) 515 break; 516 } 517 if (i >= sc->sc_gpio_npins) 518 return (EINVAL); 519 /* We never write to read-only/reserved pins. */ 520 if (bcm_gpio_pin_is_ro(sc, pin)) 521 return (EINVAL); 522 BCM_GPIO_LOCK(sc); 523 bank = BCM_GPIO_BANK(pin); 524 if (value) 525 reg = BCM_GPIO_GPSET(bank); 526 else 527 reg = BCM_GPIO_GPCLR(bank); 528 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 529 BCM_GPIO_UNLOCK(sc); 530 531 return (0); 532 } 533 534 static int 535 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 536 { 537 struct bcm_gpio_softc *sc = device_get_softc(dev); 538 uint32_t bank, reg_data; 539 int i; 540 541 for (i = 0; i < sc->sc_gpio_npins; i++) { 542 if (sc->sc_gpio_pins[i].gp_pin == pin) 543 break; 544 } 545 if (i >= sc->sc_gpio_npins) 546 return (EINVAL); 547 bank = BCM_GPIO_BANK(pin); 548 BCM_GPIO_LOCK(sc); 549 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 550 BCM_GPIO_UNLOCK(sc); 551 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0; 552 553 return (0); 554 } 555 556 static int 557 bcm_gpio_pin_toggle(device_t dev, uint32_t pin) 558 { 559 struct bcm_gpio_softc *sc = device_get_softc(dev); 560 uint32_t bank, data, reg; 561 int i; 562 563 for (i = 0; i < sc->sc_gpio_npins; i++) { 564 if (sc->sc_gpio_pins[i].gp_pin == pin) 565 break; 566 } 567 if (i >= sc->sc_gpio_npins) 568 return (EINVAL); 569 /* We never write to read-only/reserved pins. */ 570 if (bcm_gpio_pin_is_ro(sc, pin)) 571 return (EINVAL); 572 BCM_GPIO_LOCK(sc); 573 bank = BCM_GPIO_BANK(pin); 574 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 575 if (data & BCM_GPIO_MASK(pin)) 576 reg = BCM_GPIO_GPCLR(bank); 577 else 578 reg = BCM_GPIO_GPSET(bank); 579 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 580 BCM_GPIO_UNLOCK(sc); 581 582 return (0); 583 } 584 585 static int 586 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS) 587 { 588 char buf[16]; 589 struct bcm_gpio_softc *sc; 590 struct bcm_gpio_sysctl *sc_sysctl; 591 uint32_t nfunc; 592 int error; 593 594 sc_sysctl = arg1; 595 sc = sc_sysctl->sc; 596 597 /* Get the current pin function. */ 598 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin); 599 bcm_gpio_func_str(nfunc, buf, sizeof(buf)); 600 601 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 602 if (error != 0 || req->newptr == NULL) 603 return (error); 604 /* Ignore changes on read-only pins. */ 605 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin)) 606 return (0); 607 /* Parse the user supplied string and check for a valid pin function. */ 608 if (bcm_gpio_str_func(buf, &nfunc) != 0) 609 return (EINVAL); 610 611 /* Update the pin alternate function. */ 612 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc); 613 614 return (0); 615 } 616 617 static void 618 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc) 619 { 620 char pinbuf[3]; 621 struct bcm_gpio_sysctl *sc_sysctl; 622 struct sysctl_ctx_list *ctx; 623 struct sysctl_oid *tree_node, *pin_node, *pinN_node; 624 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree; 625 int i; 626 627 /* 628 * Add per-pin sysctl tree/handlers. 629 */ 630 ctx = device_get_sysctl_ctx(sc->sc_dev); 631 tree_node = device_get_sysctl_tree(sc->sc_dev); 632 tree = SYSCTL_CHILDREN(tree_node); 633 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin", 634 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GPIO Pins"); 635 pin_tree = SYSCTL_CHILDREN(pin_node); 636 637 for (i = 0; i < sc->sc_gpio_npins; i++) { 638 snprintf(pinbuf, sizeof(pinbuf), "%d", i); 639 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf, 640 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GPIO Pin"); 641 pinN_tree = SYSCTL_CHILDREN(pinN_node); 642 643 sc->sc_sysctl[i].sc = sc; 644 sc_sysctl = &sc->sc_sysctl[i]; 645 sc_sysctl->sc = sc; 646 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin; 647 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function", 648 CTLFLAG_RW | CTLTYPE_STRING | CTLFLAG_NEEDGIANT, sc_sysctl, 649 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc, 650 "A", "Pin Function"); 651 } 652 } 653 654 static int 655 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node, 656 const char *propname, const char *label) 657 { 658 int i, need_comma, npins, range_start, range_stop; 659 pcell_t *pins; 660 661 /* Get the property data. */ 662 npins = OF_getencprop_alloc_multi(node, propname, sizeof(*pins), 663 (void **)&pins); 664 if (npins < 0) 665 return (-1); 666 if (npins == 0) { 667 OF_prop_free(pins); 668 return (0); 669 } 670 for (i = 0; i < npins; i++) 671 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i]; 672 sc->sc_ro_npins += npins; 673 need_comma = 0; 674 device_printf(sc->sc_dev, "%s pins: ", label); 675 range_start = range_stop = pins[0]; 676 for (i = 1; i < npins; i++) { 677 if (pins[i] != range_stop + 1) { 678 if (need_comma) 679 printf(","); 680 if (range_start != range_stop) 681 printf("%d-%d", range_start, range_stop); 682 else 683 printf("%d", range_start); 684 range_start = range_stop = pins[i]; 685 need_comma = 1; 686 } else 687 range_stop++; 688 } 689 if (need_comma) 690 printf(","); 691 if (range_start != range_stop) 692 printf("%d-%d.\n", range_start, range_stop); 693 else 694 printf("%d.\n", range_start); 695 OF_prop_free(pins); 696 697 return (0); 698 } 699 700 static int 701 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc) 702 { 703 char *name; 704 phandle_t gpio, node, reserved; 705 ssize_t len; 706 707 /* Get read-only pins if they're provided */ 708 gpio = ofw_bus_get_node(sc->sc_dev); 709 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only", 710 "read-only") != 0) 711 return (0); 712 /* Traverse the GPIO subnodes to find the reserved pins node. */ 713 reserved = 0; 714 node = OF_child(gpio); 715 while ((node != 0) && (reserved == 0)) { 716 len = OF_getprop_alloc(node, "name", (void **)&name); 717 if (len == -1) 718 return (-1); 719 if (strcmp(name, "reserved") == 0) 720 reserved = node; 721 OF_prop_free(name); 722 node = OF_peer(node); 723 } 724 if (reserved == 0) 725 return (-1); 726 /* Get the reserved pins. */ 727 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins", 728 "reserved") != 0) 729 return (-1); 730 731 return (0); 732 } 733 734 static int 735 bcm_gpio_probe(device_t dev) 736 { 737 738 if (!ofw_bus_status_okay(dev)) 739 return (ENXIO); 740 741 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 742 return (ENXIO); 743 744 device_set_desc(dev, "BCM2708/2835 GPIO controller"); 745 return (BUS_PROBE_DEFAULT); 746 } 747 748 static int 749 bcm_gpio_intr_attach(device_t dev) 750 { 751 struct bcm_gpio_softc *sc; 752 753 /* 754 * Only first two interrupt lines are used. Third line is 755 * mirrored second line and forth line is common for all banks. 756 */ 757 sc = device_get_softc(dev); 758 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL) 759 return (-1); 760 761 if (bcm_gpio_pic_attach(sc) != 0) { 762 device_printf(dev, "unable to attach PIC\n"); 763 return (-1); 764 } 765 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE, 766 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0) 767 return (-1); 768 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE, 769 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0) 770 return (-1); 771 772 return (0); 773 } 774 775 static void 776 bcm_gpio_intr_detach(device_t dev) 777 { 778 struct bcm_gpio_softc *sc; 779 780 sc = device_get_softc(dev); 781 if (sc->sc_intrhand[0] != NULL) 782 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]); 783 if (sc->sc_intrhand[1] != NULL) 784 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]); 785 786 bcm_gpio_pic_detach(sc); 787 } 788 789 static int 790 bcm_gpio_attach(device_t dev) 791 { 792 int i, j; 793 phandle_t gpio; 794 struct bcm_gpio_softc *sc; 795 uint32_t func; 796 797 if (bcm_gpio_sc != NULL) 798 return (ENXIO); 799 800 bcm_gpio_sc = sc = device_get_softc(dev); 801 sc->sc_dev = dev; 802 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN); 803 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) { 804 device_printf(dev, "cannot allocate resources\n"); 805 goto fail; 806 } 807 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 808 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 809 /* Find our node. */ 810 gpio = ofw_bus_get_node(sc->sc_dev); 811 if (!OF_hasprop(gpio, "gpio-controller")) 812 /* Node is not a GPIO controller. */ 813 goto fail; 814 /* Guess I'm BCM2711 or not. */ 815 sc->sc_is2711 = ofw_bus_node_is_compatible(gpio, "brcm,bcm2711-gpio"); 816 sc->sc_maxpins = sc->sc_is2711 ? BCM2711_GPIO_PINS : BCM2835_GPIO_PINS; 817 /* Setup the GPIO interrupt handler. */ 818 if (bcm_gpio_intr_attach(dev)) { 819 device_printf(dev, "unable to setup the gpio irq handler\n"); 820 goto fail; 821 } 822 /* 823 * Find the read-only pins. These are pins we never touch or bad 824 * things could happen. 825 */ 826 if (bcm_gpio_get_reserved_pins(sc) == -1) 827 goto fail; 828 /* Initialize the software controlled pins. */ 829 for (i = 0, j = 0; j < sc->sc_maxpins; j++) { 830 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, 831 "pin %d", j); 832 func = bcm_gpio_get_function(sc, j); 833 sc->sc_gpio_pins[i].gp_pin = j; 834 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS; 835 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func); 836 i++; 837 } 838 sc->sc_gpio_npins = i; 839 bcm_gpio_sysctl_init(sc); 840 sc->sc_busdev = gpiobus_attach_bus(dev); 841 if (sc->sc_busdev == NULL) 842 goto fail; 843 844 fdt_pinctrl_register(dev, "brcm,pins"); 845 fdt_pinctrl_configure_tree(dev); 846 847 return (0); 848 849 fail: 850 bcm_gpio_intr_detach(dev); 851 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res); 852 mtx_destroy(&sc->sc_mtx); 853 854 return (ENXIO); 855 } 856 857 static int 858 bcm_gpio_detach(device_t dev) 859 { 860 861 return (EBUSY); 862 } 863 864 static inline void 865 bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask, 866 bool set_bits) 867 { 868 869 if (set_bits) 870 BCM_GPIO_SET_BITS(sc, reg, mask); 871 else 872 BCM_GPIO_CLEAR_BITS(sc, reg, mask); 873 } 874 875 static inline void 876 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 877 { 878 uint32_t bank; 879 880 /* Write 1 to clear. */ 881 bank = BCM_GPIO_BANK(bgi->bgi_irq); 882 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask); 883 } 884 885 static inline bool 886 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi) 887 { 888 889 return (bgi->bgi_mode == GPIO_INTR_LEVEL_LOW || 890 bgi->bgi_mode == GPIO_INTR_LEVEL_HIGH); 891 } 892 893 static inline void 894 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 895 { 896 uint32_t bank; 897 898 bank = BCM_GPIO_BANK(bgi->bgi_irq); 899 BCM_GPIO_LOCK(sc); 900 switch (bgi->bgi_mode) { 901 case GPIO_INTR_LEVEL_LOW: 902 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 903 break; 904 case GPIO_INTR_LEVEL_HIGH: 905 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 906 break; 907 case GPIO_INTR_EDGE_RISING: 908 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 909 break; 910 case GPIO_INTR_EDGE_FALLING: 911 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 912 break; 913 case GPIO_INTR_EDGE_BOTH: 914 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 915 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 916 break; 917 } 918 BCM_GPIO_UNLOCK(sc); 919 } 920 921 static inline void 922 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 923 { 924 uint32_t bank; 925 926 bank = BCM_GPIO_BANK(bgi->bgi_irq); 927 BCM_GPIO_LOCK(sc); 928 switch (bgi->bgi_mode) { 929 case GPIO_INTR_LEVEL_LOW: 930 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 931 break; 932 case GPIO_INTR_LEVEL_HIGH: 933 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 934 break; 935 case GPIO_INTR_EDGE_RISING: 936 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 937 break; 938 case GPIO_INTR_EDGE_FALLING: 939 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 940 break; 941 case GPIO_INTR_EDGE_BOTH: 942 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 943 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 944 break; 945 } 946 BCM_GPIO_UNLOCK(sc); 947 } 948 949 static int 950 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank) 951 { 952 u_int irq; 953 struct bcm_gpio_irqsrc *bgi; 954 uint32_t reg; 955 956 /* Do not care of spurious interrupt on GPIO. */ 957 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); 958 while (reg != 0) { 959 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1; 960 bgi = sc->sc_isrcs + irq; 961 if (!bcm_gpio_isrc_is_level(bgi)) 962 bcm_gpio_isrc_eoi(sc, bgi); 963 if (intr_isrc_dispatch(&bgi->bgi_isrc, 964 curthread->td_intr_frame) != 0) { 965 bcm_gpio_isrc_mask(sc, bgi); 966 if (bcm_gpio_isrc_is_level(bgi)) 967 bcm_gpio_isrc_eoi(sc, bgi); 968 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 969 irq); 970 } 971 reg &= ~bgi->bgi_mask; 972 } 973 return (FILTER_HANDLED); 974 } 975 976 static int 977 bcm_gpio_intr_bank0(void *arg) 978 { 979 980 return (bcm_gpio_intr_internal(arg, 0)); 981 } 982 983 static int 984 bcm_gpio_intr_bank1(void *arg) 985 { 986 987 return (bcm_gpio_intr_internal(arg, 1)); 988 } 989 990 static int 991 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc) 992 { 993 int error; 994 uint32_t irq; 995 const char *name; 996 997 name = device_get_nameunit(sc->sc_dev); 998 for (irq = 0; irq < sc->sc_maxpins; irq++) { 999 sc->sc_isrcs[irq].bgi_irq = irq; 1000 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq); 1001 sc->sc_isrcs[irq].bgi_mode = GPIO_INTR_CONFORM; 1002 1003 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc, 1004 sc->sc_dev, 0, "%s,%u", name, irq); 1005 if (error != 0) 1006 return (error); /* XXX deregister ISRCs */ 1007 } 1008 if (intr_pic_register(sc->sc_dev, 1009 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 1010 return (ENXIO); 1011 1012 return (0); 1013 } 1014 1015 static int 1016 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc) 1017 { 1018 1019 /* 1020 * There has not been established any procedure yet 1021 * how to detach PIC from living system correctly. 1022 */ 1023 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 1024 return (EBUSY); 1025 } 1026 1027 static void 1028 bcm_gpio_pic_config_intr(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi, 1029 uint32_t mode) 1030 { 1031 uint32_t bank; 1032 1033 bank = BCM_GPIO_BANK(bgi->bgi_irq); 1034 BCM_GPIO_LOCK(sc); 1035 bcm_gpio_modify(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask, 1036 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 1037 bcm_gpio_modify(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask, 1038 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 1039 bcm_gpio_modify(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask, 1040 mode == GPIO_INTR_LEVEL_HIGH); 1041 bcm_gpio_modify(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask, 1042 mode == GPIO_INTR_LEVEL_LOW); 1043 bgi->bgi_mode = mode; 1044 BCM_GPIO_UNLOCK(sc); 1045 } 1046 1047 static void 1048 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 1049 { 1050 struct bcm_gpio_softc *sc = device_get_softc(dev); 1051 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1052 1053 bcm_gpio_isrc_mask(sc, bgi); 1054 } 1055 1056 static void 1057 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 1058 { 1059 struct bcm_gpio_softc *sc = device_get_softc(dev); 1060 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1061 1062 arm_irq_memory_barrier(bgi->bgi_irq); 1063 bcm_gpio_isrc_unmask(sc, bgi); 1064 } 1065 1066 static int 1067 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf, 1068 u_int *irqp, uint32_t *modep) 1069 { 1070 u_int irq; 1071 uint32_t mode; 1072 1073 /* 1074 * The first cell is the interrupt number. 1075 * The second cell is used to specify flags: 1076 * bits[3:0] trigger type and level flags: 1077 * 1 = low-to-high edge triggered. 1078 * 2 = high-to-low edge triggered. 1079 * 4 = active high level-sensitive. 1080 * 8 = active low level-sensitive. 1081 */ 1082 if (daf->ncells != 2) 1083 return (EINVAL); 1084 1085 irq = daf->cells[0]; 1086 if (irq >= sc->sc_maxpins || bcm_gpio_pin_is_ro(sc, irq)) 1087 return (EINVAL); 1088 1089 /* Only reasonable modes are supported. */ 1090 if (daf->cells[1] == 1) 1091 mode = GPIO_INTR_EDGE_RISING; 1092 else if (daf->cells[1] == 2) 1093 mode = GPIO_INTR_EDGE_FALLING; 1094 else if (daf->cells[1] == 3) 1095 mode = GPIO_INTR_EDGE_BOTH; 1096 else if (daf->cells[1] == 4) 1097 mode = GPIO_INTR_LEVEL_HIGH; 1098 else if (daf->cells[1] == 8) 1099 mode = GPIO_INTR_LEVEL_LOW; 1100 else 1101 return (EINVAL); 1102 1103 *irqp = irq; 1104 if (modep != NULL) 1105 *modep = mode; 1106 return (0); 1107 } 1108 1109 static int 1110 bcm_gpio_pic_map_gpio(struct bcm_gpio_softc *sc, struct intr_map_data_gpio *dag, 1111 u_int *irqp, uint32_t *modep) 1112 { 1113 u_int irq; 1114 uint32_t mode; 1115 1116 irq = dag->gpio_pin_num; 1117 if (irq >= sc->sc_maxpins || bcm_gpio_pin_is_ro(sc, irq)) 1118 return (EINVAL); 1119 1120 mode = dag->gpio_intr_mode; 1121 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 1122 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 1123 mode != GPIO_INTR_EDGE_BOTH) 1124 return (EINVAL); 1125 1126 *irqp = irq; 1127 if (modep != NULL) 1128 *modep = mode; 1129 return (0); 1130 } 1131 1132 static int 1133 bcm_gpio_pic_map(struct bcm_gpio_softc *sc, struct intr_map_data *data, 1134 u_int *irqp, uint32_t *modep) 1135 { 1136 1137 switch (data->type) { 1138 case INTR_MAP_DATA_FDT: 1139 return (bcm_gpio_pic_map_fdt(sc, 1140 (struct intr_map_data_fdt *)data, irqp, modep)); 1141 case INTR_MAP_DATA_GPIO: 1142 return (bcm_gpio_pic_map_gpio(sc, 1143 (struct intr_map_data_gpio *)data, irqp, modep)); 1144 default: 1145 return (ENOTSUP); 1146 } 1147 } 1148 1149 static int 1150 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1151 struct intr_irqsrc **isrcp) 1152 { 1153 int error; 1154 u_int irq; 1155 struct bcm_gpio_softc *sc = device_get_softc(dev); 1156 1157 error = bcm_gpio_pic_map(sc, data, &irq, NULL); 1158 if (error == 0) 1159 *isrcp = &sc->sc_isrcs[irq].bgi_isrc; 1160 return (error); 1161 } 1162 1163 static void 1164 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1165 { 1166 struct bcm_gpio_softc *sc = device_get_softc(dev); 1167 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1168 1169 if (bcm_gpio_isrc_is_level(bgi)) 1170 bcm_gpio_isrc_eoi(sc, bgi); 1171 } 1172 1173 static void 1174 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1175 { 1176 1177 bcm_gpio_pic_enable_intr(dev, isrc); 1178 } 1179 1180 static void 1181 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1182 { 1183 struct bcm_gpio_softc *sc = device_get_softc(dev); 1184 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1185 1186 bcm_gpio_isrc_mask(sc, bgi); 1187 if (bcm_gpio_isrc_is_level(bgi)) 1188 bcm_gpio_isrc_eoi(sc, bgi); 1189 } 1190 1191 static int 1192 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1193 struct resource *res, struct intr_map_data *data) 1194 { 1195 u_int irq; 1196 uint32_t mode; 1197 struct bcm_gpio_softc *sc; 1198 struct bcm_gpio_irqsrc *bgi; 1199 1200 if (data == NULL) 1201 return (ENOTSUP); 1202 1203 sc = device_get_softc(dev); 1204 bgi = (struct bcm_gpio_irqsrc *)isrc; 1205 1206 /* Get and check config for an interrupt. */ 1207 if (bcm_gpio_pic_map(sc, data, &irq, &mode) != 0 || bgi->bgi_irq != irq) 1208 return (EINVAL); 1209 1210 /* 1211 * If this is a setup for another handler, 1212 * only check that its configuration match. 1213 */ 1214 if (isrc->isrc_handlers != 0) 1215 return (bgi->bgi_mode == mode ? 0 : EINVAL); 1216 1217 bcm_gpio_pic_config_intr(sc, bgi, mode); 1218 return (0); 1219 } 1220 1221 static int 1222 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1223 struct resource *res, struct intr_map_data *data) 1224 { 1225 struct bcm_gpio_softc *sc = device_get_softc(dev); 1226 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1227 1228 if (isrc->isrc_handlers == 0) 1229 bcm_gpio_pic_config_intr(sc, bgi, GPIO_INTR_CONFORM); 1230 return (0); 1231 } 1232 1233 static phandle_t 1234 bcm_gpio_get_node(device_t bus, device_t dev) 1235 { 1236 1237 /* We only have one child, the GPIO bus, which needs our own node. */ 1238 return (ofw_bus_get_node(bus)); 1239 } 1240 1241 static int 1242 bcm_gpio_configure_pins(device_t dev, phandle_t cfgxref) 1243 { 1244 phandle_t cfgnode; 1245 int i, pintuples, pulltuples; 1246 uint32_t pin; 1247 uint32_t *pins; 1248 uint32_t *pulls; 1249 uint32_t function; 1250 1251 cfgnode = OF_node_from_xref(cfgxref); 1252 1253 pins = NULL; 1254 pintuples = OF_getencprop_alloc_multi(cfgnode, "brcm,pins", 1255 sizeof(*pins), (void **)&pins); 1256 1257 char name[32]; 1258 OF_getprop(cfgnode, "name", &name, sizeof(name)); 1259 1260 if (pintuples < 0) 1261 return (ENOENT); 1262 1263 if (pintuples == 0) 1264 return (0); /* Empty property is not an error. */ 1265 1266 if (OF_getencprop(cfgnode, "brcm,function", &function, 1267 sizeof(function)) <= 0) { 1268 OF_prop_free(pins); 1269 return (EINVAL); 1270 } 1271 1272 pulls = NULL; 1273 pulltuples = OF_getencprop_alloc_multi(cfgnode, "brcm,pull", 1274 sizeof(*pulls), (void **)&pulls); 1275 1276 if ((pulls != NULL) && (pulltuples != pintuples)) { 1277 OF_prop_free(pins); 1278 OF_prop_free(pulls); 1279 return (EINVAL); 1280 } 1281 1282 for (i = 0; i < pintuples; i++) { 1283 pin = pins[i]; 1284 bcm_gpio_set_alternate(dev, pin, function); 1285 if (bootverbose) 1286 device_printf(dev, "set pin %d to func %d", pin, function); 1287 if (pulls) { 1288 if (bootverbose) 1289 printf(", pull %d", pulls[i]); 1290 switch (pulls[i]) { 1291 /* Convert to gpio(4) flags */ 1292 case BCM2835_PUD_OFF: 1293 bcm_gpio_pin_setflags(dev, pin, 0); 1294 break; 1295 case BCM2835_PUD_UP: 1296 bcm_gpio_pin_setflags(dev, pin, GPIO_PIN_PULLUP); 1297 break; 1298 case BCM2835_PUD_DOWN: 1299 bcm_gpio_pin_setflags(dev, pin, GPIO_PIN_PULLDOWN); 1300 break; 1301 default: 1302 printf("%s: invalid pull value for pin %d: %d\n", 1303 name, pin, pulls[i]); 1304 } 1305 } 1306 if (bootverbose) 1307 printf("\n"); 1308 } 1309 1310 OF_prop_free(pins); 1311 if (pulls) 1312 OF_prop_free(pulls); 1313 1314 return (0); 1315 } 1316 1317 static device_method_t bcm_gpio_methods[] = { 1318 /* Device interface */ 1319 DEVMETHOD(device_probe, bcm_gpio_probe), 1320 DEVMETHOD(device_attach, bcm_gpio_attach), 1321 DEVMETHOD(device_detach, bcm_gpio_detach), 1322 1323 /* GPIO protocol */ 1324 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus), 1325 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max), 1326 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname), 1327 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags), 1328 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps), 1329 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags), 1330 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get), 1331 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set), 1332 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle), 1333 1334 /* Interrupt controller interface */ 1335 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr), 1336 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr), 1337 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr), 1338 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter), 1339 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread), 1340 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread), 1341 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr), 1342 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr), 1343 1344 /* ofw_bus interface */ 1345 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node), 1346 1347 /* fdt_pinctrl interface */ 1348 DEVMETHOD(fdt_pinctrl_configure, bcm_gpio_configure_pins), 1349 1350 DEVMETHOD_END 1351 }; 1352 1353 static driver_t bcm_gpio_driver = { 1354 "gpio", 1355 bcm_gpio_methods, 1356 sizeof(struct bcm_gpio_softc), 1357 }; 1358 1359 EARLY_DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, 0, 0, 1360 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 1361