1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_platform.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/gpio.h> 39 #include <sys/interrupt.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/proc.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/gpio/gpiobusvar.h> 52 #include <dev/ofw/ofw_bus.h> 53 54 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 55 56 #include "gpio_if.h" 57 58 #include "pic_if.h" 59 60 #ifdef DEBUG 61 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 62 printf(fmt,##args); } while (0) 63 #else 64 #define dprintf(fmt, args...) 65 #endif 66 67 #define BCM_GPIO_IRQS 4 68 #define BCM_GPIO_PINS 54 69 #define BCM_GPIO_PINS_PER_BANK 32 70 71 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 72 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | \ 73 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 74 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 75 76 static struct resource_spec bcm_gpio_res_spec[] = { 77 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 78 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */ 79 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */ 80 { -1, 0, 0 } 81 }; 82 83 struct bcm_gpio_sysctl { 84 struct bcm_gpio_softc *sc; 85 uint32_t pin; 86 }; 87 88 struct bcm_gpio_irqsrc { 89 struct intr_irqsrc bgi_isrc; 90 uint32_t bgi_irq; 91 uint32_t bgi_mode; 92 uint32_t bgi_mask; 93 }; 94 95 struct bcm_gpio_softc { 96 device_t sc_dev; 97 device_t sc_busdev; 98 struct mtx sc_mtx; 99 struct resource * sc_res[BCM_GPIO_IRQS + 1]; 100 bus_space_tag_t sc_bst; 101 bus_space_handle_t sc_bsh; 102 void * sc_intrhand[BCM_GPIO_IRQS]; 103 int sc_gpio_npins; 104 int sc_ro_npins; 105 int sc_ro_pins[BCM_GPIO_PINS]; 106 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS]; 107 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS]; 108 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS]; 109 }; 110 111 enum bcm_gpio_pud { 112 BCM_GPIO_NONE, 113 BCM_GPIO_PULLDOWN, 114 BCM_GPIO_PULLUP, 115 }; 116 117 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 118 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 119 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 120 #define BCM_GPIO_WRITE(_sc, _off, _val) \ 121 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val) 122 #define BCM_GPIO_READ(_sc, _off) \ 123 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off) 124 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \ 125 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits)) 126 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \ 127 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits) 128 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK) 129 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK)) 130 131 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */ 132 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */ 133 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */ 134 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */ 135 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */ 136 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */ 137 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */ 138 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */ 139 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */ 140 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */ 141 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */ 142 #define BCM_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */ 143 #define BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */ 144 145 static struct ofw_compat_data compat_data[] = { 146 {"broadcom,bcm2835-gpio", 1}, 147 {"brcm,bcm2835-gpio", 1}, 148 {NULL, 0} 149 }; 150 151 static struct bcm_gpio_softc *bcm_gpio_sc = NULL; 152 153 static int bcm_gpio_intr_bank0(void *arg); 154 static int bcm_gpio_intr_bank1(void *arg); 155 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc); 156 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc); 157 158 static int 159 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin) 160 { 161 int i; 162 163 for (i = 0; i < sc->sc_ro_npins; i++) 164 if (pin == sc->sc_ro_pins[i]) 165 return (1); 166 return (0); 167 } 168 169 static uint32_t 170 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin) 171 { 172 uint32_t bank, func, offset; 173 174 /* Five banks, 10 pins per bank, 3 bits per pin. */ 175 bank = pin / 10; 176 offset = (pin - bank * 10) * 3; 177 178 BCM_GPIO_LOCK(sc); 179 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7; 180 BCM_GPIO_UNLOCK(sc); 181 182 return (func); 183 } 184 185 static void 186 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize) 187 { 188 189 switch (nfunc) { 190 case BCM_GPIO_INPUT: 191 strncpy(buf, "input", bufsize); 192 break; 193 case BCM_GPIO_OUTPUT: 194 strncpy(buf, "output", bufsize); 195 break; 196 case BCM_GPIO_ALT0: 197 strncpy(buf, "alt0", bufsize); 198 break; 199 case BCM_GPIO_ALT1: 200 strncpy(buf, "alt1", bufsize); 201 break; 202 case BCM_GPIO_ALT2: 203 strncpy(buf, "alt2", bufsize); 204 break; 205 case BCM_GPIO_ALT3: 206 strncpy(buf, "alt3", bufsize); 207 break; 208 case BCM_GPIO_ALT4: 209 strncpy(buf, "alt4", bufsize); 210 break; 211 case BCM_GPIO_ALT5: 212 strncpy(buf, "alt5", bufsize); 213 break; 214 default: 215 strncpy(buf, "invalid", bufsize); 216 } 217 } 218 219 static int 220 bcm_gpio_str_func(char *func, uint32_t *nfunc) 221 { 222 223 if (strcasecmp(func, "input") == 0) 224 *nfunc = BCM_GPIO_INPUT; 225 else if (strcasecmp(func, "output") == 0) 226 *nfunc = BCM_GPIO_OUTPUT; 227 else if (strcasecmp(func, "alt0") == 0) 228 *nfunc = BCM_GPIO_ALT0; 229 else if (strcasecmp(func, "alt1") == 0) 230 *nfunc = BCM_GPIO_ALT1; 231 else if (strcasecmp(func, "alt2") == 0) 232 *nfunc = BCM_GPIO_ALT2; 233 else if (strcasecmp(func, "alt3") == 0) 234 *nfunc = BCM_GPIO_ALT3; 235 else if (strcasecmp(func, "alt4") == 0) 236 *nfunc = BCM_GPIO_ALT4; 237 else if (strcasecmp(func, "alt5") == 0) 238 *nfunc = BCM_GPIO_ALT5; 239 else 240 return (-1); 241 242 return (0); 243 } 244 245 static uint32_t 246 bcm_gpio_func_flag(uint32_t nfunc) 247 { 248 249 switch (nfunc) { 250 case BCM_GPIO_INPUT: 251 return (GPIO_PIN_INPUT); 252 case BCM_GPIO_OUTPUT: 253 return (GPIO_PIN_OUTPUT); 254 } 255 return (0); 256 } 257 258 static void 259 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f) 260 { 261 uint32_t bank, data, offset; 262 263 /* Must be called with lock held. */ 264 BCM_GPIO_LOCK_ASSERT(sc); 265 266 /* Five banks, 10 pins per bank, 3 bits per pin. */ 267 bank = pin / 10; 268 offset = (pin - bank * 10) * 3; 269 270 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)); 271 data &= ~(7 << offset); 272 data |= (f << offset); 273 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data); 274 } 275 276 static void 277 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state) 278 { 279 uint32_t bank; 280 281 /* Must be called with lock held. */ 282 BCM_GPIO_LOCK_ASSERT(sc); 283 284 bank = BCM_GPIO_BANK(pin); 285 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), state); 286 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin)); 287 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), 0); 288 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), 0); 289 } 290 291 void 292 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc) 293 { 294 struct bcm_gpio_softc *sc; 295 int i; 296 297 sc = device_get_softc(dev); 298 BCM_GPIO_LOCK(sc); 299 300 /* Disable pull-up or pull-down on pin. */ 301 bcm_gpio_set_pud(sc, pin, BCM_GPIO_NONE); 302 303 /* And now set the pin function. */ 304 bcm_gpio_set_function(sc, pin, nfunc); 305 306 /* Update the pin flags. */ 307 for (i = 0; i < sc->sc_gpio_npins; i++) { 308 if (sc->sc_gpio_pins[i].gp_pin == pin) 309 break; 310 } 311 if (i < sc->sc_gpio_npins) 312 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc); 313 314 BCM_GPIO_UNLOCK(sc); 315 } 316 317 static void 318 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin, 319 unsigned int flags) 320 { 321 322 BCM_GPIO_LOCK(sc); 323 324 /* 325 * Manage input/output. 326 */ 327 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 328 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); 329 if (flags & GPIO_PIN_OUTPUT) { 330 pin->gp_flags |= GPIO_PIN_OUTPUT; 331 bcm_gpio_set_function(sc, pin->gp_pin, 332 BCM_GPIO_OUTPUT); 333 } else { 334 pin->gp_flags |= GPIO_PIN_INPUT; 335 bcm_gpio_set_function(sc, pin->gp_pin, 336 BCM_GPIO_INPUT); 337 } 338 } 339 340 /* Manage Pull-up/pull-down. */ 341 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN); 342 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 343 if (flags & GPIO_PIN_PULLUP) { 344 pin->gp_flags |= GPIO_PIN_PULLUP; 345 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP); 346 } else { 347 pin->gp_flags |= GPIO_PIN_PULLDOWN; 348 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN); 349 } 350 } else 351 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE); 352 353 BCM_GPIO_UNLOCK(sc); 354 } 355 356 static device_t 357 bcm_gpio_get_bus(device_t dev) 358 { 359 struct bcm_gpio_softc *sc; 360 361 sc = device_get_softc(dev); 362 363 return (sc->sc_busdev); 364 } 365 366 static int 367 bcm_gpio_pin_max(device_t dev, int *maxpin) 368 { 369 370 *maxpin = BCM_GPIO_PINS - 1; 371 return (0); 372 } 373 374 static int 375 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 376 { 377 struct bcm_gpio_softc *sc = device_get_softc(dev); 378 int i; 379 380 for (i = 0; i < sc->sc_gpio_npins; i++) { 381 if (sc->sc_gpio_pins[i].gp_pin == pin) 382 break; 383 } 384 385 if (i >= sc->sc_gpio_npins) 386 return (EINVAL); 387 388 BCM_GPIO_LOCK(sc); 389 *caps = sc->sc_gpio_pins[i].gp_caps; 390 BCM_GPIO_UNLOCK(sc); 391 392 return (0); 393 } 394 395 static int 396 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 397 { 398 struct bcm_gpio_softc *sc = device_get_softc(dev); 399 int i; 400 401 for (i = 0; i < sc->sc_gpio_npins; i++) { 402 if (sc->sc_gpio_pins[i].gp_pin == pin) 403 break; 404 } 405 406 if (i >= sc->sc_gpio_npins) 407 return (EINVAL); 408 409 BCM_GPIO_LOCK(sc); 410 *flags = sc->sc_gpio_pins[i].gp_flags; 411 BCM_GPIO_UNLOCK(sc); 412 413 return (0); 414 } 415 416 static int 417 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 418 { 419 struct bcm_gpio_softc *sc = device_get_softc(dev); 420 int i; 421 422 for (i = 0; i < sc->sc_gpio_npins; i++) { 423 if (sc->sc_gpio_pins[i].gp_pin == pin) 424 break; 425 } 426 427 if (i >= sc->sc_gpio_npins) 428 return (EINVAL); 429 430 BCM_GPIO_LOCK(sc); 431 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME); 432 BCM_GPIO_UNLOCK(sc); 433 434 return (0); 435 } 436 437 static int 438 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 439 { 440 struct bcm_gpio_softc *sc = device_get_softc(dev); 441 int i; 442 443 for (i = 0; i < sc->sc_gpio_npins; i++) { 444 if (sc->sc_gpio_pins[i].gp_pin == pin) 445 break; 446 } 447 448 if (i >= sc->sc_gpio_npins) 449 return (EINVAL); 450 451 /* We never touch on read-only/reserved pins. */ 452 if (bcm_gpio_pin_is_ro(sc, pin)) 453 return (EINVAL); 454 455 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags); 456 457 return (0); 458 } 459 460 static int 461 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 462 { 463 struct bcm_gpio_softc *sc = device_get_softc(dev); 464 uint32_t bank, reg; 465 int i; 466 467 for (i = 0; i < sc->sc_gpio_npins; i++) { 468 if (sc->sc_gpio_pins[i].gp_pin == pin) 469 break; 470 } 471 if (i >= sc->sc_gpio_npins) 472 return (EINVAL); 473 /* We never write to read-only/reserved pins. */ 474 if (bcm_gpio_pin_is_ro(sc, pin)) 475 return (EINVAL); 476 BCM_GPIO_LOCK(sc); 477 bank = BCM_GPIO_BANK(pin); 478 if (value) 479 reg = BCM_GPIO_GPSET(bank); 480 else 481 reg = BCM_GPIO_GPCLR(bank); 482 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 483 BCM_GPIO_UNLOCK(sc); 484 485 return (0); 486 } 487 488 static int 489 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 490 { 491 struct bcm_gpio_softc *sc = device_get_softc(dev); 492 uint32_t bank, reg_data; 493 int i; 494 495 for (i = 0; i < sc->sc_gpio_npins; i++) { 496 if (sc->sc_gpio_pins[i].gp_pin == pin) 497 break; 498 } 499 if (i >= sc->sc_gpio_npins) 500 return (EINVAL); 501 bank = BCM_GPIO_BANK(pin); 502 BCM_GPIO_LOCK(sc); 503 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 504 BCM_GPIO_UNLOCK(sc); 505 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0; 506 507 return (0); 508 } 509 510 static int 511 bcm_gpio_pin_toggle(device_t dev, uint32_t pin) 512 { 513 struct bcm_gpio_softc *sc = device_get_softc(dev); 514 uint32_t bank, data, reg; 515 int i; 516 517 for (i = 0; i < sc->sc_gpio_npins; i++) { 518 if (sc->sc_gpio_pins[i].gp_pin == pin) 519 break; 520 } 521 if (i >= sc->sc_gpio_npins) 522 return (EINVAL); 523 /* We never write to read-only/reserved pins. */ 524 if (bcm_gpio_pin_is_ro(sc, pin)) 525 return (EINVAL); 526 BCM_GPIO_LOCK(sc); 527 bank = BCM_GPIO_BANK(pin); 528 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 529 if (data & BCM_GPIO_MASK(pin)) 530 reg = BCM_GPIO_GPCLR(bank); 531 else 532 reg = BCM_GPIO_GPSET(bank); 533 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 534 BCM_GPIO_UNLOCK(sc); 535 536 return (0); 537 } 538 539 static int 540 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS) 541 { 542 char buf[16]; 543 struct bcm_gpio_softc *sc; 544 struct bcm_gpio_sysctl *sc_sysctl; 545 uint32_t nfunc; 546 int error; 547 548 sc_sysctl = arg1; 549 sc = sc_sysctl->sc; 550 551 /* Get the current pin function. */ 552 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin); 553 bcm_gpio_func_str(nfunc, buf, sizeof(buf)); 554 555 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 556 if (error != 0 || req->newptr == NULL) 557 return (error); 558 /* Ignore changes on read-only pins. */ 559 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin)) 560 return (0); 561 /* Parse the user supplied string and check for a valid pin function. */ 562 if (bcm_gpio_str_func(buf, &nfunc) != 0) 563 return (EINVAL); 564 565 /* Update the pin alternate function. */ 566 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc); 567 568 return (0); 569 } 570 571 static void 572 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc) 573 { 574 char pinbuf[3]; 575 struct bcm_gpio_sysctl *sc_sysctl; 576 struct sysctl_ctx_list *ctx; 577 struct sysctl_oid *tree_node, *pin_node, *pinN_node; 578 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree; 579 int i; 580 581 /* 582 * Add per-pin sysctl tree/handlers. 583 */ 584 ctx = device_get_sysctl_ctx(sc->sc_dev); 585 tree_node = device_get_sysctl_tree(sc->sc_dev); 586 tree = SYSCTL_CHILDREN(tree_node); 587 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin", 588 CTLFLAG_RD, NULL, "GPIO Pins"); 589 pin_tree = SYSCTL_CHILDREN(pin_node); 590 591 for (i = 0; i < sc->sc_gpio_npins; i++) { 592 593 snprintf(pinbuf, sizeof(pinbuf), "%d", i); 594 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf, 595 CTLFLAG_RD, NULL, "GPIO Pin"); 596 pinN_tree = SYSCTL_CHILDREN(pinN_node); 597 598 sc->sc_sysctl[i].sc = sc; 599 sc_sysctl = &sc->sc_sysctl[i]; 600 sc_sysctl->sc = sc; 601 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin; 602 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function", 603 CTLFLAG_RW | CTLTYPE_STRING, sc_sysctl, 604 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc, 605 "A", "Pin Function"); 606 } 607 } 608 609 static int 610 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node, 611 const char *propname, const char *label) 612 { 613 int i, need_comma, npins, range_start, range_stop; 614 pcell_t *pins; 615 616 /* Get the property data. */ 617 npins = OF_getencprop_alloc(node, propname, sizeof(*pins), 618 (void **)&pins); 619 if (npins < 0) 620 return (-1); 621 if (npins == 0) { 622 OF_prop_free(pins); 623 return (0); 624 } 625 for (i = 0; i < npins; i++) 626 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i]; 627 sc->sc_ro_npins += npins; 628 need_comma = 0; 629 device_printf(sc->sc_dev, "%s pins: ", label); 630 range_start = range_stop = pins[0]; 631 for (i = 1; i < npins; i++) { 632 if (pins[i] != range_stop + 1) { 633 if (need_comma) 634 printf(","); 635 if (range_start != range_stop) 636 printf("%d-%d", range_start, range_stop); 637 else 638 printf("%d", range_start); 639 range_start = range_stop = pins[i]; 640 need_comma = 1; 641 } else 642 range_stop++; 643 } 644 if (need_comma) 645 printf(","); 646 if (range_start != range_stop) 647 printf("%d-%d.\n", range_start, range_stop); 648 else 649 printf("%d.\n", range_start); 650 OF_prop_free(pins); 651 652 return (0); 653 } 654 655 static int 656 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc) 657 { 658 char *name; 659 phandle_t gpio, node, reserved; 660 ssize_t len; 661 662 /* Get read-only pins if they're provided */ 663 gpio = ofw_bus_get_node(sc->sc_dev); 664 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only", 665 "read-only") != 0) 666 return (0); 667 /* Traverse the GPIO subnodes to find the reserved pins node. */ 668 reserved = 0; 669 node = OF_child(gpio); 670 while ((node != 0) && (reserved == 0)) { 671 len = OF_getprop_alloc(node, "name", 1, (void **)&name); 672 if (len == -1) 673 return (-1); 674 if (strcmp(name, "reserved") == 0) 675 reserved = node; 676 OF_prop_free(name); 677 node = OF_peer(node); 678 } 679 if (reserved == 0) 680 return (-1); 681 /* Get the reserved pins. */ 682 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins", 683 "reserved") != 0) 684 return (-1); 685 686 return (0); 687 } 688 689 static int 690 bcm_gpio_probe(device_t dev) 691 { 692 693 if (!ofw_bus_status_okay(dev)) 694 return (ENXIO); 695 696 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 697 return (ENXIO); 698 699 device_set_desc(dev, "BCM2708/2835 GPIO controller"); 700 return (BUS_PROBE_DEFAULT); 701 } 702 703 static int 704 bcm_gpio_intr_attach(device_t dev) 705 { 706 struct bcm_gpio_softc *sc; 707 708 /* 709 * Only first two interrupt lines are used. Third line is 710 * mirrored second line and forth line is common for all banks. 711 */ 712 sc = device_get_softc(dev); 713 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL) 714 return (-1); 715 716 if (bcm_gpio_pic_attach(sc) != 0) { 717 device_printf(dev, "unable to attach PIC\n"); 718 return (-1); 719 } 720 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE, 721 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0) 722 return (-1); 723 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE, 724 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0) 725 return (-1); 726 727 return (0); 728 } 729 730 static void 731 bcm_gpio_intr_detach(device_t dev) 732 { 733 struct bcm_gpio_softc *sc; 734 735 sc = device_get_softc(dev); 736 if (sc->sc_intrhand[0] != NULL) 737 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]); 738 if (sc->sc_intrhand[1] != NULL) 739 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]); 740 741 bcm_gpio_pic_detach(sc); 742 } 743 744 static int 745 bcm_gpio_attach(device_t dev) 746 { 747 int i, j; 748 phandle_t gpio; 749 struct bcm_gpio_softc *sc; 750 uint32_t func; 751 752 if (bcm_gpio_sc != NULL) 753 return (ENXIO); 754 755 bcm_gpio_sc = sc = device_get_softc(dev); 756 sc->sc_dev = dev; 757 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN); 758 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) { 759 device_printf(dev, "cannot allocate resources\n"); 760 goto fail; 761 } 762 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 763 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 764 /* Setup the GPIO interrupt handler. */ 765 if (bcm_gpio_intr_attach(dev)) { 766 device_printf(dev, "unable to setup the gpio irq handler\n"); 767 goto fail; 768 } 769 /* Find our node. */ 770 gpio = ofw_bus_get_node(sc->sc_dev); 771 if (!OF_hasprop(gpio, "gpio-controller")) 772 /* Node is not a GPIO controller. */ 773 goto fail; 774 /* 775 * Find the read-only pins. These are pins we never touch or bad 776 * things could happen. 777 */ 778 if (bcm_gpio_get_reserved_pins(sc) == -1) 779 goto fail; 780 /* Initialize the software controlled pins. */ 781 for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) { 782 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, 783 "pin %d", j); 784 func = bcm_gpio_get_function(sc, j); 785 sc->sc_gpio_pins[i].gp_pin = j; 786 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS; 787 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func); 788 i++; 789 } 790 sc->sc_gpio_npins = i; 791 bcm_gpio_sysctl_init(sc); 792 sc->sc_busdev = gpiobus_attach_bus(dev); 793 if (sc->sc_busdev == NULL) 794 goto fail; 795 796 return (0); 797 798 fail: 799 bcm_gpio_intr_detach(dev); 800 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res); 801 mtx_destroy(&sc->sc_mtx); 802 803 return (ENXIO); 804 } 805 806 static int 807 bcm_gpio_detach(device_t dev) 808 { 809 810 return (EBUSY); 811 } 812 813 static inline void 814 bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask, 815 bool set_bits) 816 { 817 818 if (set_bits) 819 BCM_GPIO_SET_BITS(sc, reg, mask); 820 else 821 BCM_GPIO_CLEAR_BITS(sc, reg, mask); 822 } 823 824 static inline void 825 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 826 { 827 uint32_t bank; 828 829 /* Write 1 to clear. */ 830 bank = BCM_GPIO_BANK(bgi->bgi_irq); 831 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask); 832 } 833 834 static inline bool 835 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi) 836 { 837 838 return (bgi->bgi_mode == GPIO_INTR_LEVEL_LOW || 839 bgi->bgi_mode == GPIO_INTR_LEVEL_HIGH); 840 } 841 842 static inline void 843 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 844 { 845 uint32_t bank; 846 847 bank = BCM_GPIO_BANK(bgi->bgi_irq); 848 BCM_GPIO_LOCK(sc); 849 switch (bgi->bgi_mode) { 850 case GPIO_INTR_LEVEL_LOW: 851 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 852 break; 853 case GPIO_INTR_LEVEL_HIGH: 854 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 855 break; 856 case GPIO_INTR_EDGE_RISING: 857 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 858 break; 859 case GPIO_INTR_EDGE_FALLING: 860 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 861 break; 862 case GPIO_INTR_EDGE_BOTH: 863 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 864 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 865 break; 866 } 867 BCM_GPIO_UNLOCK(sc); 868 } 869 870 static inline void 871 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 872 { 873 uint32_t bank; 874 875 bank = BCM_GPIO_BANK(bgi->bgi_irq); 876 BCM_GPIO_LOCK(sc); 877 switch (bgi->bgi_mode) { 878 case GPIO_INTR_LEVEL_LOW: 879 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 880 break; 881 case GPIO_INTR_LEVEL_HIGH: 882 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 883 break; 884 case GPIO_INTR_EDGE_RISING: 885 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 886 break; 887 case GPIO_INTR_EDGE_FALLING: 888 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 889 break; 890 case GPIO_INTR_EDGE_BOTH: 891 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 892 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 893 break; 894 } 895 BCM_GPIO_UNLOCK(sc); 896 } 897 898 static int 899 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank) 900 { 901 u_int irq; 902 struct bcm_gpio_irqsrc *bgi; 903 uint32_t reg; 904 905 /* Do not care of spurious interrupt on GPIO. */ 906 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); 907 while (reg != 0) { 908 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1; 909 bgi = sc->sc_isrcs + irq; 910 if (!bcm_gpio_isrc_is_level(bgi)) 911 bcm_gpio_isrc_eoi(sc, bgi); 912 if (intr_isrc_dispatch(&bgi->bgi_isrc, 913 curthread->td_intr_frame) != 0) { 914 bcm_gpio_isrc_mask(sc, bgi); 915 if (bcm_gpio_isrc_is_level(bgi)) 916 bcm_gpio_isrc_eoi(sc, bgi); 917 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 918 irq); 919 } 920 reg &= ~bgi->bgi_mask; 921 } 922 return (FILTER_HANDLED); 923 } 924 925 static int 926 bcm_gpio_intr_bank0(void *arg) 927 { 928 929 return (bcm_gpio_intr_internal(arg, 0)); 930 } 931 932 static int 933 bcm_gpio_intr_bank1(void *arg) 934 { 935 936 return (bcm_gpio_intr_internal(arg, 1)); 937 } 938 939 static int 940 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc) 941 { 942 int error; 943 uint32_t irq; 944 const char *name; 945 946 name = device_get_nameunit(sc->sc_dev); 947 for (irq = 0; irq < BCM_GPIO_PINS; irq++) { 948 sc->sc_isrcs[irq].bgi_irq = irq; 949 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq); 950 sc->sc_isrcs[irq].bgi_mode = GPIO_INTR_CONFORM; 951 952 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc, 953 sc->sc_dev, 0, "%s,%u", name, irq); 954 if (error != 0) 955 return (error); /* XXX deregister ISRCs */ 956 } 957 if (intr_pic_register(sc->sc_dev, 958 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 959 return (ENXIO); 960 961 return (0); 962 } 963 964 static int 965 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc) 966 { 967 968 /* 969 * There has not been established any procedure yet 970 * how to detach PIC from living system correctly. 971 */ 972 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 973 return (EBUSY); 974 } 975 976 static void 977 bcm_gpio_pic_config_intr(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi, 978 uint32_t mode) 979 { 980 uint32_t bank; 981 982 bank = BCM_GPIO_BANK(bgi->bgi_irq); 983 BCM_GPIO_LOCK(sc); 984 bcm_gpio_modify(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask, 985 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 986 bcm_gpio_modify(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask, 987 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 988 bcm_gpio_modify(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask, 989 mode == GPIO_INTR_LEVEL_HIGH); 990 bcm_gpio_modify(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask, 991 mode == GPIO_INTR_LEVEL_LOW); 992 bgi->bgi_mode = mode; 993 BCM_GPIO_UNLOCK(sc); 994 } 995 996 static void 997 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 998 { 999 struct bcm_gpio_softc *sc = device_get_softc(dev); 1000 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1001 1002 bcm_gpio_isrc_mask(sc, bgi); 1003 } 1004 1005 static void 1006 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 1007 { 1008 struct bcm_gpio_softc *sc = device_get_softc(dev); 1009 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1010 1011 arm_irq_memory_barrier(bgi->bgi_irq); 1012 bcm_gpio_isrc_unmask(sc, bgi); 1013 } 1014 1015 static int 1016 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf, 1017 u_int *irqp, uint32_t *modep) 1018 { 1019 u_int irq; 1020 uint32_t mode; 1021 1022 /* 1023 * The first cell is the interrupt number. 1024 * The second cell is used to specify flags: 1025 * bits[3:0] trigger type and level flags: 1026 * 1 = low-to-high edge triggered. 1027 * 2 = high-to-low edge triggered. 1028 * 4 = active high level-sensitive. 1029 * 8 = active low level-sensitive. 1030 */ 1031 if (daf->ncells != 2) 1032 return (EINVAL); 1033 1034 irq = daf->cells[0]; 1035 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1036 return (EINVAL); 1037 1038 /* Only reasonable modes are supported. */ 1039 if (daf->cells[1] == 1) 1040 mode = GPIO_INTR_EDGE_RISING; 1041 else if (daf->cells[1] == 2) 1042 mode = GPIO_INTR_EDGE_FALLING; 1043 else if (daf->cells[1] == 3) 1044 mode = GPIO_INTR_EDGE_BOTH; 1045 else if (daf->cells[1] == 4) 1046 mode = GPIO_INTR_LEVEL_HIGH; 1047 else if (daf->cells[1] == 8) 1048 mode = GPIO_INTR_LEVEL_LOW; 1049 else 1050 return (EINVAL); 1051 1052 *irqp = irq; 1053 if (modep != NULL) 1054 *modep = mode; 1055 return (0); 1056 } 1057 1058 static int 1059 bcm_gpio_pic_map_gpio(struct bcm_gpio_softc *sc, struct intr_map_data_gpio *dag, 1060 u_int *irqp, uint32_t *modep) 1061 { 1062 u_int irq; 1063 uint32_t mode; 1064 1065 irq = dag->gpio_pin_num; 1066 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1067 return (EINVAL); 1068 1069 mode = dag->gpio_intr_mode; 1070 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 1071 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 1072 mode != GPIO_INTR_EDGE_BOTH) 1073 return (EINVAL); 1074 1075 *irqp = irq; 1076 if (modep != NULL) 1077 *modep = mode; 1078 return (0); 1079 } 1080 1081 static int 1082 bcm_gpio_pic_map(struct bcm_gpio_softc *sc, struct intr_map_data *data, 1083 u_int *irqp, uint32_t *modep) 1084 { 1085 1086 switch (data->type) { 1087 case INTR_MAP_DATA_FDT: 1088 return (bcm_gpio_pic_map_fdt(sc, 1089 (struct intr_map_data_fdt *)data, irqp, modep)); 1090 case INTR_MAP_DATA_GPIO: 1091 return (bcm_gpio_pic_map_gpio(sc, 1092 (struct intr_map_data_gpio *)data, irqp, modep)); 1093 default: 1094 return (ENOTSUP); 1095 } 1096 } 1097 1098 static int 1099 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1100 struct intr_irqsrc **isrcp) 1101 { 1102 int error; 1103 u_int irq; 1104 struct bcm_gpio_softc *sc = device_get_softc(dev); 1105 1106 error = bcm_gpio_pic_map(sc, data, &irq, NULL); 1107 if (error == 0) 1108 *isrcp = &sc->sc_isrcs[irq].bgi_isrc; 1109 return (error); 1110 } 1111 1112 static void 1113 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1114 { 1115 struct bcm_gpio_softc *sc = device_get_softc(dev); 1116 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1117 1118 if (bcm_gpio_isrc_is_level(bgi)) 1119 bcm_gpio_isrc_eoi(sc, bgi); 1120 } 1121 1122 static void 1123 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1124 { 1125 1126 bcm_gpio_pic_enable_intr(dev, isrc); 1127 } 1128 1129 static void 1130 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1131 { 1132 struct bcm_gpio_softc *sc = device_get_softc(dev); 1133 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1134 1135 bcm_gpio_isrc_mask(sc, bgi); 1136 if (bcm_gpio_isrc_is_level(bgi)) 1137 bcm_gpio_isrc_eoi(sc, bgi); 1138 } 1139 1140 static int 1141 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1142 struct resource *res, struct intr_map_data *data) 1143 { 1144 u_int irq; 1145 uint32_t mode; 1146 struct bcm_gpio_softc *sc; 1147 struct bcm_gpio_irqsrc *bgi; 1148 1149 if (data == NULL) 1150 return (ENOTSUP); 1151 1152 sc = device_get_softc(dev); 1153 bgi = (struct bcm_gpio_irqsrc *)isrc; 1154 1155 /* Get and check config for an interrupt. */ 1156 if (bcm_gpio_pic_map(sc, data, &irq, &mode) != 0 || bgi->bgi_irq != irq) 1157 return (EINVAL); 1158 1159 /* 1160 * If this is a setup for another handler, 1161 * only check that its configuration match. 1162 */ 1163 if (isrc->isrc_handlers != 0) 1164 return (bgi->bgi_mode == mode ? 0 : EINVAL); 1165 1166 bcm_gpio_pic_config_intr(sc, bgi, mode); 1167 return (0); 1168 } 1169 1170 static int 1171 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1172 struct resource *res, struct intr_map_data *data) 1173 { 1174 struct bcm_gpio_softc *sc = device_get_softc(dev); 1175 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1176 1177 if (isrc->isrc_handlers == 0) 1178 bcm_gpio_pic_config_intr(sc, bgi, GPIO_INTR_CONFORM); 1179 return (0); 1180 } 1181 1182 static phandle_t 1183 bcm_gpio_get_node(device_t bus, device_t dev) 1184 { 1185 1186 /* We only have one child, the GPIO bus, which needs our own node. */ 1187 return (ofw_bus_get_node(bus)); 1188 } 1189 1190 static device_method_t bcm_gpio_methods[] = { 1191 /* Device interface */ 1192 DEVMETHOD(device_probe, bcm_gpio_probe), 1193 DEVMETHOD(device_attach, bcm_gpio_attach), 1194 DEVMETHOD(device_detach, bcm_gpio_detach), 1195 1196 /* GPIO protocol */ 1197 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus), 1198 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max), 1199 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname), 1200 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags), 1201 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps), 1202 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags), 1203 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get), 1204 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set), 1205 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle), 1206 1207 /* Interrupt controller interface */ 1208 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr), 1209 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr), 1210 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr), 1211 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter), 1212 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread), 1213 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread), 1214 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr), 1215 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr), 1216 1217 /* ofw_bus interface */ 1218 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node), 1219 1220 DEVMETHOD_END 1221 }; 1222 1223 static devclass_t bcm_gpio_devclass; 1224 1225 static driver_t bcm_gpio_driver = { 1226 "gpio", 1227 bcm_gpio_methods, 1228 sizeof(struct bcm_gpio_softc), 1229 }; 1230 1231 DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, bcm_gpio_devclass, 0, 0); 1232