xref: /freebsd/sys/arm/broadcom/bcm2835/bcm2835_gpio.c (revision d9f0ce31900a48d1a2bfc1c8c86f79d1e831451a)
1 /*-
2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3  * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org>
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  */
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 #include "opt_platform.h"
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/gpio.h>
37 #include <sys/interrupt.h>
38 #include <sys/kernel.h>
39 #include <sys/lock.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/sysctl.h>
45 
46 #include <machine/bus.h>
47 #include <machine/intr.h>
48 
49 #include <dev/gpio/gpiobusvar.h>
50 #include <dev/ofw/ofw_bus.h>
51 
52 #include <arm/broadcom/bcm2835/bcm2835_gpio.h>
53 
54 #include "gpio_if.h"
55 
56 #ifdef INTRNG
57 #include "pic_if.h"
58 #endif
59 
60 #ifdef DEBUG
61 #define dprintf(fmt, args...) do { printf("%s(): ", __func__);   \
62     printf(fmt,##args); } while (0)
63 #else
64 #define dprintf(fmt, args...)
65 #endif
66 
67 #define	BCM_GPIO_IRQS		4
68 #define	BCM_GPIO_PINS		54
69 #define	BCM_GPIO_PINS_PER_BANK	32
70 #define	BCM_GPIO_DEFAULT_CAPS	(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |	\
71     GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
72 
73 static struct resource_spec bcm_gpio_res_spec[] = {
74 	{ SYS_RES_MEMORY, 0, RF_ACTIVE },
75 	{ SYS_RES_IRQ, 0, RF_ACTIVE },	/* bank 0 interrupt */
76 	{ SYS_RES_IRQ, 1, RF_ACTIVE },	/* bank 1 interrupt */
77 	{ SYS_RES_IRQ, 2, RF_ACTIVE },	/* bank 1 interrupt (mirrored) */
78 	{ SYS_RES_IRQ, 3, RF_ACTIVE },	/* bank 0-1 interrupt (united) */
79 	{ -1, 0, 0 }
80 };
81 
82 struct bcm_gpio_sysctl {
83 	struct bcm_gpio_softc	*sc;
84 	uint32_t		pin;
85 };
86 
87 #ifdef INTRNG
88 struct bcm_gpio_irqsrc {
89 	struct intr_irqsrc	bgi_isrc;
90 	uint32_t		bgi_irq;
91 	uint32_t		bgi_reg;
92 	uint32_t		bgi_mask;
93 };
94 #endif
95 
96 struct bcm_gpio_softc {
97 	device_t		sc_dev;
98 	device_t		sc_busdev;
99 	struct mtx		sc_mtx;
100 	struct resource *	sc_res[BCM_GPIO_IRQS + 1];
101 	bus_space_tag_t		sc_bst;
102 	bus_space_handle_t	sc_bsh;
103 	void *			sc_intrhand[BCM_GPIO_IRQS];
104 	int			sc_gpio_npins;
105 	int			sc_ro_npins;
106 	int			sc_ro_pins[BCM_GPIO_PINS];
107 	struct gpio_pin		sc_gpio_pins[BCM_GPIO_PINS];
108 #ifndef INTRNG
109 	struct intr_event *	sc_events[BCM_GPIO_PINS];
110 #endif
111 	struct bcm_gpio_sysctl	sc_sysctl[BCM_GPIO_PINS];
112 #ifdef INTRNG
113 	struct bcm_gpio_irqsrc	sc_isrcs[BCM_GPIO_PINS];
114 #else
115 	enum intr_trigger	sc_irq_trigger[BCM_GPIO_PINS];
116 	enum intr_polarity	sc_irq_polarity[BCM_GPIO_PINS];
117 #endif
118 };
119 
120 enum bcm_gpio_pud {
121 	BCM_GPIO_NONE,
122 	BCM_GPIO_PULLDOWN,
123 	BCM_GPIO_PULLUP,
124 };
125 
126 #define	BCM_GPIO_LOCK(_sc)	mtx_lock_spin(&(_sc)->sc_mtx)
127 #define	BCM_GPIO_UNLOCK(_sc)	mtx_unlock_spin(&(_sc)->sc_mtx)
128 #define	BCM_GPIO_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
129 #define	BCM_GPIO_WRITE(_sc, _off, _val)		\
130     bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
131 #define	BCM_GPIO_READ(_sc, _off)		\
132     bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
133 #define	BCM_GPIO_CLEAR_BITS(_sc, _off, _bits)	\
134     BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits))
135 #define	BCM_GPIO_SET_BITS(_sc, _off, _bits)	\
136     BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits)
137 #define	BCM_GPIO_BANK(a)	(a / BCM_GPIO_PINS_PER_BANK)
138 #define	BCM_GPIO_MASK(a)	(1U << (a % BCM_GPIO_PINS_PER_BANK))
139 
140 #define	BCM_GPIO_GPFSEL(_bank)	(0x00 + _bank * 4)	/* Function Select */
141 #define	BCM_GPIO_GPSET(_bank)	(0x1c + _bank * 4)	/* Pin Out Set */
142 #define	BCM_GPIO_GPCLR(_bank)	(0x28 + _bank * 4)	/* Pin Out Clear */
143 #define	BCM_GPIO_GPLEV(_bank)	(0x34 + _bank * 4)	/* Pin Level */
144 #define	BCM_GPIO_GPEDS(_bank)	(0x40 + _bank * 4)	/* Event Status */
145 #define	BCM_GPIO_GPREN(_bank)	(0x4c + _bank * 4)	/* Rising Edge irq */
146 #define	BCM_GPIO_GPFEN(_bank)	(0x58 + _bank * 4)	/* Falling Edge irq */
147 #define	BCM_GPIO_GPHEN(_bank)	(0x64 + _bank * 4)	/* High Level irq */
148 #define	BCM_GPIO_GPLEN(_bank)	(0x70 + _bank * 4)	/* Low Level irq */
149 #define	BCM_GPIO_GPAREN(_bank)	(0x7c + _bank * 4)	/* Async Rising Edge */
150 #define	BCM_GPIO_GPAFEN(_bank)	(0x88 + _bank * 4)	/* Async Falling Egde */
151 #define	BCM_GPIO_GPPUD(_bank)	(0x94)			/* Pin Pull up/down */
152 #define	BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4)	/* Pin Pull up clock */
153 
154 static struct bcm_gpio_softc *bcm_gpio_sc = NULL;
155 
156 #ifdef INTRNG
157 static int bcm_gpio_intr_bank0(void *arg);
158 static int bcm_gpio_intr_bank1(void *arg);
159 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc);
160 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc);
161 #endif
162 
163 static int
164 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin)
165 {
166 	int i;
167 
168 	for (i = 0; i < sc->sc_ro_npins; i++)
169 		if (pin == sc->sc_ro_pins[i])
170 			return (1);
171 	return (0);
172 }
173 
174 static uint32_t
175 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin)
176 {
177 	uint32_t bank, func, offset;
178 
179 	/* Five banks, 10 pins per bank, 3 bits per pin. */
180 	bank = pin / 10;
181 	offset = (pin - bank * 10) * 3;
182 
183 	BCM_GPIO_LOCK(sc);
184 	func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7;
185 	BCM_GPIO_UNLOCK(sc);
186 
187 	return (func);
188 }
189 
190 static void
191 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize)
192 {
193 
194 	switch (nfunc) {
195 	case BCM_GPIO_INPUT:
196 		strncpy(buf, "input", bufsize);
197 		break;
198 	case BCM_GPIO_OUTPUT:
199 		strncpy(buf, "output", bufsize);
200 		break;
201 	case BCM_GPIO_ALT0:
202 		strncpy(buf, "alt0", bufsize);
203 		break;
204 	case BCM_GPIO_ALT1:
205 		strncpy(buf, "alt1", bufsize);
206 		break;
207 	case BCM_GPIO_ALT2:
208 		strncpy(buf, "alt2", bufsize);
209 		break;
210 	case BCM_GPIO_ALT3:
211 		strncpy(buf, "alt3", bufsize);
212 		break;
213 	case BCM_GPIO_ALT4:
214 		strncpy(buf, "alt4", bufsize);
215 		break;
216 	case BCM_GPIO_ALT5:
217 		strncpy(buf, "alt5", bufsize);
218 		break;
219 	default:
220 		strncpy(buf, "invalid", bufsize);
221 	}
222 }
223 
224 static int
225 bcm_gpio_str_func(char *func, uint32_t *nfunc)
226 {
227 
228 	if (strcasecmp(func, "input") == 0)
229 		*nfunc = BCM_GPIO_INPUT;
230 	else if (strcasecmp(func, "output") == 0)
231 		*nfunc = BCM_GPIO_OUTPUT;
232 	else if (strcasecmp(func, "alt0") == 0)
233 		*nfunc = BCM_GPIO_ALT0;
234 	else if (strcasecmp(func, "alt1") == 0)
235 		*nfunc = BCM_GPIO_ALT1;
236 	else if (strcasecmp(func, "alt2") == 0)
237 		*nfunc = BCM_GPIO_ALT2;
238 	else if (strcasecmp(func, "alt3") == 0)
239 		*nfunc = BCM_GPIO_ALT3;
240 	else if (strcasecmp(func, "alt4") == 0)
241 		*nfunc = BCM_GPIO_ALT4;
242 	else if (strcasecmp(func, "alt5") == 0)
243 		*nfunc = BCM_GPIO_ALT5;
244 	else
245 		return (-1);
246 
247 	return (0);
248 }
249 
250 static uint32_t
251 bcm_gpio_func_flag(uint32_t nfunc)
252 {
253 
254 	switch (nfunc) {
255 	case BCM_GPIO_INPUT:
256 		return (GPIO_PIN_INPUT);
257 	case BCM_GPIO_OUTPUT:
258 		return (GPIO_PIN_OUTPUT);
259 	}
260 	return (0);
261 }
262 
263 static void
264 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f)
265 {
266 	uint32_t bank, data, offset;
267 
268 	/* Must be called with lock held. */
269 	BCM_GPIO_LOCK_ASSERT(sc);
270 
271 	/* Five banks, 10 pins per bank, 3 bits per pin. */
272 	bank = pin / 10;
273 	offset = (pin - bank * 10) * 3;
274 
275 	data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank));
276 	data &= ~(7 << offset);
277 	data |= (f << offset);
278 	BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data);
279 }
280 
281 static void
282 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state)
283 {
284 	uint32_t bank;
285 
286 	/* Must be called with lock held. */
287 	BCM_GPIO_LOCK_ASSERT(sc);
288 
289 	bank = BCM_GPIO_BANK(pin);
290 	BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), state);
291 	BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin));
292 	BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), 0);
293 	BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), 0);
294 }
295 
296 void
297 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc)
298 {
299 	struct bcm_gpio_softc *sc;
300 	int i;
301 
302 	sc = device_get_softc(dev);
303 	BCM_GPIO_LOCK(sc);
304 
305 	/* Disable pull-up or pull-down on pin. */
306 	bcm_gpio_set_pud(sc, pin, BCM_GPIO_NONE);
307 
308 	/* And now set the pin function. */
309 	bcm_gpio_set_function(sc, pin, nfunc);
310 
311 	/* Update the pin flags. */
312 	for (i = 0; i < sc->sc_gpio_npins; i++) {
313 		if (sc->sc_gpio_pins[i].gp_pin == pin)
314 			break;
315 	}
316 	if (i < sc->sc_gpio_npins)
317 		sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc);
318 
319         BCM_GPIO_UNLOCK(sc);
320 }
321 
322 static void
323 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin,
324     unsigned int flags)
325 {
326 
327 	BCM_GPIO_LOCK(sc);
328 
329 	/*
330 	 * Manage input/output.
331 	 */
332 	if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
333 		pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
334 		if (flags & GPIO_PIN_OUTPUT) {
335 			pin->gp_flags |= GPIO_PIN_OUTPUT;
336 			bcm_gpio_set_function(sc, pin->gp_pin,
337 			    BCM_GPIO_OUTPUT);
338 		} else {
339 			pin->gp_flags |= GPIO_PIN_INPUT;
340 			bcm_gpio_set_function(sc, pin->gp_pin,
341 			    BCM_GPIO_INPUT);
342 		}
343 	}
344 
345 	/* Manage Pull-up/pull-down. */
346 	pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN);
347 	if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
348 		if (flags & GPIO_PIN_PULLUP) {
349 			pin->gp_flags |= GPIO_PIN_PULLUP;
350 			bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP);
351 		} else {
352 			pin->gp_flags |= GPIO_PIN_PULLDOWN;
353 			bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN);
354 		}
355 	} else
356 		bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE);
357 
358 	BCM_GPIO_UNLOCK(sc);
359 }
360 
361 static device_t
362 bcm_gpio_get_bus(device_t dev)
363 {
364 	struct bcm_gpio_softc *sc;
365 
366 	sc = device_get_softc(dev);
367 
368 	return (sc->sc_busdev);
369 }
370 
371 static int
372 bcm_gpio_pin_max(device_t dev, int *maxpin)
373 {
374 
375 	*maxpin = BCM_GPIO_PINS - 1;
376 	return (0);
377 }
378 
379 static int
380 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
381 {
382 	struct bcm_gpio_softc *sc = device_get_softc(dev);
383 	int i;
384 
385 	for (i = 0; i < sc->sc_gpio_npins; i++) {
386 		if (sc->sc_gpio_pins[i].gp_pin == pin)
387 			break;
388 	}
389 
390 	if (i >= sc->sc_gpio_npins)
391 		return (EINVAL);
392 
393 	BCM_GPIO_LOCK(sc);
394 	*caps = sc->sc_gpio_pins[i].gp_caps;
395 	BCM_GPIO_UNLOCK(sc);
396 
397 	return (0);
398 }
399 
400 static int
401 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
402 {
403 	struct bcm_gpio_softc *sc = device_get_softc(dev);
404 	int i;
405 
406 	for (i = 0; i < sc->sc_gpio_npins; i++) {
407 		if (sc->sc_gpio_pins[i].gp_pin == pin)
408 			break;
409 	}
410 
411 	if (i >= sc->sc_gpio_npins)
412 		return (EINVAL);
413 
414 	BCM_GPIO_LOCK(sc);
415 	*flags = sc->sc_gpio_pins[i].gp_flags;
416 	BCM_GPIO_UNLOCK(sc);
417 
418 	return (0);
419 }
420 
421 static int
422 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
423 {
424 	struct bcm_gpio_softc *sc = device_get_softc(dev);
425 	int i;
426 
427 	for (i = 0; i < sc->sc_gpio_npins; i++) {
428 		if (sc->sc_gpio_pins[i].gp_pin == pin)
429 			break;
430 	}
431 
432 	if (i >= sc->sc_gpio_npins)
433 		return (EINVAL);
434 
435 	BCM_GPIO_LOCK(sc);
436 	memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME);
437 	BCM_GPIO_UNLOCK(sc);
438 
439 	return (0);
440 }
441 
442 static int
443 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
444 {
445 	struct bcm_gpio_softc *sc = device_get_softc(dev);
446 	int i;
447 
448 	for (i = 0; i < sc->sc_gpio_npins; i++) {
449 		if (sc->sc_gpio_pins[i].gp_pin == pin)
450 			break;
451 	}
452 
453 	if (i >= sc->sc_gpio_npins)
454 		return (EINVAL);
455 
456 	/* We never touch on read-only/reserved pins. */
457 	if (bcm_gpio_pin_is_ro(sc, pin))
458 		return (EINVAL);
459 
460 	bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
461 
462 	return (0);
463 }
464 
465 static int
466 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
467 {
468 	struct bcm_gpio_softc *sc = device_get_softc(dev);
469 	uint32_t bank, reg;
470 	int i;
471 
472 	for (i = 0; i < sc->sc_gpio_npins; i++) {
473 		if (sc->sc_gpio_pins[i].gp_pin == pin)
474 			break;
475 	}
476 	if (i >= sc->sc_gpio_npins)
477 		return (EINVAL);
478 	/* We never write to read-only/reserved pins. */
479 	if (bcm_gpio_pin_is_ro(sc, pin))
480 		return (EINVAL);
481 	BCM_GPIO_LOCK(sc);
482 	bank = BCM_GPIO_BANK(pin);
483 	if (value)
484 		reg = BCM_GPIO_GPSET(bank);
485 	else
486 		reg = BCM_GPIO_GPCLR(bank);
487 	BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));
488 	BCM_GPIO_UNLOCK(sc);
489 
490 	return (0);
491 }
492 
493 static int
494 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
495 {
496 	struct bcm_gpio_softc *sc = device_get_softc(dev);
497 	uint32_t bank, reg_data;
498 	int i;
499 
500 	for (i = 0; i < sc->sc_gpio_npins; i++) {
501 		if (sc->sc_gpio_pins[i].gp_pin == pin)
502 			break;
503 	}
504 	if (i >= sc->sc_gpio_npins)
505 		return (EINVAL);
506 	bank = BCM_GPIO_BANK(pin);
507 	BCM_GPIO_LOCK(sc);
508 	reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank));
509 	BCM_GPIO_UNLOCK(sc);
510 	*val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0;
511 
512 	return (0);
513 }
514 
515 static int
516 bcm_gpio_pin_toggle(device_t dev, uint32_t pin)
517 {
518 	struct bcm_gpio_softc *sc = device_get_softc(dev);
519 	uint32_t bank, data, reg;
520 	int i;
521 
522 	for (i = 0; i < sc->sc_gpio_npins; i++) {
523 		if (sc->sc_gpio_pins[i].gp_pin == pin)
524 			break;
525 	}
526 	if (i >= sc->sc_gpio_npins)
527 		return (EINVAL);
528 	/* We never write to read-only/reserved pins. */
529 	if (bcm_gpio_pin_is_ro(sc, pin))
530 		return (EINVAL);
531 	BCM_GPIO_LOCK(sc);
532 	bank = BCM_GPIO_BANK(pin);
533 	data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank));
534 	if (data & BCM_GPIO_MASK(pin))
535 		reg = BCM_GPIO_GPCLR(bank);
536 	else
537 		reg = BCM_GPIO_GPSET(bank);
538 	BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));
539 	BCM_GPIO_UNLOCK(sc);
540 
541 	return (0);
542 }
543 
544 static int
545 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS)
546 {
547 	char buf[16];
548 	struct bcm_gpio_softc *sc;
549 	struct bcm_gpio_sysctl *sc_sysctl;
550 	uint32_t nfunc;
551 	int error;
552 
553 	sc_sysctl = arg1;
554 	sc = sc_sysctl->sc;
555 
556 	/* Get the current pin function. */
557 	nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin);
558 	bcm_gpio_func_str(nfunc, buf, sizeof(buf));
559 
560 	error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
561 	if (error != 0 || req->newptr == NULL)
562 		return (error);
563 	/* Ignore changes on read-only pins. */
564 	if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin))
565 		return (0);
566 	/* Parse the user supplied string and check for a valid pin function. */
567 	if (bcm_gpio_str_func(buf, &nfunc) != 0)
568 		return (EINVAL);
569 
570 	/* Update the pin alternate function. */
571 	bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc);
572 
573 	return (0);
574 }
575 
576 static void
577 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc)
578 {
579 	char pinbuf[3];
580 	struct bcm_gpio_sysctl *sc_sysctl;
581 	struct sysctl_ctx_list *ctx;
582 	struct sysctl_oid *tree_node, *pin_node, *pinN_node;
583 	struct sysctl_oid_list *tree, *pin_tree, *pinN_tree;
584 	int i;
585 
586 	/*
587 	 * Add per-pin sysctl tree/handlers.
588 	 */
589 	ctx = device_get_sysctl_ctx(sc->sc_dev);
590  	tree_node = device_get_sysctl_tree(sc->sc_dev);
591  	tree = SYSCTL_CHILDREN(tree_node);
592 	pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin",
593 	    CTLFLAG_RD, NULL, "GPIO Pins");
594 	pin_tree = SYSCTL_CHILDREN(pin_node);
595 
596 	for (i = 0; i < sc->sc_gpio_npins; i++) {
597 
598 		snprintf(pinbuf, sizeof(pinbuf), "%d", i);
599 		pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf,
600 		    CTLFLAG_RD, NULL, "GPIO Pin");
601 		pinN_tree = SYSCTL_CHILDREN(pinN_node);
602 
603 		sc->sc_sysctl[i].sc = sc;
604 		sc_sysctl = &sc->sc_sysctl[i];
605 		sc_sysctl->sc = sc;
606 		sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin;
607 		SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function",
608 		    CTLFLAG_RW | CTLTYPE_STRING, sc_sysctl,
609 		    sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc,
610 		    "A", "Pin Function");
611 	}
612 }
613 
614 static int
615 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node,
616 	const char *propname, const char *label)
617 {
618 	int i, need_comma, npins, range_start, range_stop;
619 	pcell_t *pins;
620 
621 	/* Get the property data. */
622 	npins = OF_getencprop_alloc(node, propname, sizeof(*pins),
623 	    (void **)&pins);
624 	if (npins < 0)
625 		return (-1);
626 	if (npins == 0) {
627 		free(pins, M_OFWPROP);
628 		return (0);
629 	}
630 	for (i = 0; i < npins; i++)
631 		sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i];
632 	sc->sc_ro_npins += npins;
633 	need_comma = 0;
634 	device_printf(sc->sc_dev, "%s pins: ", label);
635 	range_start = range_stop = pins[0];
636 	for (i = 1; i < npins; i++) {
637 		if (pins[i] != range_stop + 1) {
638 			if (need_comma)
639 				printf(",");
640 			if (range_start != range_stop)
641 				printf("%d-%d", range_start, range_stop);
642 			else
643 				printf("%d", range_start);
644 			range_start = range_stop = pins[i];
645 			need_comma = 1;
646 		} else
647 			range_stop++;
648 	}
649 	if (need_comma)
650 		printf(",");
651 	if (range_start != range_stop)
652 		printf("%d-%d.\n", range_start, range_stop);
653 	else
654 		printf("%d.\n", range_start);
655 	free(pins, M_OFWPROP);
656 
657 	return (0);
658 }
659 
660 static int
661 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc)
662 {
663 	char *name;
664 	phandle_t gpio, node, reserved;
665 	ssize_t len;
666 
667 	/* Get read-only pins. */
668 	gpio = ofw_bus_get_node(sc->sc_dev);
669 	if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only",
670 	    "read-only") != 0)
671 		return (-1);
672 	/* Traverse the GPIO subnodes to find the reserved pins node. */
673 	reserved = 0;
674 	node = OF_child(gpio);
675 	while ((node != 0) && (reserved == 0)) {
676 		len = OF_getprop_alloc(node, "name", 1, (void **)&name);
677 		if (len == -1)
678 			return (-1);
679 		if (strcmp(name, "reserved") == 0)
680 			reserved = node;
681 		free(name, M_OFWPROP);
682 		node = OF_peer(node);
683 	}
684 	if (reserved == 0)
685 		return (-1);
686 	/* Get the reserved pins. */
687 	if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins",
688 	    "reserved") != 0)
689 		return (-1);
690 
691 	return (0);
692 }
693 
694 #ifndef INTRNG
695 static int
696 bcm_gpio_intr(void *arg)
697 {
698 	int bank_last, irq;
699 	struct bcm_gpio_softc *sc;
700 	struct intr_event *event;
701 	uint32_t bank, mask, reg;
702 
703 	sc = (struct bcm_gpio_softc *)arg;
704 	reg = 0;
705 	bank_last = -1;
706 	for (irq = 0; irq < BCM_GPIO_PINS; irq++) {
707 		bank = BCM_GPIO_BANK(irq);
708 		mask = BCM_GPIO_MASK(irq);
709 		if (bank != bank_last) {
710 			reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank));
711 			bank_last = bank;
712 		}
713 		if (reg & mask) {
714 			event = sc->sc_events[irq];
715 			if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers))
716 				intr_event_handle(event, NULL);
717 			else {
718 				device_printf(sc->sc_dev, "Stray IRQ %d\n",
719 				    irq);
720 			}
721 			/* Clear the Status bit by writing '1' to it. */
722 			BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), mask);
723 		}
724 	}
725 
726 	return (FILTER_HANDLED);
727 }
728 #endif
729 
730 static int
731 bcm_gpio_probe(device_t dev)
732 {
733 
734 	if (!ofw_bus_status_okay(dev))
735 		return (ENXIO);
736 
737 	if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-gpio"))
738 		return (ENXIO);
739 
740 	device_set_desc(dev, "BCM2708/2835 GPIO controller");
741 	return (BUS_PROBE_DEFAULT);
742 }
743 
744 #ifdef INTRNG
745 static int
746 bcm_gpio_intr_attach(device_t dev)
747 {
748 	struct bcm_gpio_softc *sc;
749 
750 	/*
751 	 *  Only first two interrupt lines are used. Third line is
752 	 *  mirrored second line and forth line is common for all banks.
753 	 */
754 	sc = device_get_softc(dev);
755 	if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL)
756 		return (-1);
757 
758 	if (bcm_gpio_pic_attach(sc) != 0) {
759 		device_printf(dev, "unable to attach PIC\n");
760 		return (-1);
761 	}
762 	if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE,
763 	    bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0)
764 		return (-1);
765 	if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE,
766 	    bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0)
767 		return (-1);
768 
769 	return (0);
770 }
771 
772 static void
773 bcm_gpio_intr_detach(device_t dev)
774 {
775 	struct bcm_gpio_softc *sc;
776 
777 	sc = device_get_softc(dev);
778 	if (sc->sc_intrhand[0] != NULL)
779 		bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]);
780 	if (sc->sc_intrhand[1] != NULL)
781 		bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]);
782 
783 	bcm_gpio_pic_detach(sc);
784 }
785 
786 #else
787 static int
788 bcm_gpio_intr_attach(device_t dev)
789 {
790 	struct bcm_gpio_softc *sc;
791 	int i;
792 
793 	sc = device_get_softc(dev);
794 	for (i = 0; i < BCM_GPIO_IRQS; i++) {
795 		if (bus_setup_intr(dev, sc->sc_res[i + 1],
796 		    INTR_TYPE_MISC | INTR_MPSAFE, bcm_gpio_intr,
797 		    NULL, sc, &sc->sc_intrhand[i]) != 0) {
798 			return (-1);
799 		}
800 	}
801 
802 	return (0);
803 }
804 
805 static void
806 bcm_gpio_intr_detach(device_t dev)
807 {
808 	struct bcm_gpio_softc *sc;
809 	int i;
810 
811 	sc = device_get_softc(dev);
812 	for (i = 0; i < BCM_GPIO_IRQS; i++) {
813 		if (sc->sc_intrhand[i]) {
814 			bus_teardown_intr(dev, sc->sc_res[i + 1],
815 			    sc->sc_intrhand[i]);
816 		}
817 	}
818 }
819 #endif
820 
821 static int
822 bcm_gpio_attach(device_t dev)
823 {
824 	int i, j;
825 	phandle_t gpio;
826 	struct bcm_gpio_softc *sc;
827 	uint32_t func;
828 
829 	if (bcm_gpio_sc != NULL)
830 		return (ENXIO);
831 
832 	bcm_gpio_sc = sc = device_get_softc(dev);
833  	sc->sc_dev = dev;
834 	mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN);
835 	if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) {
836 		device_printf(dev, "cannot allocate resources\n");
837 		goto fail;
838 	}
839 	sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
840 	sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
841 	/* Setup the GPIO interrupt handler. */
842 	if (bcm_gpio_intr_attach(dev)) {
843 		device_printf(dev, "unable to setup the gpio irq handler\n");
844 		goto fail;
845 	}
846 	/* Find our node. */
847 	gpio = ofw_bus_get_node(sc->sc_dev);
848 	if (!OF_hasprop(gpio, "gpio-controller"))
849 		/* Node is not a GPIO controller. */
850 		goto fail;
851 	/*
852 	 * Find the read-only pins.  These are pins we never touch or bad
853 	 * things could happen.
854 	 */
855 	if (bcm_gpio_get_reserved_pins(sc) == -1)
856 		goto fail;
857 	/* Initialize the software controlled pins. */
858 	for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) {
859 		snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME,
860 		    "pin %d", j);
861 		func = bcm_gpio_get_function(sc, j);
862 		sc->sc_gpio_pins[i].gp_pin = j;
863 		sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS;
864 		sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func);
865 #ifndef INTRNG
866 		/* The default is active-low interrupts. */
867 		sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL;
868 		sc->sc_irq_polarity[i] = INTR_POLARITY_LOW;
869 #endif
870 		i++;
871 	}
872 	sc->sc_gpio_npins = i;
873 	bcm_gpio_sysctl_init(sc);
874 	sc->sc_busdev = gpiobus_attach_bus(dev);
875 	if (sc->sc_busdev == NULL)
876 		goto fail;
877 
878 	return (0);
879 
880 fail:
881 	bcm_gpio_intr_detach(dev);
882 	bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res);
883 	mtx_destroy(&sc->sc_mtx);
884 
885 	return (ENXIO);
886 }
887 
888 static int
889 bcm_gpio_detach(device_t dev)
890 {
891 
892 	return (EBUSY);
893 }
894 
895 #ifdef INTRNG
896 static inline void
897 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
898 {
899 	uint32_t bank;
900 
901 	/* Write 1 to clear. */
902 	bank = BCM_GPIO_BANK(bgi->bgi_irq);
903 	BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask);
904 }
905 
906 static inline bool
907 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi)
908 {
909 	uint32_t bank;
910 
911 	bank = BCM_GPIO_BANK(bgi->bgi_irq);
912 	return (bgi->bgi_reg == BCM_GPIO_GPHEN(bank) ||
913 	    bgi->bgi_reg == BCM_GPIO_GPLEN(bank));
914 }
915 
916 static inline void
917 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
918 {
919 
920 	BCM_GPIO_LOCK(sc);
921 	BCM_GPIO_CLEAR_BITS(sc, bgi->bgi_reg, bgi->bgi_mask);
922 	BCM_GPIO_UNLOCK(bcm_gpio_sc);
923 }
924 
925 static inline void
926 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
927 {
928 
929 	BCM_GPIO_LOCK(sc);
930 	BCM_GPIO_SET_BITS(sc, bgi->bgi_reg, bgi->bgi_mask);
931 	BCM_GPIO_UNLOCK(sc);
932 }
933 
934 static int
935 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank)
936 {
937 	u_int irq;
938 	struct bcm_gpio_irqsrc *bgi;
939 	uint32_t reg;
940 
941 	/* Do not care of spurious interrupt on GPIO. */
942 	reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank));
943 	while (reg != 0) {
944 		irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1;
945 		bgi = sc->sc_isrcs + irq;
946 		if (!bcm_gpio_isrc_is_level(bgi))
947 			bcm_gpio_isrc_eoi(sc, bgi);
948 		if (intr_isrc_dispatch(&bgi->bgi_isrc,
949 		    curthread->td_intr_frame) != 0) {
950 			bcm_gpio_isrc_mask(sc, bgi);
951 			if (bcm_gpio_isrc_is_level(bgi))
952 				bcm_gpio_isrc_eoi(sc, bgi);
953 			device_printf(sc->sc_dev, "Stray irq %u disabled\n",
954 			    irq);
955 		}
956 		reg &= ~bgi->bgi_mask;
957 	}
958 	return (FILTER_HANDLED);
959 }
960 
961 static int
962 bcm_gpio_intr_bank0(void *arg)
963 {
964 
965 	return (bcm_gpio_intr_internal(arg, 0));
966 }
967 
968 static int
969 bcm_gpio_intr_bank1(void *arg)
970 {
971 
972 	return (bcm_gpio_intr_internal(arg, 1));
973 }
974 
975 static int
976 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc)
977 {
978 	int error;
979 	uint32_t irq;
980 	const char *name;
981 
982 	name = device_get_nameunit(sc->sc_dev);
983 	for (irq = 0; irq < BCM_GPIO_PINS; irq++) {
984 		sc->sc_isrcs[irq].bgi_irq = irq;
985 		sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq);
986 		sc->sc_isrcs[irq].bgi_reg = 0;
987 
988 		error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc,
989 		    sc->sc_dev, 0, "%s,%u", name, irq);
990 		if (error != 0)
991 			return (error); /* XXX deregister ISRCs */
992 	}
993 	return (intr_pic_register(sc->sc_dev,
994 	    OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))));
995 }
996 
997 static int
998 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc)
999 {
1000 
1001 	/*
1002 	 *  There has not been established any procedure yet
1003 	 *  how to detach PIC from living system correctly.
1004 	 */
1005 	device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__);
1006 	return (EBUSY);
1007 }
1008 
1009 static void
1010 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1011 {
1012 	struct bcm_gpio_softc *sc = device_get_softc(dev);
1013 	struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1014 
1015 	bcm_gpio_isrc_mask(sc, bgi);
1016 }
1017 
1018 static void
1019 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1020 {
1021 	struct bcm_gpio_softc *sc = device_get_softc(dev);
1022 	struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1023 
1024 	arm_irq_memory_barrier(bgi->bgi_irq);
1025 	bcm_gpio_isrc_unmask(sc, bgi);
1026 }
1027 
1028 static int
1029 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, u_int ncells, pcell_t *cells,
1030     u_int *irqp, uint32_t *regp)
1031 {
1032 	u_int irq;
1033 	uint32_t reg, bank;
1034 
1035 	/*
1036 	 * The first cell is the interrupt number.
1037 	 * The second cell is used to specify flags:
1038 	 *	bits[3:0] trigger type and level flags:
1039 	 *		1 = low-to-high edge triggered.
1040 	 *		2 = high-to-low edge triggered.
1041 	 *		4 = active high level-sensitive.
1042 	 *		8 = active low level-sensitive.
1043 	 */
1044 	if (ncells != 2)
1045 		return (EINVAL);
1046 
1047 	irq = cells[0];
1048 	if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq))
1049 		return (EINVAL);
1050 
1051 	/*
1052 	 * All interrupt types could be set for an interrupt at one moment.
1053 	 * At least, the combination of 'low-to-high' and 'high-to-low' edge
1054 	 * triggered interrupt types can make a sense. However, no combo is
1055 	 * supported now.
1056 	 */
1057 	bank = BCM_GPIO_BANK(irq);
1058 	if (cells[1] == 1)
1059 		reg = BCM_GPIO_GPREN(bank);
1060 	else if (cells[1] == 2)
1061 		reg = BCM_GPIO_GPFEN(bank);
1062 	else if (cells[1] == 4)
1063 		reg = BCM_GPIO_GPHEN(bank);
1064 	else if (cells[1] == 8)
1065 		reg = BCM_GPIO_GPLEN(bank);
1066 	else
1067 		return (EINVAL);
1068 
1069 	*irqp = irq;
1070 	if (regp != NULL)
1071 		*regp = reg;
1072 	return (0);
1073 }
1074 
1075 static int
1076 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
1077     struct intr_irqsrc **isrcp)
1078 {
1079 	int error;
1080 	u_int irq;
1081 	struct bcm_gpio_softc *sc;
1082 
1083 	if (data->type != INTR_MAP_DATA_FDT)
1084 		return (ENOTSUP);
1085 
1086 	sc = device_get_softc(dev);
1087 	error = bcm_gpio_pic_map_fdt(sc, data->fdt.ncells, data->fdt.cells,
1088 	    &irq, NULL);
1089 	if (error == 0)
1090 		*isrcp = &sc->sc_isrcs[irq].bgi_isrc;
1091 	return (error);
1092 }
1093 
1094 static void
1095 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1096 {
1097 	struct bcm_gpio_softc *sc = device_get_softc(dev);
1098 	struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1099 
1100 	if (bcm_gpio_isrc_is_level(bgi))
1101 		bcm_gpio_isrc_eoi(sc, bgi);
1102 }
1103 
1104 static void
1105 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1106 {
1107 
1108 	bcm_gpio_pic_enable_intr(dev, isrc);
1109 }
1110 
1111 static void
1112 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1113 {
1114 	struct bcm_gpio_softc *sc = device_get_softc(dev);
1115 	struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1116 
1117 	bcm_gpio_isrc_mask(sc, bgi);
1118 	if (bcm_gpio_isrc_is_level(bgi))
1119 		bcm_gpio_isrc_eoi(sc, bgi);
1120 }
1121 
1122 static int
1123 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1124     struct resource *res, struct intr_map_data *data)
1125 {
1126 	u_int irq;
1127 	uint32_t bank, reg;
1128 	struct bcm_gpio_softc *sc;
1129 	struct bcm_gpio_irqsrc *bgi;
1130 
1131 	if (data == NULL || data->type != INTR_MAP_DATA_FDT)
1132 		return (ENOTSUP);
1133 
1134 	sc = device_get_softc(dev);
1135 	bgi = (struct bcm_gpio_irqsrc *)isrc;
1136 
1137 	/* Get and check config for an interrupt. */
1138 	if (bcm_gpio_pic_map_fdt(sc, data->fdt.ncells, data->fdt.cells, &irq,
1139 	    &reg) != 0 || bgi->bgi_irq != irq)
1140 		return (EINVAL);
1141 
1142 	/*
1143 	 * If this is a setup for another handler,
1144 	 * only check that its configuration match.
1145 	 */
1146 	if (isrc->isrc_handlers != 0)
1147 		return (bgi->bgi_reg == reg ? 0 : EINVAL);
1148 
1149 	bank = BCM_GPIO_BANK(irq);
1150 	BCM_GPIO_LOCK(sc);
1151 	BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
1152 	BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
1153 	BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask);
1154 	BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask);
1155 	bgi->bgi_reg = reg;
1156 	BCM_GPIO_SET_BITS(sc, reg, bgi->bgi_mask);
1157 	BCM_GPIO_UNLOCK(sc);
1158 	return (0);
1159 }
1160 
1161 static int
1162 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1163     struct resource *res, struct intr_map_data *data)
1164 {
1165 	struct bcm_gpio_softc *sc = device_get_softc(dev);
1166 	struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1167 
1168 	if (isrc->isrc_handlers == 0) {
1169 		BCM_GPIO_LOCK(sc);
1170 		BCM_GPIO_CLEAR_BITS(sc, bgi->bgi_reg, bgi->bgi_mask);
1171 		bgi->bgi_reg = 0;
1172 		BCM_GPIO_UNLOCK(sc);
1173 	}
1174 	return (0);
1175 }
1176 
1177 #else
1178 static uint32_t
1179 bcm_gpio_intr_reg(struct bcm_gpio_softc *sc, unsigned int irq, uint32_t bank)
1180 {
1181 
1182 	if (irq > BCM_GPIO_PINS)
1183 		return (0);
1184 	if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) {
1185 		if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
1186 			return (BCM_GPIO_GPLEN(bank));
1187 		else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
1188 			return (BCM_GPIO_GPHEN(bank));
1189 	} else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) {
1190 		if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
1191 			return (BCM_GPIO_GPFEN(bank));
1192 		else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
1193 			return (BCM_GPIO_GPREN(bank));
1194 	}
1195 
1196 	return (0);
1197 }
1198 
1199 static void
1200 bcm_gpio_mask_irq(void *source)
1201 {
1202 	uint32_t bank, mask, reg;
1203 	unsigned int irq;
1204 
1205 	irq = (unsigned int)source;
1206 	if (irq > BCM_GPIO_PINS)
1207 		return;
1208 	if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq))
1209 		return;
1210 	bank = BCM_GPIO_BANK(irq);
1211 	mask = BCM_GPIO_MASK(irq);
1212 	BCM_GPIO_LOCK(bcm_gpio_sc);
1213 	reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank);
1214 	if (reg != 0)
1215 		BCM_GPIO_CLEAR_BITS(bcm_gpio_sc, reg, mask);
1216 	BCM_GPIO_UNLOCK(bcm_gpio_sc);
1217 }
1218 
1219 static void
1220 bcm_gpio_unmask_irq(void *source)
1221 {
1222 	uint32_t bank, mask, reg;
1223 	unsigned int irq;
1224 
1225 	irq = (unsigned int)source;
1226 	if (irq > BCM_GPIO_PINS)
1227 		return;
1228 	if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq))
1229 		return;
1230 	bank = BCM_GPIO_BANK(irq);
1231 	mask = BCM_GPIO_MASK(irq);
1232 	BCM_GPIO_LOCK(bcm_gpio_sc);
1233 	reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank);
1234 	if (reg != 0)
1235 		BCM_GPIO_SET_BITS(bcm_gpio_sc, reg, mask);
1236 	BCM_GPIO_UNLOCK(bcm_gpio_sc);
1237 }
1238 
1239 static int
1240 bcm_gpio_activate_resource(device_t bus, device_t child, int type, int rid,
1241 	struct resource *res)
1242 {
1243 	int pin;
1244 
1245 	if (type != SYS_RES_IRQ)
1246 		return (ENXIO);
1247 	/* Unmask the interrupt. */
1248 	pin = rman_get_start(res);
1249 	bcm_gpio_unmask_irq((void *)pin);
1250 
1251 	return (0);
1252 }
1253 
1254 static int
1255 bcm_gpio_deactivate_resource(device_t bus, device_t child, int type, int rid,
1256 	struct resource *res)
1257 {
1258 	int pin;
1259 
1260 	if (type != SYS_RES_IRQ)
1261 		return (ENXIO);
1262 	/* Mask the interrupt. */
1263 	pin = rman_get_start(res);
1264 	bcm_gpio_mask_irq((void *)pin);
1265 
1266 	return (0);
1267 }
1268 
1269 static int
1270 bcm_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig,
1271 	enum intr_polarity pol)
1272 {
1273 	int bank;
1274 	struct bcm_gpio_softc *sc;
1275 	uint32_t mask, oldreg, reg;
1276 
1277 	if (irq > BCM_GPIO_PINS)
1278 		return (EINVAL);
1279 	/* There is no standard trigger or polarity. */
1280 	if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
1281 		return (EINVAL);
1282 	sc = device_get_softc(dev);
1283 	if (bcm_gpio_pin_is_ro(sc, irq))
1284 		return (EINVAL);
1285 	bank = BCM_GPIO_BANK(irq);
1286 	mask = BCM_GPIO_MASK(irq);
1287 	BCM_GPIO_LOCK(sc);
1288 	oldreg = bcm_gpio_intr_reg(sc, irq, bank);
1289 	sc->sc_irq_trigger[irq] = trig;
1290 	sc->sc_irq_polarity[irq] = pol;
1291 	reg = bcm_gpio_intr_reg(sc, irq, bank);
1292 	if (reg != 0)
1293 		BCM_GPIO_SET_BITS(sc, reg, mask);
1294 	if (reg != oldreg && oldreg != 0)
1295 		BCM_GPIO_CLEAR_BITS(sc, oldreg, mask);
1296 	BCM_GPIO_UNLOCK(sc);
1297 
1298 	return (0);
1299 }
1300 
1301 static int
1302 bcm_gpio_setup_intr(device_t bus, device_t child, struct resource *ires,
1303 	int flags, driver_filter_t *filt, driver_intr_t *handler,
1304 	void *arg, void **cookiep)
1305 {
1306 	struct bcm_gpio_softc *sc;
1307 	struct intr_event *event;
1308 	int pin, error;
1309 
1310 	sc = device_get_softc(bus);
1311 	pin = rman_get_start(ires);
1312 	if (pin > BCM_GPIO_PINS)
1313 		panic("%s: bad pin %d", __func__, pin);
1314 	event = sc->sc_events[pin];
1315 	if (event == NULL) {
1316 		error = intr_event_create(&event, (void *)pin, 0, pin,
1317 		    bcm_gpio_mask_irq, bcm_gpio_unmask_irq, NULL, NULL,
1318 		    "gpio%d pin%d:", device_get_unit(bus), pin);
1319 		if (error != 0)
1320 			return (error);
1321 		sc->sc_events[pin] = event;
1322 	}
1323 	intr_event_add_handler(event, device_get_nameunit(child), filt,
1324 	    handler, arg, intr_priority(flags), flags, cookiep);
1325 
1326 	return (0);
1327 }
1328 
1329 static int
1330 bcm_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires,
1331 	void *cookie)
1332 {
1333 	struct bcm_gpio_softc *sc;
1334 	int pin, err;
1335 
1336 	sc = device_get_softc(dev);
1337 	pin = rman_get_start(ires);
1338 	if (pin > BCM_GPIO_PINS)
1339 		panic("%s: bad pin %d", __func__, pin);
1340 	if (sc->sc_events[pin] == NULL)
1341 		panic("Trying to teardown unoccupied IRQ");
1342 	err = intr_event_remove_handler(cookie);
1343 	if (!err)
1344 		sc->sc_events[pin] = NULL;
1345 
1346 	return (err);
1347 }
1348 #endif
1349 
1350 static phandle_t
1351 bcm_gpio_get_node(device_t bus, device_t dev)
1352 {
1353 
1354 	/* We only have one child, the GPIO bus, which needs our own node. */
1355 	return (ofw_bus_get_node(bus));
1356 }
1357 
1358 static device_method_t bcm_gpio_methods[] = {
1359 	/* Device interface */
1360 	DEVMETHOD(device_probe,		bcm_gpio_probe),
1361 	DEVMETHOD(device_attach,	bcm_gpio_attach),
1362 	DEVMETHOD(device_detach,	bcm_gpio_detach),
1363 
1364 	/* GPIO protocol */
1365 	DEVMETHOD(gpio_get_bus,		bcm_gpio_get_bus),
1366 	DEVMETHOD(gpio_pin_max,		bcm_gpio_pin_max),
1367 	DEVMETHOD(gpio_pin_getname,	bcm_gpio_pin_getname),
1368 	DEVMETHOD(gpio_pin_getflags,	bcm_gpio_pin_getflags),
1369 	DEVMETHOD(gpio_pin_getcaps,	bcm_gpio_pin_getcaps),
1370 	DEVMETHOD(gpio_pin_setflags,	bcm_gpio_pin_setflags),
1371 	DEVMETHOD(gpio_pin_get,		bcm_gpio_pin_get),
1372 	DEVMETHOD(gpio_pin_set,		bcm_gpio_pin_set),
1373 	DEVMETHOD(gpio_pin_toggle,	bcm_gpio_pin_toggle),
1374 
1375 #ifdef INTRNG
1376 	/* Interrupt controller interface */
1377 	DEVMETHOD(pic_disable_intr,	bcm_gpio_pic_disable_intr),
1378 	DEVMETHOD(pic_enable_intr,	bcm_gpio_pic_enable_intr),
1379 	DEVMETHOD(pic_map_intr,		bcm_gpio_pic_map_intr),
1380 	DEVMETHOD(pic_post_filter,	bcm_gpio_pic_post_filter),
1381 	DEVMETHOD(pic_post_ithread,	bcm_gpio_pic_post_ithread),
1382 	DEVMETHOD(pic_pre_ithread,	bcm_gpio_pic_pre_ithread),
1383 	DEVMETHOD(pic_setup_intr,	bcm_gpio_pic_setup_intr),
1384 	DEVMETHOD(pic_teardown_intr,	bcm_gpio_pic_teardown_intr),
1385 #else
1386 	/* Bus interface */
1387 	DEVMETHOD(bus_activate_resource,	bcm_gpio_activate_resource),
1388 	DEVMETHOD(bus_deactivate_resource,	bcm_gpio_deactivate_resource),
1389 	DEVMETHOD(bus_config_intr,	bcm_gpio_config_intr),
1390 	DEVMETHOD(bus_setup_intr,	bcm_gpio_setup_intr),
1391 	DEVMETHOD(bus_teardown_intr,	bcm_gpio_teardown_intr),
1392 #endif
1393 	/* ofw_bus interface */
1394 	DEVMETHOD(ofw_bus_get_node,	bcm_gpio_get_node),
1395 
1396 	DEVMETHOD_END
1397 };
1398 
1399 static devclass_t bcm_gpio_devclass;
1400 
1401 static driver_t bcm_gpio_driver = {
1402 	"gpio",
1403 	bcm_gpio_methods,
1404 	sizeof(struct bcm_gpio_softc),
1405 };
1406 
1407 DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, bcm_gpio_devclass, 0, 0);
1408