1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_platform.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/gpio.h> 37 #include <sys/interrupt.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/gpio/gpiobusvar.h> 50 #include <dev/ofw/ofw_bus.h> 51 52 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 53 54 #include "gpio_if.h" 55 56 #ifdef INTRNG 57 #include "pic_if.h" 58 #endif 59 60 #ifdef DEBUG 61 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 62 printf(fmt,##args); } while (0) 63 #else 64 #define dprintf(fmt, args...) 65 #endif 66 67 #define BCM_GPIO_IRQS 4 68 #define BCM_GPIO_PINS 54 69 #define BCM_GPIO_PINS_PER_BANK 32 70 71 #ifdef INTRNG 72 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 73 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | \ 74 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 75 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 76 #else 77 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 78 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) 79 #endif 80 81 static struct resource_spec bcm_gpio_res_spec[] = { 82 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 83 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */ 84 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */ 85 { SYS_RES_IRQ, 2, RF_ACTIVE }, /* bank 1 interrupt (mirrored) */ 86 { SYS_RES_IRQ, 3, RF_ACTIVE }, /* bank 0-1 interrupt (united) */ 87 { -1, 0, 0 } 88 }; 89 90 struct bcm_gpio_sysctl { 91 struct bcm_gpio_softc *sc; 92 uint32_t pin; 93 }; 94 95 #ifdef INTRNG 96 struct bcm_gpio_irqsrc { 97 struct intr_irqsrc bgi_isrc; 98 uint32_t bgi_irq; 99 uint32_t bgi_mode; 100 uint32_t bgi_mask; 101 }; 102 #endif 103 104 struct bcm_gpio_softc { 105 device_t sc_dev; 106 device_t sc_busdev; 107 struct mtx sc_mtx; 108 struct resource * sc_res[BCM_GPIO_IRQS + 1]; 109 bus_space_tag_t sc_bst; 110 bus_space_handle_t sc_bsh; 111 void * sc_intrhand[BCM_GPIO_IRQS]; 112 int sc_gpio_npins; 113 int sc_ro_npins; 114 int sc_ro_pins[BCM_GPIO_PINS]; 115 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS]; 116 #ifndef INTRNG 117 struct intr_event * sc_events[BCM_GPIO_PINS]; 118 #endif 119 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS]; 120 #ifdef INTRNG 121 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS]; 122 #else 123 enum intr_trigger sc_irq_trigger[BCM_GPIO_PINS]; 124 enum intr_polarity sc_irq_polarity[BCM_GPIO_PINS]; 125 #endif 126 }; 127 128 enum bcm_gpio_pud { 129 BCM_GPIO_NONE, 130 BCM_GPIO_PULLDOWN, 131 BCM_GPIO_PULLUP, 132 }; 133 134 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 135 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 136 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 137 #define BCM_GPIO_WRITE(_sc, _off, _val) \ 138 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val) 139 #define BCM_GPIO_READ(_sc, _off) \ 140 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off) 141 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \ 142 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits)) 143 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \ 144 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits) 145 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK) 146 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK)) 147 148 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */ 149 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */ 150 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */ 151 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */ 152 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */ 153 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */ 154 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */ 155 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */ 156 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */ 157 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */ 158 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */ 159 #define BCM_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */ 160 #define BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */ 161 162 static struct bcm_gpio_softc *bcm_gpio_sc = NULL; 163 164 #ifdef INTRNG 165 static int bcm_gpio_intr_bank0(void *arg); 166 static int bcm_gpio_intr_bank1(void *arg); 167 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc); 168 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc); 169 #endif 170 171 static int 172 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin) 173 { 174 int i; 175 176 for (i = 0; i < sc->sc_ro_npins; i++) 177 if (pin == sc->sc_ro_pins[i]) 178 return (1); 179 return (0); 180 } 181 182 static uint32_t 183 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin) 184 { 185 uint32_t bank, func, offset; 186 187 /* Five banks, 10 pins per bank, 3 bits per pin. */ 188 bank = pin / 10; 189 offset = (pin - bank * 10) * 3; 190 191 BCM_GPIO_LOCK(sc); 192 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7; 193 BCM_GPIO_UNLOCK(sc); 194 195 return (func); 196 } 197 198 static void 199 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize) 200 { 201 202 switch (nfunc) { 203 case BCM_GPIO_INPUT: 204 strncpy(buf, "input", bufsize); 205 break; 206 case BCM_GPIO_OUTPUT: 207 strncpy(buf, "output", bufsize); 208 break; 209 case BCM_GPIO_ALT0: 210 strncpy(buf, "alt0", bufsize); 211 break; 212 case BCM_GPIO_ALT1: 213 strncpy(buf, "alt1", bufsize); 214 break; 215 case BCM_GPIO_ALT2: 216 strncpy(buf, "alt2", bufsize); 217 break; 218 case BCM_GPIO_ALT3: 219 strncpy(buf, "alt3", bufsize); 220 break; 221 case BCM_GPIO_ALT4: 222 strncpy(buf, "alt4", bufsize); 223 break; 224 case BCM_GPIO_ALT5: 225 strncpy(buf, "alt5", bufsize); 226 break; 227 default: 228 strncpy(buf, "invalid", bufsize); 229 } 230 } 231 232 static int 233 bcm_gpio_str_func(char *func, uint32_t *nfunc) 234 { 235 236 if (strcasecmp(func, "input") == 0) 237 *nfunc = BCM_GPIO_INPUT; 238 else if (strcasecmp(func, "output") == 0) 239 *nfunc = BCM_GPIO_OUTPUT; 240 else if (strcasecmp(func, "alt0") == 0) 241 *nfunc = BCM_GPIO_ALT0; 242 else if (strcasecmp(func, "alt1") == 0) 243 *nfunc = BCM_GPIO_ALT1; 244 else if (strcasecmp(func, "alt2") == 0) 245 *nfunc = BCM_GPIO_ALT2; 246 else if (strcasecmp(func, "alt3") == 0) 247 *nfunc = BCM_GPIO_ALT3; 248 else if (strcasecmp(func, "alt4") == 0) 249 *nfunc = BCM_GPIO_ALT4; 250 else if (strcasecmp(func, "alt5") == 0) 251 *nfunc = BCM_GPIO_ALT5; 252 else 253 return (-1); 254 255 return (0); 256 } 257 258 static uint32_t 259 bcm_gpio_func_flag(uint32_t nfunc) 260 { 261 262 switch (nfunc) { 263 case BCM_GPIO_INPUT: 264 return (GPIO_PIN_INPUT); 265 case BCM_GPIO_OUTPUT: 266 return (GPIO_PIN_OUTPUT); 267 } 268 return (0); 269 } 270 271 static void 272 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f) 273 { 274 uint32_t bank, data, offset; 275 276 /* Must be called with lock held. */ 277 BCM_GPIO_LOCK_ASSERT(sc); 278 279 /* Five banks, 10 pins per bank, 3 bits per pin. */ 280 bank = pin / 10; 281 offset = (pin - bank * 10) * 3; 282 283 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)); 284 data &= ~(7 << offset); 285 data |= (f << offset); 286 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data); 287 } 288 289 static void 290 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state) 291 { 292 uint32_t bank; 293 294 /* Must be called with lock held. */ 295 BCM_GPIO_LOCK_ASSERT(sc); 296 297 bank = BCM_GPIO_BANK(pin); 298 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), state); 299 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin)); 300 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), 0); 301 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), 0); 302 } 303 304 void 305 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc) 306 { 307 struct bcm_gpio_softc *sc; 308 int i; 309 310 sc = device_get_softc(dev); 311 BCM_GPIO_LOCK(sc); 312 313 /* Disable pull-up or pull-down on pin. */ 314 bcm_gpio_set_pud(sc, pin, BCM_GPIO_NONE); 315 316 /* And now set the pin function. */ 317 bcm_gpio_set_function(sc, pin, nfunc); 318 319 /* Update the pin flags. */ 320 for (i = 0; i < sc->sc_gpio_npins; i++) { 321 if (sc->sc_gpio_pins[i].gp_pin == pin) 322 break; 323 } 324 if (i < sc->sc_gpio_npins) 325 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc); 326 327 BCM_GPIO_UNLOCK(sc); 328 } 329 330 static void 331 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin, 332 unsigned int flags) 333 { 334 335 BCM_GPIO_LOCK(sc); 336 337 /* 338 * Manage input/output. 339 */ 340 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 341 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); 342 if (flags & GPIO_PIN_OUTPUT) { 343 pin->gp_flags |= GPIO_PIN_OUTPUT; 344 bcm_gpio_set_function(sc, pin->gp_pin, 345 BCM_GPIO_OUTPUT); 346 } else { 347 pin->gp_flags |= GPIO_PIN_INPUT; 348 bcm_gpio_set_function(sc, pin->gp_pin, 349 BCM_GPIO_INPUT); 350 } 351 } 352 353 /* Manage Pull-up/pull-down. */ 354 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN); 355 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 356 if (flags & GPIO_PIN_PULLUP) { 357 pin->gp_flags |= GPIO_PIN_PULLUP; 358 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP); 359 } else { 360 pin->gp_flags |= GPIO_PIN_PULLDOWN; 361 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN); 362 } 363 } else 364 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE); 365 366 BCM_GPIO_UNLOCK(sc); 367 } 368 369 static device_t 370 bcm_gpio_get_bus(device_t dev) 371 { 372 struct bcm_gpio_softc *sc; 373 374 sc = device_get_softc(dev); 375 376 return (sc->sc_busdev); 377 } 378 379 static int 380 bcm_gpio_pin_max(device_t dev, int *maxpin) 381 { 382 383 *maxpin = BCM_GPIO_PINS - 1; 384 return (0); 385 } 386 387 static int 388 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 389 { 390 struct bcm_gpio_softc *sc = device_get_softc(dev); 391 int i; 392 393 for (i = 0; i < sc->sc_gpio_npins; i++) { 394 if (sc->sc_gpio_pins[i].gp_pin == pin) 395 break; 396 } 397 398 if (i >= sc->sc_gpio_npins) 399 return (EINVAL); 400 401 BCM_GPIO_LOCK(sc); 402 *caps = sc->sc_gpio_pins[i].gp_caps; 403 BCM_GPIO_UNLOCK(sc); 404 405 return (0); 406 } 407 408 static int 409 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 410 { 411 struct bcm_gpio_softc *sc = device_get_softc(dev); 412 int i; 413 414 for (i = 0; i < sc->sc_gpio_npins; i++) { 415 if (sc->sc_gpio_pins[i].gp_pin == pin) 416 break; 417 } 418 419 if (i >= sc->sc_gpio_npins) 420 return (EINVAL); 421 422 BCM_GPIO_LOCK(sc); 423 *flags = sc->sc_gpio_pins[i].gp_flags; 424 BCM_GPIO_UNLOCK(sc); 425 426 return (0); 427 } 428 429 static int 430 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 431 { 432 struct bcm_gpio_softc *sc = device_get_softc(dev); 433 int i; 434 435 for (i = 0; i < sc->sc_gpio_npins; i++) { 436 if (sc->sc_gpio_pins[i].gp_pin == pin) 437 break; 438 } 439 440 if (i >= sc->sc_gpio_npins) 441 return (EINVAL); 442 443 BCM_GPIO_LOCK(sc); 444 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME); 445 BCM_GPIO_UNLOCK(sc); 446 447 return (0); 448 } 449 450 static int 451 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 452 { 453 struct bcm_gpio_softc *sc = device_get_softc(dev); 454 int i; 455 456 for (i = 0; i < sc->sc_gpio_npins; i++) { 457 if (sc->sc_gpio_pins[i].gp_pin == pin) 458 break; 459 } 460 461 if (i >= sc->sc_gpio_npins) 462 return (EINVAL); 463 464 /* We never touch on read-only/reserved pins. */ 465 if (bcm_gpio_pin_is_ro(sc, pin)) 466 return (EINVAL); 467 468 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags); 469 470 return (0); 471 } 472 473 static int 474 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 475 { 476 struct bcm_gpio_softc *sc = device_get_softc(dev); 477 uint32_t bank, reg; 478 int i; 479 480 for (i = 0; i < sc->sc_gpio_npins; i++) { 481 if (sc->sc_gpio_pins[i].gp_pin == pin) 482 break; 483 } 484 if (i >= sc->sc_gpio_npins) 485 return (EINVAL); 486 /* We never write to read-only/reserved pins. */ 487 if (bcm_gpio_pin_is_ro(sc, pin)) 488 return (EINVAL); 489 BCM_GPIO_LOCK(sc); 490 bank = BCM_GPIO_BANK(pin); 491 if (value) 492 reg = BCM_GPIO_GPSET(bank); 493 else 494 reg = BCM_GPIO_GPCLR(bank); 495 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 496 BCM_GPIO_UNLOCK(sc); 497 498 return (0); 499 } 500 501 static int 502 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 503 { 504 struct bcm_gpio_softc *sc = device_get_softc(dev); 505 uint32_t bank, reg_data; 506 int i; 507 508 for (i = 0; i < sc->sc_gpio_npins; i++) { 509 if (sc->sc_gpio_pins[i].gp_pin == pin) 510 break; 511 } 512 if (i >= sc->sc_gpio_npins) 513 return (EINVAL); 514 bank = BCM_GPIO_BANK(pin); 515 BCM_GPIO_LOCK(sc); 516 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 517 BCM_GPIO_UNLOCK(sc); 518 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0; 519 520 return (0); 521 } 522 523 static int 524 bcm_gpio_pin_toggle(device_t dev, uint32_t pin) 525 { 526 struct bcm_gpio_softc *sc = device_get_softc(dev); 527 uint32_t bank, data, reg; 528 int i; 529 530 for (i = 0; i < sc->sc_gpio_npins; i++) { 531 if (sc->sc_gpio_pins[i].gp_pin == pin) 532 break; 533 } 534 if (i >= sc->sc_gpio_npins) 535 return (EINVAL); 536 /* We never write to read-only/reserved pins. */ 537 if (bcm_gpio_pin_is_ro(sc, pin)) 538 return (EINVAL); 539 BCM_GPIO_LOCK(sc); 540 bank = BCM_GPIO_BANK(pin); 541 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 542 if (data & BCM_GPIO_MASK(pin)) 543 reg = BCM_GPIO_GPCLR(bank); 544 else 545 reg = BCM_GPIO_GPSET(bank); 546 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 547 BCM_GPIO_UNLOCK(sc); 548 549 return (0); 550 } 551 552 static int 553 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS) 554 { 555 char buf[16]; 556 struct bcm_gpio_softc *sc; 557 struct bcm_gpio_sysctl *sc_sysctl; 558 uint32_t nfunc; 559 int error; 560 561 sc_sysctl = arg1; 562 sc = sc_sysctl->sc; 563 564 /* Get the current pin function. */ 565 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin); 566 bcm_gpio_func_str(nfunc, buf, sizeof(buf)); 567 568 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 569 if (error != 0 || req->newptr == NULL) 570 return (error); 571 /* Ignore changes on read-only pins. */ 572 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin)) 573 return (0); 574 /* Parse the user supplied string and check for a valid pin function. */ 575 if (bcm_gpio_str_func(buf, &nfunc) != 0) 576 return (EINVAL); 577 578 /* Update the pin alternate function. */ 579 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc); 580 581 return (0); 582 } 583 584 static void 585 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc) 586 { 587 char pinbuf[3]; 588 struct bcm_gpio_sysctl *sc_sysctl; 589 struct sysctl_ctx_list *ctx; 590 struct sysctl_oid *tree_node, *pin_node, *pinN_node; 591 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree; 592 int i; 593 594 /* 595 * Add per-pin sysctl tree/handlers. 596 */ 597 ctx = device_get_sysctl_ctx(sc->sc_dev); 598 tree_node = device_get_sysctl_tree(sc->sc_dev); 599 tree = SYSCTL_CHILDREN(tree_node); 600 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin", 601 CTLFLAG_RD, NULL, "GPIO Pins"); 602 pin_tree = SYSCTL_CHILDREN(pin_node); 603 604 for (i = 0; i < sc->sc_gpio_npins; i++) { 605 606 snprintf(pinbuf, sizeof(pinbuf), "%d", i); 607 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf, 608 CTLFLAG_RD, NULL, "GPIO Pin"); 609 pinN_tree = SYSCTL_CHILDREN(pinN_node); 610 611 sc->sc_sysctl[i].sc = sc; 612 sc_sysctl = &sc->sc_sysctl[i]; 613 sc_sysctl->sc = sc; 614 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin; 615 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function", 616 CTLFLAG_RW | CTLTYPE_STRING, sc_sysctl, 617 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc, 618 "A", "Pin Function"); 619 } 620 } 621 622 static int 623 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node, 624 const char *propname, const char *label) 625 { 626 int i, need_comma, npins, range_start, range_stop; 627 pcell_t *pins; 628 629 /* Get the property data. */ 630 npins = OF_getencprop_alloc(node, propname, sizeof(*pins), 631 (void **)&pins); 632 if (npins < 0) 633 return (-1); 634 if (npins == 0) { 635 OF_prop_free(pins); 636 return (0); 637 } 638 for (i = 0; i < npins; i++) 639 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i]; 640 sc->sc_ro_npins += npins; 641 need_comma = 0; 642 device_printf(sc->sc_dev, "%s pins: ", label); 643 range_start = range_stop = pins[0]; 644 for (i = 1; i < npins; i++) { 645 if (pins[i] != range_stop + 1) { 646 if (need_comma) 647 printf(","); 648 if (range_start != range_stop) 649 printf("%d-%d", range_start, range_stop); 650 else 651 printf("%d", range_start); 652 range_start = range_stop = pins[i]; 653 need_comma = 1; 654 } else 655 range_stop++; 656 } 657 if (need_comma) 658 printf(","); 659 if (range_start != range_stop) 660 printf("%d-%d.\n", range_start, range_stop); 661 else 662 printf("%d.\n", range_start); 663 OF_prop_free(pins); 664 665 return (0); 666 } 667 668 static int 669 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc) 670 { 671 char *name; 672 phandle_t gpio, node, reserved; 673 ssize_t len; 674 675 /* Get read-only pins. */ 676 gpio = ofw_bus_get_node(sc->sc_dev); 677 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only", 678 "read-only") != 0) 679 return (-1); 680 /* Traverse the GPIO subnodes to find the reserved pins node. */ 681 reserved = 0; 682 node = OF_child(gpio); 683 while ((node != 0) && (reserved == 0)) { 684 len = OF_getprop_alloc(node, "name", 1, (void **)&name); 685 if (len == -1) 686 return (-1); 687 if (strcmp(name, "reserved") == 0) 688 reserved = node; 689 OF_prop_free(name); 690 node = OF_peer(node); 691 } 692 if (reserved == 0) 693 return (-1); 694 /* Get the reserved pins. */ 695 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins", 696 "reserved") != 0) 697 return (-1); 698 699 return (0); 700 } 701 702 #ifndef INTRNG 703 static int 704 bcm_gpio_intr(void *arg) 705 { 706 int bank_last, irq; 707 struct bcm_gpio_softc *sc; 708 struct intr_event *event; 709 uint32_t bank, mask, reg; 710 711 sc = (struct bcm_gpio_softc *)arg; 712 reg = 0; 713 bank_last = -1; 714 for (irq = 0; irq < BCM_GPIO_PINS; irq++) { 715 bank = BCM_GPIO_BANK(irq); 716 mask = BCM_GPIO_MASK(irq); 717 if (bank != bank_last) { 718 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); 719 bank_last = bank; 720 } 721 if (reg & mask) { 722 event = sc->sc_events[irq]; 723 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers)) 724 intr_event_handle(event, NULL); 725 else { 726 device_printf(sc->sc_dev, "Stray IRQ %d\n", 727 irq); 728 } 729 /* Clear the Status bit by writing '1' to it. */ 730 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), mask); 731 } 732 } 733 734 return (FILTER_HANDLED); 735 } 736 #endif 737 738 static int 739 bcm_gpio_probe(device_t dev) 740 { 741 742 if (!ofw_bus_status_okay(dev)) 743 return (ENXIO); 744 745 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-gpio")) 746 return (ENXIO); 747 748 device_set_desc(dev, "BCM2708/2835 GPIO controller"); 749 return (BUS_PROBE_DEFAULT); 750 } 751 752 #ifdef INTRNG 753 static int 754 bcm_gpio_intr_attach(device_t dev) 755 { 756 struct bcm_gpio_softc *sc; 757 758 /* 759 * Only first two interrupt lines are used. Third line is 760 * mirrored second line and forth line is common for all banks. 761 */ 762 sc = device_get_softc(dev); 763 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL) 764 return (-1); 765 766 if (bcm_gpio_pic_attach(sc) != 0) { 767 device_printf(dev, "unable to attach PIC\n"); 768 return (-1); 769 } 770 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE, 771 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0) 772 return (-1); 773 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE, 774 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0) 775 return (-1); 776 777 return (0); 778 } 779 780 static void 781 bcm_gpio_intr_detach(device_t dev) 782 { 783 struct bcm_gpio_softc *sc; 784 785 sc = device_get_softc(dev); 786 if (sc->sc_intrhand[0] != NULL) 787 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]); 788 if (sc->sc_intrhand[1] != NULL) 789 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]); 790 791 bcm_gpio_pic_detach(sc); 792 } 793 794 #else 795 static int 796 bcm_gpio_intr_attach(device_t dev) 797 { 798 struct bcm_gpio_softc *sc; 799 int i; 800 801 sc = device_get_softc(dev); 802 for (i = 0; i < BCM_GPIO_IRQS; i++) { 803 if (bus_setup_intr(dev, sc->sc_res[i + 1], 804 INTR_TYPE_MISC | INTR_MPSAFE, bcm_gpio_intr, 805 NULL, sc, &sc->sc_intrhand[i]) != 0) { 806 return (-1); 807 } 808 } 809 810 return (0); 811 } 812 813 static void 814 bcm_gpio_intr_detach(device_t dev) 815 { 816 struct bcm_gpio_softc *sc; 817 int i; 818 819 sc = device_get_softc(dev); 820 for (i = 0; i < BCM_GPIO_IRQS; i++) { 821 if (sc->sc_intrhand[i]) { 822 bus_teardown_intr(dev, sc->sc_res[i + 1], 823 sc->sc_intrhand[i]); 824 } 825 } 826 } 827 #endif 828 829 static int 830 bcm_gpio_attach(device_t dev) 831 { 832 int i, j; 833 phandle_t gpio; 834 struct bcm_gpio_softc *sc; 835 uint32_t func; 836 837 if (bcm_gpio_sc != NULL) 838 return (ENXIO); 839 840 bcm_gpio_sc = sc = device_get_softc(dev); 841 sc->sc_dev = dev; 842 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN); 843 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) { 844 device_printf(dev, "cannot allocate resources\n"); 845 goto fail; 846 } 847 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 848 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 849 /* Setup the GPIO interrupt handler. */ 850 if (bcm_gpio_intr_attach(dev)) { 851 device_printf(dev, "unable to setup the gpio irq handler\n"); 852 goto fail; 853 } 854 /* Find our node. */ 855 gpio = ofw_bus_get_node(sc->sc_dev); 856 if (!OF_hasprop(gpio, "gpio-controller")) 857 /* Node is not a GPIO controller. */ 858 goto fail; 859 /* 860 * Find the read-only pins. These are pins we never touch or bad 861 * things could happen. 862 */ 863 if (bcm_gpio_get_reserved_pins(sc) == -1) 864 goto fail; 865 /* Initialize the software controlled pins. */ 866 for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) { 867 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, 868 "pin %d", j); 869 func = bcm_gpio_get_function(sc, j); 870 sc->sc_gpio_pins[i].gp_pin = j; 871 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS; 872 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func); 873 #ifndef INTRNG 874 /* The default is active-low interrupts. */ 875 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL; 876 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW; 877 #endif 878 i++; 879 } 880 sc->sc_gpio_npins = i; 881 bcm_gpio_sysctl_init(sc); 882 sc->sc_busdev = gpiobus_attach_bus(dev); 883 if (sc->sc_busdev == NULL) 884 goto fail; 885 886 return (0); 887 888 fail: 889 bcm_gpio_intr_detach(dev); 890 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res); 891 mtx_destroy(&sc->sc_mtx); 892 893 return (ENXIO); 894 } 895 896 static int 897 bcm_gpio_detach(device_t dev) 898 { 899 900 return (EBUSY); 901 } 902 903 #ifdef INTRNG 904 static inline void 905 bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask, 906 bool set_bits) 907 { 908 909 if (set_bits) 910 BCM_GPIO_SET_BITS(sc, reg, mask); 911 else 912 BCM_GPIO_CLEAR_BITS(sc, reg, mask); 913 } 914 915 static inline void 916 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 917 { 918 uint32_t bank; 919 920 /* Write 1 to clear. */ 921 bank = BCM_GPIO_BANK(bgi->bgi_irq); 922 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask); 923 } 924 925 static inline bool 926 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi) 927 { 928 929 return (bgi->bgi_mode == GPIO_INTR_LEVEL_LOW || 930 bgi->bgi_mode == GPIO_INTR_LEVEL_HIGH); 931 } 932 933 static inline void 934 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 935 { 936 uint32_t bank; 937 938 bank = BCM_GPIO_BANK(bgi->bgi_irq); 939 BCM_GPIO_LOCK(sc); 940 switch (bgi->bgi_mode) { 941 case GPIO_INTR_LEVEL_LOW: 942 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 943 break; 944 case GPIO_INTR_LEVEL_HIGH: 945 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 946 break; 947 case GPIO_INTR_EDGE_RISING: 948 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 949 break; 950 case GPIO_INTR_EDGE_FALLING: 951 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 952 break; 953 case GPIO_INTR_EDGE_BOTH: 954 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 955 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 956 break; 957 } 958 BCM_GPIO_UNLOCK(sc); 959 } 960 961 static inline void 962 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 963 { 964 uint32_t bank; 965 966 bank = BCM_GPIO_BANK(bgi->bgi_irq); 967 BCM_GPIO_LOCK(sc); 968 switch (bgi->bgi_mode) { 969 case GPIO_INTR_LEVEL_LOW: 970 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 971 break; 972 case GPIO_INTR_LEVEL_HIGH: 973 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 974 break; 975 case GPIO_INTR_EDGE_RISING: 976 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 977 break; 978 case GPIO_INTR_EDGE_FALLING: 979 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 980 break; 981 case GPIO_INTR_EDGE_BOTH: 982 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 983 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 984 break; 985 } 986 BCM_GPIO_UNLOCK(sc); 987 } 988 989 static int 990 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank) 991 { 992 u_int irq; 993 struct bcm_gpio_irqsrc *bgi; 994 uint32_t reg; 995 996 /* Do not care of spurious interrupt on GPIO. */ 997 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); 998 while (reg != 0) { 999 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1; 1000 bgi = sc->sc_isrcs + irq; 1001 if (!bcm_gpio_isrc_is_level(bgi)) 1002 bcm_gpio_isrc_eoi(sc, bgi); 1003 if (intr_isrc_dispatch(&bgi->bgi_isrc, 1004 curthread->td_intr_frame) != 0) { 1005 bcm_gpio_isrc_mask(sc, bgi); 1006 if (bcm_gpio_isrc_is_level(bgi)) 1007 bcm_gpio_isrc_eoi(sc, bgi); 1008 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 1009 irq); 1010 } 1011 reg &= ~bgi->bgi_mask; 1012 } 1013 return (FILTER_HANDLED); 1014 } 1015 1016 static int 1017 bcm_gpio_intr_bank0(void *arg) 1018 { 1019 1020 return (bcm_gpio_intr_internal(arg, 0)); 1021 } 1022 1023 static int 1024 bcm_gpio_intr_bank1(void *arg) 1025 { 1026 1027 return (bcm_gpio_intr_internal(arg, 1)); 1028 } 1029 1030 static int 1031 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc) 1032 { 1033 int error; 1034 uint32_t irq; 1035 const char *name; 1036 1037 name = device_get_nameunit(sc->sc_dev); 1038 for (irq = 0; irq < BCM_GPIO_PINS; irq++) { 1039 sc->sc_isrcs[irq].bgi_irq = irq; 1040 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq); 1041 sc->sc_isrcs[irq].bgi_mode = GPIO_INTR_CONFORM; 1042 1043 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc, 1044 sc->sc_dev, 0, "%s,%u", name, irq); 1045 if (error != 0) 1046 return (error); /* XXX deregister ISRCs */ 1047 } 1048 return (intr_pic_register(sc->sc_dev, 1049 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)))); 1050 } 1051 1052 static int 1053 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc) 1054 { 1055 1056 /* 1057 * There has not been established any procedure yet 1058 * how to detach PIC from living system correctly. 1059 */ 1060 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 1061 return (EBUSY); 1062 } 1063 1064 static void 1065 bcm_gpio_pic_config_intr(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi, 1066 uint32_t mode) 1067 { 1068 uint32_t bank; 1069 1070 bank = BCM_GPIO_BANK(bgi->bgi_irq); 1071 BCM_GPIO_LOCK(sc); 1072 bcm_gpio_modify(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask, 1073 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 1074 bcm_gpio_modify(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask, 1075 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 1076 bcm_gpio_modify(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask, 1077 mode == GPIO_INTR_LEVEL_HIGH); 1078 bcm_gpio_modify(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask, 1079 mode == GPIO_INTR_LEVEL_LOW); 1080 bgi->bgi_mode = mode; 1081 BCM_GPIO_UNLOCK(sc); 1082 } 1083 1084 static void 1085 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 1086 { 1087 struct bcm_gpio_softc *sc = device_get_softc(dev); 1088 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1089 1090 bcm_gpio_isrc_mask(sc, bgi); 1091 } 1092 1093 static void 1094 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 1095 { 1096 struct bcm_gpio_softc *sc = device_get_softc(dev); 1097 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1098 1099 arm_irq_memory_barrier(bgi->bgi_irq); 1100 bcm_gpio_isrc_unmask(sc, bgi); 1101 } 1102 1103 static int 1104 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf, 1105 u_int *irqp, uint32_t *modep) 1106 { 1107 u_int irq; 1108 uint32_t mode, bank; 1109 1110 /* 1111 * The first cell is the interrupt number. 1112 * The second cell is used to specify flags: 1113 * bits[3:0] trigger type and level flags: 1114 * 1 = low-to-high edge triggered. 1115 * 2 = high-to-low edge triggered. 1116 * 4 = active high level-sensitive. 1117 * 8 = active low level-sensitive. 1118 */ 1119 if (daf->ncells != 2) 1120 return (EINVAL); 1121 1122 irq = daf->cells[0]; 1123 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1124 return (EINVAL); 1125 1126 /* Only reasonable modes are supported. */ 1127 bank = BCM_GPIO_BANK(irq); 1128 if (daf->cells[1] == 1) 1129 mode = GPIO_INTR_EDGE_RISING; 1130 else if (daf->cells[1] == 2) 1131 mode = GPIO_INTR_EDGE_FALLING; 1132 else if (daf->cells[1] == 3) 1133 mode = GPIO_INTR_EDGE_BOTH; 1134 else if (daf->cells[1] == 4) 1135 mode = GPIO_INTR_LEVEL_HIGH; 1136 else if (daf->cells[1] == 8) 1137 mode = GPIO_INTR_LEVEL_LOW; 1138 else 1139 return (EINVAL); 1140 1141 *irqp = irq; 1142 if (modep != NULL) 1143 *modep = mode; 1144 return (0); 1145 } 1146 1147 static int 1148 bcm_gpio_pic_map_gpio(struct bcm_gpio_softc *sc, struct intr_map_data_gpio *dag, 1149 u_int *irqp, uint32_t *modep) 1150 { 1151 u_int irq; 1152 uint32_t mode; 1153 1154 irq = dag->gpio_pin_num; 1155 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1156 return (EINVAL); 1157 1158 mode = dag->gpio_intr_mode; 1159 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 1160 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 1161 mode != GPIO_INTR_EDGE_BOTH) 1162 return (EINVAL); 1163 1164 *irqp = irq; 1165 if (modep != NULL) 1166 *modep = mode; 1167 return (0); 1168 } 1169 1170 static int 1171 bcm_gpio_pic_map(struct bcm_gpio_softc *sc, struct intr_map_data *data, 1172 u_int *irqp, uint32_t *modep) 1173 { 1174 1175 switch (data->type) { 1176 case INTR_MAP_DATA_FDT: 1177 return (bcm_gpio_pic_map_fdt(sc, 1178 (struct intr_map_data_fdt *)data, irqp, modep)); 1179 case INTR_MAP_DATA_GPIO: 1180 return (bcm_gpio_pic_map_gpio(sc, 1181 (struct intr_map_data_gpio *)data, irqp, modep)); 1182 default: 1183 return (ENOTSUP); 1184 } 1185 } 1186 1187 static int 1188 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1189 struct intr_irqsrc **isrcp) 1190 { 1191 int error; 1192 u_int irq; 1193 struct bcm_gpio_softc *sc = device_get_softc(dev); 1194 1195 error = bcm_gpio_pic_map(sc, data, &irq, NULL); 1196 if (error == 0) 1197 *isrcp = &sc->sc_isrcs[irq].bgi_isrc; 1198 return (error); 1199 } 1200 1201 static void 1202 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1203 { 1204 struct bcm_gpio_softc *sc = device_get_softc(dev); 1205 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1206 1207 if (bcm_gpio_isrc_is_level(bgi)) 1208 bcm_gpio_isrc_eoi(sc, bgi); 1209 } 1210 1211 static void 1212 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1213 { 1214 1215 bcm_gpio_pic_enable_intr(dev, isrc); 1216 } 1217 1218 static void 1219 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1220 { 1221 struct bcm_gpio_softc *sc = device_get_softc(dev); 1222 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1223 1224 bcm_gpio_isrc_mask(sc, bgi); 1225 if (bcm_gpio_isrc_is_level(bgi)) 1226 bcm_gpio_isrc_eoi(sc, bgi); 1227 } 1228 1229 static int 1230 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1231 struct resource *res, struct intr_map_data *data) 1232 { 1233 u_int irq; 1234 uint32_t mode; 1235 struct bcm_gpio_softc *sc; 1236 struct bcm_gpio_irqsrc *bgi; 1237 1238 if (data == NULL) 1239 return (ENOTSUP); 1240 1241 sc = device_get_softc(dev); 1242 bgi = (struct bcm_gpio_irqsrc *)isrc; 1243 1244 /* Get and check config for an interrupt. */ 1245 if (bcm_gpio_pic_map(sc, data, &irq, &mode) != 0 || bgi->bgi_irq != irq) 1246 return (EINVAL); 1247 1248 /* 1249 * If this is a setup for another handler, 1250 * only check that its configuration match. 1251 */ 1252 if (isrc->isrc_handlers != 0) 1253 return (bgi->bgi_mode == mode ? 0 : EINVAL); 1254 1255 bcm_gpio_pic_config_intr(sc, bgi, mode); 1256 return (0); 1257 } 1258 1259 static int 1260 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1261 struct resource *res, struct intr_map_data *data) 1262 { 1263 struct bcm_gpio_softc *sc = device_get_softc(dev); 1264 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1265 1266 if (isrc->isrc_handlers == 0) 1267 bcm_gpio_pic_config_intr(sc, bgi, GPIO_INTR_CONFORM); 1268 return (0); 1269 } 1270 1271 #else 1272 static uint32_t 1273 bcm_gpio_intr_reg(struct bcm_gpio_softc *sc, unsigned int irq, uint32_t bank) 1274 { 1275 1276 if (irq > BCM_GPIO_PINS) 1277 return (0); 1278 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) { 1279 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1280 return (BCM_GPIO_GPLEN(bank)); 1281 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1282 return (BCM_GPIO_GPHEN(bank)); 1283 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) { 1284 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1285 return (BCM_GPIO_GPFEN(bank)); 1286 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1287 return (BCM_GPIO_GPREN(bank)); 1288 } 1289 1290 return (0); 1291 } 1292 1293 static void 1294 bcm_gpio_mask_irq(void *source) 1295 { 1296 uint32_t bank, mask, reg; 1297 unsigned int irq; 1298 1299 irq = (unsigned int)source; 1300 if (irq > BCM_GPIO_PINS) 1301 return; 1302 if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq)) 1303 return; 1304 bank = BCM_GPIO_BANK(irq); 1305 mask = BCM_GPIO_MASK(irq); 1306 BCM_GPIO_LOCK(bcm_gpio_sc); 1307 reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank); 1308 if (reg != 0) 1309 BCM_GPIO_CLEAR_BITS(bcm_gpio_sc, reg, mask); 1310 BCM_GPIO_UNLOCK(bcm_gpio_sc); 1311 } 1312 1313 static void 1314 bcm_gpio_unmask_irq(void *source) 1315 { 1316 uint32_t bank, mask, reg; 1317 unsigned int irq; 1318 1319 irq = (unsigned int)source; 1320 if (irq > BCM_GPIO_PINS) 1321 return; 1322 if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq)) 1323 return; 1324 bank = BCM_GPIO_BANK(irq); 1325 mask = BCM_GPIO_MASK(irq); 1326 BCM_GPIO_LOCK(bcm_gpio_sc); 1327 reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank); 1328 if (reg != 0) 1329 BCM_GPIO_SET_BITS(bcm_gpio_sc, reg, mask); 1330 BCM_GPIO_UNLOCK(bcm_gpio_sc); 1331 } 1332 1333 static int 1334 bcm_gpio_activate_resource(device_t bus, device_t child, int type, int rid, 1335 struct resource *res) 1336 { 1337 int pin; 1338 1339 if (type != SYS_RES_IRQ) 1340 return (ENXIO); 1341 /* Unmask the interrupt. */ 1342 pin = rman_get_start(res); 1343 bcm_gpio_unmask_irq((void *)pin); 1344 1345 return (0); 1346 } 1347 1348 static int 1349 bcm_gpio_deactivate_resource(device_t bus, device_t child, int type, int rid, 1350 struct resource *res) 1351 { 1352 int pin; 1353 1354 if (type != SYS_RES_IRQ) 1355 return (ENXIO); 1356 /* Mask the interrupt. */ 1357 pin = rman_get_start(res); 1358 bcm_gpio_mask_irq((void *)pin); 1359 1360 return (0); 1361 } 1362 1363 static int 1364 bcm_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, 1365 enum intr_polarity pol) 1366 { 1367 int bank; 1368 struct bcm_gpio_softc *sc; 1369 uint32_t mask, oldreg, reg; 1370 1371 if (irq > BCM_GPIO_PINS) 1372 return (EINVAL); 1373 /* There is no standard trigger or polarity. */ 1374 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) 1375 return (EINVAL); 1376 sc = device_get_softc(dev); 1377 if (bcm_gpio_pin_is_ro(sc, irq)) 1378 return (EINVAL); 1379 bank = BCM_GPIO_BANK(irq); 1380 mask = BCM_GPIO_MASK(irq); 1381 BCM_GPIO_LOCK(sc); 1382 oldreg = bcm_gpio_intr_reg(sc, irq, bank); 1383 sc->sc_irq_trigger[irq] = trig; 1384 sc->sc_irq_polarity[irq] = pol; 1385 reg = bcm_gpio_intr_reg(sc, irq, bank); 1386 if (reg != 0) 1387 BCM_GPIO_SET_BITS(sc, reg, mask); 1388 if (reg != oldreg && oldreg != 0) 1389 BCM_GPIO_CLEAR_BITS(sc, oldreg, mask); 1390 BCM_GPIO_UNLOCK(sc); 1391 1392 return (0); 1393 } 1394 1395 static int 1396 bcm_gpio_setup_intr(device_t bus, device_t child, struct resource *ires, 1397 int flags, driver_filter_t *filt, driver_intr_t *handler, 1398 void *arg, void **cookiep) 1399 { 1400 struct bcm_gpio_softc *sc; 1401 struct intr_event *event; 1402 int pin, error; 1403 1404 sc = device_get_softc(bus); 1405 pin = rman_get_start(ires); 1406 if (pin > BCM_GPIO_PINS) 1407 panic("%s: bad pin %d", __func__, pin); 1408 event = sc->sc_events[pin]; 1409 if (event == NULL) { 1410 error = intr_event_create(&event, (void *)pin, 0, pin, 1411 bcm_gpio_mask_irq, bcm_gpio_unmask_irq, NULL, NULL, 1412 "gpio%d pin%d:", device_get_unit(bus), pin); 1413 if (error != 0) 1414 return (error); 1415 sc->sc_events[pin] = event; 1416 } 1417 intr_event_add_handler(event, device_get_nameunit(child), filt, 1418 handler, arg, intr_priority(flags), flags, cookiep); 1419 1420 return (0); 1421 } 1422 1423 static int 1424 bcm_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires, 1425 void *cookie) 1426 { 1427 struct bcm_gpio_softc *sc; 1428 int pin, err; 1429 1430 sc = device_get_softc(dev); 1431 pin = rman_get_start(ires); 1432 if (pin > BCM_GPIO_PINS) 1433 panic("%s: bad pin %d", __func__, pin); 1434 if (sc->sc_events[pin] == NULL) 1435 panic("Trying to teardown unoccupied IRQ"); 1436 err = intr_event_remove_handler(cookie); 1437 if (!err) 1438 sc->sc_events[pin] = NULL; 1439 1440 return (err); 1441 } 1442 #endif 1443 1444 static phandle_t 1445 bcm_gpio_get_node(device_t bus, device_t dev) 1446 { 1447 1448 /* We only have one child, the GPIO bus, which needs our own node. */ 1449 return (ofw_bus_get_node(bus)); 1450 } 1451 1452 static device_method_t bcm_gpio_methods[] = { 1453 /* Device interface */ 1454 DEVMETHOD(device_probe, bcm_gpio_probe), 1455 DEVMETHOD(device_attach, bcm_gpio_attach), 1456 DEVMETHOD(device_detach, bcm_gpio_detach), 1457 1458 /* GPIO protocol */ 1459 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus), 1460 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max), 1461 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname), 1462 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags), 1463 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps), 1464 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags), 1465 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get), 1466 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set), 1467 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle), 1468 1469 #ifdef INTRNG 1470 /* Interrupt controller interface */ 1471 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr), 1472 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr), 1473 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr), 1474 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter), 1475 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread), 1476 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread), 1477 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr), 1478 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr), 1479 #else 1480 /* Bus interface */ 1481 DEVMETHOD(bus_activate_resource, bcm_gpio_activate_resource), 1482 DEVMETHOD(bus_deactivate_resource, bcm_gpio_deactivate_resource), 1483 DEVMETHOD(bus_config_intr, bcm_gpio_config_intr), 1484 DEVMETHOD(bus_setup_intr, bcm_gpio_setup_intr), 1485 DEVMETHOD(bus_teardown_intr, bcm_gpio_teardown_intr), 1486 #endif 1487 /* ofw_bus interface */ 1488 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node), 1489 1490 DEVMETHOD_END 1491 }; 1492 1493 static devclass_t bcm_gpio_devclass; 1494 1495 static driver_t bcm_gpio_driver = { 1496 "gpio", 1497 bcm_gpio_methods, 1498 sizeof(struct bcm_gpio_softc), 1499 }; 1500 1501 DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, bcm_gpio_devclass, 0, 0); 1502