1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_platform.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/gpio.h> 39 #include <sys/interrupt.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/proc.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/fdt/fdt_pinctrl.h> 52 #include <dev/gpio/gpiobusvar.h> 53 #include <dev/ofw/ofw_bus.h> 54 55 #include "gpio_if.h" 56 57 #include "pic_if.h" 58 59 #ifdef DEBUG 60 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 61 printf(fmt,##args); } while (0) 62 #else 63 #define dprintf(fmt, args...) 64 #endif 65 66 #define BCM_GPIO_IRQS 4 67 #define BCM_GPIO_PINS 54 68 #define BCM_GPIO_PINS_PER_BANK 32 69 70 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 71 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | \ 72 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 73 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 74 75 #define BCM2835_FSEL_GPIO_IN 0 76 #define BCM2835_FSEL_GPIO_OUT 1 77 #define BCM2835_FSEL_ALT5 2 78 #define BCM2835_FSEL_ALT4 3 79 #define BCM2835_FSEL_ALT0 4 80 #define BCM2835_FSEL_ALT1 5 81 #define BCM2835_FSEL_ALT2 6 82 #define BCM2835_FSEL_ALT3 7 83 84 #define BCM2835_PUD_OFF 0 85 #define BCM2835_PUD_DOWN 1 86 #define BCM2835_PUD_UP 2 87 88 static struct resource_spec bcm_gpio_res_spec[] = { 89 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 90 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */ 91 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */ 92 { -1, 0, 0 } 93 }; 94 95 struct bcm_gpio_sysctl { 96 struct bcm_gpio_softc *sc; 97 uint32_t pin; 98 }; 99 100 struct bcm_gpio_irqsrc { 101 struct intr_irqsrc bgi_isrc; 102 uint32_t bgi_irq; 103 uint32_t bgi_mode; 104 uint32_t bgi_mask; 105 }; 106 107 struct bcm_gpio_softc { 108 device_t sc_dev; 109 device_t sc_busdev; 110 struct mtx sc_mtx; 111 struct resource * sc_res[BCM_GPIO_IRQS + 1]; 112 bus_space_tag_t sc_bst; 113 bus_space_handle_t sc_bsh; 114 void * sc_intrhand[BCM_GPIO_IRQS]; 115 int sc_gpio_npins; 116 int sc_ro_npins; 117 int sc_ro_pins[BCM_GPIO_PINS]; 118 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS]; 119 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS]; 120 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS]; 121 }; 122 123 enum bcm_gpio_pud { 124 BCM_GPIO_NONE, 125 BCM_GPIO_PULLDOWN, 126 BCM_GPIO_PULLUP, 127 }; 128 129 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 130 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 131 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 132 #define BCM_GPIO_WRITE(_sc, _off, _val) \ 133 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val) 134 #define BCM_GPIO_READ(_sc, _off) \ 135 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off) 136 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \ 137 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits)) 138 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \ 139 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits) 140 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK) 141 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK)) 142 143 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */ 144 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */ 145 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */ 146 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */ 147 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */ 148 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */ 149 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */ 150 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */ 151 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */ 152 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */ 153 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */ 154 #define BCM_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */ 155 #define BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */ 156 157 static struct ofw_compat_data compat_data[] = { 158 {"broadcom,bcm2835-gpio", 1}, 159 {"brcm,bcm2835-gpio", 1}, 160 {NULL, 0} 161 }; 162 163 static struct bcm_gpio_softc *bcm_gpio_sc = NULL; 164 165 static int bcm_gpio_intr_bank0(void *arg); 166 static int bcm_gpio_intr_bank1(void *arg); 167 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc); 168 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc); 169 170 static int 171 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin) 172 { 173 int i; 174 175 for (i = 0; i < sc->sc_ro_npins; i++) 176 if (pin == sc->sc_ro_pins[i]) 177 return (1); 178 return (0); 179 } 180 181 static uint32_t 182 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin) 183 { 184 uint32_t bank, func, offset; 185 186 /* Five banks, 10 pins per bank, 3 bits per pin. */ 187 bank = pin / 10; 188 offset = (pin - bank * 10) * 3; 189 190 BCM_GPIO_LOCK(sc); 191 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7; 192 BCM_GPIO_UNLOCK(sc); 193 194 return (func); 195 } 196 197 static void 198 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize) 199 { 200 201 switch (nfunc) { 202 case BCM2835_FSEL_GPIO_IN: 203 strncpy(buf, "input", bufsize); 204 break; 205 case BCM2835_FSEL_GPIO_OUT: 206 strncpy(buf, "output", bufsize); 207 break; 208 case BCM2835_FSEL_ALT0: 209 strncpy(buf, "alt0", bufsize); 210 break; 211 case BCM2835_FSEL_ALT1: 212 strncpy(buf, "alt1", bufsize); 213 break; 214 case BCM2835_FSEL_ALT2: 215 strncpy(buf, "alt2", bufsize); 216 break; 217 case BCM2835_FSEL_ALT3: 218 strncpy(buf, "alt3", bufsize); 219 break; 220 case BCM2835_FSEL_ALT4: 221 strncpy(buf, "alt4", bufsize); 222 break; 223 case BCM2835_FSEL_ALT5: 224 strncpy(buf, "alt5", bufsize); 225 break; 226 default: 227 strncpy(buf, "invalid", bufsize); 228 } 229 } 230 231 static int 232 bcm_gpio_str_func(char *func, uint32_t *nfunc) 233 { 234 235 if (strcasecmp(func, "input") == 0) 236 *nfunc = BCM2835_FSEL_GPIO_IN; 237 else if (strcasecmp(func, "output") == 0) 238 *nfunc = BCM2835_FSEL_GPIO_OUT; 239 else if (strcasecmp(func, "alt0") == 0) 240 *nfunc = BCM2835_FSEL_ALT0; 241 else if (strcasecmp(func, "alt1") == 0) 242 *nfunc = BCM2835_FSEL_ALT1; 243 else if (strcasecmp(func, "alt2") == 0) 244 *nfunc = BCM2835_FSEL_ALT2; 245 else if (strcasecmp(func, "alt3") == 0) 246 *nfunc = BCM2835_FSEL_ALT3; 247 else if (strcasecmp(func, "alt4") == 0) 248 *nfunc = BCM2835_FSEL_ALT4; 249 else if (strcasecmp(func, "alt5") == 0) 250 *nfunc = BCM2835_FSEL_ALT5; 251 else 252 return (-1); 253 254 return (0); 255 } 256 257 static uint32_t 258 bcm_gpio_func_flag(uint32_t nfunc) 259 { 260 261 switch (nfunc) { 262 case BCM2835_FSEL_GPIO_IN: 263 return (GPIO_PIN_INPUT); 264 case BCM2835_FSEL_GPIO_OUT: 265 return (GPIO_PIN_OUTPUT); 266 } 267 return (0); 268 } 269 270 static void 271 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f) 272 { 273 uint32_t bank, data, offset; 274 275 /* Must be called with lock held. */ 276 BCM_GPIO_LOCK_ASSERT(sc); 277 278 /* Five banks, 10 pins per bank, 3 bits per pin. */ 279 bank = pin / 10; 280 offset = (pin - bank * 10) * 3; 281 282 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)); 283 data &= ~(7 << offset); 284 data |= (f << offset); 285 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data); 286 } 287 288 static void 289 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state) 290 { 291 uint32_t bank; 292 293 /* Must be called with lock held. */ 294 BCM_GPIO_LOCK_ASSERT(sc); 295 296 bank = BCM_GPIO_BANK(pin); 297 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), state); 298 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin)); 299 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), 0); 300 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), 0); 301 } 302 303 static void 304 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc) 305 { 306 struct bcm_gpio_softc *sc; 307 int i; 308 309 sc = device_get_softc(dev); 310 BCM_GPIO_LOCK(sc); 311 312 /* Set the pin function. */ 313 bcm_gpio_set_function(sc, pin, nfunc); 314 315 /* Update the pin flags. */ 316 for (i = 0; i < sc->sc_gpio_npins; i++) { 317 if (sc->sc_gpio_pins[i].gp_pin == pin) 318 break; 319 } 320 if (i < sc->sc_gpio_npins) 321 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc); 322 323 BCM_GPIO_UNLOCK(sc); 324 } 325 326 static void 327 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin, 328 unsigned int flags) 329 { 330 331 BCM_GPIO_LOCK(sc); 332 333 /* 334 * Manage input/output. 335 */ 336 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 337 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); 338 if (flags & GPIO_PIN_OUTPUT) { 339 pin->gp_flags |= GPIO_PIN_OUTPUT; 340 bcm_gpio_set_function(sc, pin->gp_pin, 341 BCM2835_FSEL_GPIO_OUT); 342 } else { 343 pin->gp_flags |= GPIO_PIN_INPUT; 344 bcm_gpio_set_function(sc, pin->gp_pin, 345 BCM2835_FSEL_GPIO_IN); 346 } 347 } 348 349 /* Manage Pull-up/pull-down. */ 350 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN); 351 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 352 if (flags & GPIO_PIN_PULLUP) { 353 pin->gp_flags |= GPIO_PIN_PULLUP; 354 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP); 355 } else { 356 pin->gp_flags |= GPIO_PIN_PULLDOWN; 357 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN); 358 } 359 } else 360 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE); 361 362 BCM_GPIO_UNLOCK(sc); 363 } 364 365 static device_t 366 bcm_gpio_get_bus(device_t dev) 367 { 368 struct bcm_gpio_softc *sc; 369 370 sc = device_get_softc(dev); 371 372 return (sc->sc_busdev); 373 } 374 375 static int 376 bcm_gpio_pin_max(device_t dev, int *maxpin) 377 { 378 379 *maxpin = BCM_GPIO_PINS - 1; 380 return (0); 381 } 382 383 static int 384 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 385 { 386 struct bcm_gpio_softc *sc = device_get_softc(dev); 387 int i; 388 389 for (i = 0; i < sc->sc_gpio_npins; i++) { 390 if (sc->sc_gpio_pins[i].gp_pin == pin) 391 break; 392 } 393 394 if (i >= sc->sc_gpio_npins) 395 return (EINVAL); 396 397 BCM_GPIO_LOCK(sc); 398 *caps = sc->sc_gpio_pins[i].gp_caps; 399 BCM_GPIO_UNLOCK(sc); 400 401 return (0); 402 } 403 404 static int 405 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 406 { 407 struct bcm_gpio_softc *sc = device_get_softc(dev); 408 int i; 409 410 for (i = 0; i < sc->sc_gpio_npins; i++) { 411 if (sc->sc_gpio_pins[i].gp_pin == pin) 412 break; 413 } 414 415 if (i >= sc->sc_gpio_npins) 416 return (EINVAL); 417 418 BCM_GPIO_LOCK(sc); 419 *flags = sc->sc_gpio_pins[i].gp_flags; 420 BCM_GPIO_UNLOCK(sc); 421 422 return (0); 423 } 424 425 static int 426 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 427 { 428 struct bcm_gpio_softc *sc = device_get_softc(dev); 429 int i; 430 431 for (i = 0; i < sc->sc_gpio_npins; i++) { 432 if (sc->sc_gpio_pins[i].gp_pin == pin) 433 break; 434 } 435 436 if (i >= sc->sc_gpio_npins) 437 return (EINVAL); 438 439 BCM_GPIO_LOCK(sc); 440 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME); 441 BCM_GPIO_UNLOCK(sc); 442 443 return (0); 444 } 445 446 static int 447 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 448 { 449 struct bcm_gpio_softc *sc = device_get_softc(dev); 450 int i; 451 452 for (i = 0; i < sc->sc_gpio_npins; i++) { 453 if (sc->sc_gpio_pins[i].gp_pin == pin) 454 break; 455 } 456 457 if (i >= sc->sc_gpio_npins) 458 return (EINVAL); 459 460 /* We never touch on read-only/reserved pins. */ 461 if (bcm_gpio_pin_is_ro(sc, pin)) 462 return (EINVAL); 463 464 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags); 465 466 return (0); 467 } 468 469 static int 470 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 471 { 472 struct bcm_gpio_softc *sc = device_get_softc(dev); 473 uint32_t bank, reg; 474 int i; 475 476 for (i = 0; i < sc->sc_gpio_npins; i++) { 477 if (sc->sc_gpio_pins[i].gp_pin == pin) 478 break; 479 } 480 if (i >= sc->sc_gpio_npins) 481 return (EINVAL); 482 /* We never write to read-only/reserved pins. */ 483 if (bcm_gpio_pin_is_ro(sc, pin)) 484 return (EINVAL); 485 BCM_GPIO_LOCK(sc); 486 bank = BCM_GPIO_BANK(pin); 487 if (value) 488 reg = BCM_GPIO_GPSET(bank); 489 else 490 reg = BCM_GPIO_GPCLR(bank); 491 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 492 BCM_GPIO_UNLOCK(sc); 493 494 return (0); 495 } 496 497 static int 498 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 499 { 500 struct bcm_gpio_softc *sc = device_get_softc(dev); 501 uint32_t bank, reg_data; 502 int i; 503 504 for (i = 0; i < sc->sc_gpio_npins; i++) { 505 if (sc->sc_gpio_pins[i].gp_pin == pin) 506 break; 507 } 508 if (i >= sc->sc_gpio_npins) 509 return (EINVAL); 510 bank = BCM_GPIO_BANK(pin); 511 BCM_GPIO_LOCK(sc); 512 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 513 BCM_GPIO_UNLOCK(sc); 514 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0; 515 516 return (0); 517 } 518 519 static int 520 bcm_gpio_pin_toggle(device_t dev, uint32_t pin) 521 { 522 struct bcm_gpio_softc *sc = device_get_softc(dev); 523 uint32_t bank, data, reg; 524 int i; 525 526 for (i = 0; i < sc->sc_gpio_npins; i++) { 527 if (sc->sc_gpio_pins[i].gp_pin == pin) 528 break; 529 } 530 if (i >= sc->sc_gpio_npins) 531 return (EINVAL); 532 /* We never write to read-only/reserved pins. */ 533 if (bcm_gpio_pin_is_ro(sc, pin)) 534 return (EINVAL); 535 BCM_GPIO_LOCK(sc); 536 bank = BCM_GPIO_BANK(pin); 537 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 538 if (data & BCM_GPIO_MASK(pin)) 539 reg = BCM_GPIO_GPCLR(bank); 540 else 541 reg = BCM_GPIO_GPSET(bank); 542 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 543 BCM_GPIO_UNLOCK(sc); 544 545 return (0); 546 } 547 548 static int 549 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS) 550 { 551 char buf[16]; 552 struct bcm_gpio_softc *sc; 553 struct bcm_gpio_sysctl *sc_sysctl; 554 uint32_t nfunc; 555 int error; 556 557 sc_sysctl = arg1; 558 sc = sc_sysctl->sc; 559 560 /* Get the current pin function. */ 561 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin); 562 bcm_gpio_func_str(nfunc, buf, sizeof(buf)); 563 564 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 565 if (error != 0 || req->newptr == NULL) 566 return (error); 567 /* Ignore changes on read-only pins. */ 568 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin)) 569 return (0); 570 /* Parse the user supplied string and check for a valid pin function. */ 571 if (bcm_gpio_str_func(buf, &nfunc) != 0) 572 return (EINVAL); 573 574 /* Update the pin alternate function. */ 575 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc); 576 577 return (0); 578 } 579 580 static void 581 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc) 582 { 583 char pinbuf[3]; 584 struct bcm_gpio_sysctl *sc_sysctl; 585 struct sysctl_ctx_list *ctx; 586 struct sysctl_oid *tree_node, *pin_node, *pinN_node; 587 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree; 588 int i; 589 590 /* 591 * Add per-pin sysctl tree/handlers. 592 */ 593 ctx = device_get_sysctl_ctx(sc->sc_dev); 594 tree_node = device_get_sysctl_tree(sc->sc_dev); 595 tree = SYSCTL_CHILDREN(tree_node); 596 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin", 597 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GPIO Pins"); 598 pin_tree = SYSCTL_CHILDREN(pin_node); 599 600 for (i = 0; i < sc->sc_gpio_npins; i++) { 601 snprintf(pinbuf, sizeof(pinbuf), "%d", i); 602 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf, 603 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GPIO Pin"); 604 pinN_tree = SYSCTL_CHILDREN(pinN_node); 605 606 sc->sc_sysctl[i].sc = sc; 607 sc_sysctl = &sc->sc_sysctl[i]; 608 sc_sysctl->sc = sc; 609 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin; 610 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function", 611 CTLFLAG_RW | CTLTYPE_STRING | CTLFLAG_NEEDGIANT, sc_sysctl, 612 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc, 613 "A", "Pin Function"); 614 } 615 } 616 617 static int 618 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node, 619 const char *propname, const char *label) 620 { 621 int i, need_comma, npins, range_start, range_stop; 622 pcell_t *pins; 623 624 /* Get the property data. */ 625 npins = OF_getencprop_alloc_multi(node, propname, sizeof(*pins), 626 (void **)&pins); 627 if (npins < 0) 628 return (-1); 629 if (npins == 0) { 630 OF_prop_free(pins); 631 return (0); 632 } 633 for (i = 0; i < npins; i++) 634 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i]; 635 sc->sc_ro_npins += npins; 636 need_comma = 0; 637 device_printf(sc->sc_dev, "%s pins: ", label); 638 range_start = range_stop = pins[0]; 639 for (i = 1; i < npins; i++) { 640 if (pins[i] != range_stop + 1) { 641 if (need_comma) 642 printf(","); 643 if (range_start != range_stop) 644 printf("%d-%d", range_start, range_stop); 645 else 646 printf("%d", range_start); 647 range_start = range_stop = pins[i]; 648 need_comma = 1; 649 } else 650 range_stop++; 651 } 652 if (need_comma) 653 printf(","); 654 if (range_start != range_stop) 655 printf("%d-%d.\n", range_start, range_stop); 656 else 657 printf("%d.\n", range_start); 658 OF_prop_free(pins); 659 660 return (0); 661 } 662 663 static int 664 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc) 665 { 666 char *name; 667 phandle_t gpio, node, reserved; 668 ssize_t len; 669 670 /* Get read-only pins if they're provided */ 671 gpio = ofw_bus_get_node(sc->sc_dev); 672 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only", 673 "read-only") != 0) 674 return (0); 675 /* Traverse the GPIO subnodes to find the reserved pins node. */ 676 reserved = 0; 677 node = OF_child(gpio); 678 while ((node != 0) && (reserved == 0)) { 679 len = OF_getprop_alloc(node, "name", (void **)&name); 680 if (len == -1) 681 return (-1); 682 if (strcmp(name, "reserved") == 0) 683 reserved = node; 684 OF_prop_free(name); 685 node = OF_peer(node); 686 } 687 if (reserved == 0) 688 return (-1); 689 /* Get the reserved pins. */ 690 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins", 691 "reserved") != 0) 692 return (-1); 693 694 return (0); 695 } 696 697 static int 698 bcm_gpio_probe(device_t dev) 699 { 700 701 if (!ofw_bus_status_okay(dev)) 702 return (ENXIO); 703 704 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 705 return (ENXIO); 706 707 device_set_desc(dev, "BCM2708/2835 GPIO controller"); 708 return (BUS_PROBE_DEFAULT); 709 } 710 711 static int 712 bcm_gpio_intr_attach(device_t dev) 713 { 714 struct bcm_gpio_softc *sc; 715 716 /* 717 * Only first two interrupt lines are used. Third line is 718 * mirrored second line and forth line is common for all banks. 719 */ 720 sc = device_get_softc(dev); 721 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL) 722 return (-1); 723 724 if (bcm_gpio_pic_attach(sc) != 0) { 725 device_printf(dev, "unable to attach PIC\n"); 726 return (-1); 727 } 728 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE, 729 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0) 730 return (-1); 731 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE, 732 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0) 733 return (-1); 734 735 return (0); 736 } 737 738 static void 739 bcm_gpio_intr_detach(device_t dev) 740 { 741 struct bcm_gpio_softc *sc; 742 743 sc = device_get_softc(dev); 744 if (sc->sc_intrhand[0] != NULL) 745 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]); 746 if (sc->sc_intrhand[1] != NULL) 747 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]); 748 749 bcm_gpio_pic_detach(sc); 750 } 751 752 static int 753 bcm_gpio_attach(device_t dev) 754 { 755 int i, j; 756 phandle_t gpio; 757 struct bcm_gpio_softc *sc; 758 uint32_t func; 759 760 if (bcm_gpio_sc != NULL) 761 return (ENXIO); 762 763 bcm_gpio_sc = sc = device_get_softc(dev); 764 sc->sc_dev = dev; 765 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN); 766 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) { 767 device_printf(dev, "cannot allocate resources\n"); 768 goto fail; 769 } 770 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 771 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 772 /* Setup the GPIO interrupt handler. */ 773 if (bcm_gpio_intr_attach(dev)) { 774 device_printf(dev, "unable to setup the gpio irq handler\n"); 775 goto fail; 776 } 777 /* Find our node. */ 778 gpio = ofw_bus_get_node(sc->sc_dev); 779 if (!OF_hasprop(gpio, "gpio-controller")) 780 /* Node is not a GPIO controller. */ 781 goto fail; 782 /* 783 * Find the read-only pins. These are pins we never touch or bad 784 * things could happen. 785 */ 786 if (bcm_gpio_get_reserved_pins(sc) == -1) 787 goto fail; 788 /* Initialize the software controlled pins. */ 789 for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) { 790 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, 791 "pin %d", j); 792 func = bcm_gpio_get_function(sc, j); 793 sc->sc_gpio_pins[i].gp_pin = j; 794 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS; 795 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func); 796 i++; 797 } 798 sc->sc_gpio_npins = i; 799 bcm_gpio_sysctl_init(sc); 800 sc->sc_busdev = gpiobus_attach_bus(dev); 801 if (sc->sc_busdev == NULL) 802 goto fail; 803 804 fdt_pinctrl_register(dev, "brcm,pins"); 805 fdt_pinctrl_configure_tree(dev); 806 807 return (0); 808 809 fail: 810 bcm_gpio_intr_detach(dev); 811 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res); 812 mtx_destroy(&sc->sc_mtx); 813 814 return (ENXIO); 815 } 816 817 static int 818 bcm_gpio_detach(device_t dev) 819 { 820 821 return (EBUSY); 822 } 823 824 static inline void 825 bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask, 826 bool set_bits) 827 { 828 829 if (set_bits) 830 BCM_GPIO_SET_BITS(sc, reg, mask); 831 else 832 BCM_GPIO_CLEAR_BITS(sc, reg, mask); 833 } 834 835 static inline void 836 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 837 { 838 uint32_t bank; 839 840 /* Write 1 to clear. */ 841 bank = BCM_GPIO_BANK(bgi->bgi_irq); 842 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask); 843 } 844 845 static inline bool 846 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi) 847 { 848 849 return (bgi->bgi_mode == GPIO_INTR_LEVEL_LOW || 850 bgi->bgi_mode == GPIO_INTR_LEVEL_HIGH); 851 } 852 853 static inline void 854 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 855 { 856 uint32_t bank; 857 858 bank = BCM_GPIO_BANK(bgi->bgi_irq); 859 BCM_GPIO_LOCK(sc); 860 switch (bgi->bgi_mode) { 861 case GPIO_INTR_LEVEL_LOW: 862 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 863 break; 864 case GPIO_INTR_LEVEL_HIGH: 865 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 866 break; 867 case GPIO_INTR_EDGE_RISING: 868 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 869 break; 870 case GPIO_INTR_EDGE_FALLING: 871 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 872 break; 873 case GPIO_INTR_EDGE_BOTH: 874 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 875 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 876 break; 877 } 878 BCM_GPIO_UNLOCK(sc); 879 } 880 881 static inline void 882 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 883 { 884 uint32_t bank; 885 886 bank = BCM_GPIO_BANK(bgi->bgi_irq); 887 BCM_GPIO_LOCK(sc); 888 switch (bgi->bgi_mode) { 889 case GPIO_INTR_LEVEL_LOW: 890 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 891 break; 892 case GPIO_INTR_LEVEL_HIGH: 893 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 894 break; 895 case GPIO_INTR_EDGE_RISING: 896 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 897 break; 898 case GPIO_INTR_EDGE_FALLING: 899 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 900 break; 901 case GPIO_INTR_EDGE_BOTH: 902 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 903 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 904 break; 905 } 906 BCM_GPIO_UNLOCK(sc); 907 } 908 909 static int 910 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank) 911 { 912 u_int irq; 913 struct bcm_gpio_irqsrc *bgi; 914 uint32_t reg; 915 916 /* Do not care of spurious interrupt on GPIO. */ 917 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); 918 while (reg != 0) { 919 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1; 920 bgi = sc->sc_isrcs + irq; 921 if (!bcm_gpio_isrc_is_level(bgi)) 922 bcm_gpio_isrc_eoi(sc, bgi); 923 if (intr_isrc_dispatch(&bgi->bgi_isrc, 924 curthread->td_intr_frame) != 0) { 925 bcm_gpio_isrc_mask(sc, bgi); 926 if (bcm_gpio_isrc_is_level(bgi)) 927 bcm_gpio_isrc_eoi(sc, bgi); 928 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 929 irq); 930 } 931 reg &= ~bgi->bgi_mask; 932 } 933 return (FILTER_HANDLED); 934 } 935 936 static int 937 bcm_gpio_intr_bank0(void *arg) 938 { 939 940 return (bcm_gpio_intr_internal(arg, 0)); 941 } 942 943 static int 944 bcm_gpio_intr_bank1(void *arg) 945 { 946 947 return (bcm_gpio_intr_internal(arg, 1)); 948 } 949 950 static int 951 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc) 952 { 953 int error; 954 uint32_t irq; 955 const char *name; 956 957 name = device_get_nameunit(sc->sc_dev); 958 for (irq = 0; irq < BCM_GPIO_PINS; irq++) { 959 sc->sc_isrcs[irq].bgi_irq = irq; 960 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq); 961 sc->sc_isrcs[irq].bgi_mode = GPIO_INTR_CONFORM; 962 963 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc, 964 sc->sc_dev, 0, "%s,%u", name, irq); 965 if (error != 0) 966 return (error); /* XXX deregister ISRCs */ 967 } 968 if (intr_pic_register(sc->sc_dev, 969 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 970 return (ENXIO); 971 972 return (0); 973 } 974 975 static int 976 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc) 977 { 978 979 /* 980 * There has not been established any procedure yet 981 * how to detach PIC from living system correctly. 982 */ 983 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 984 return (EBUSY); 985 } 986 987 static void 988 bcm_gpio_pic_config_intr(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi, 989 uint32_t mode) 990 { 991 uint32_t bank; 992 993 bank = BCM_GPIO_BANK(bgi->bgi_irq); 994 BCM_GPIO_LOCK(sc); 995 bcm_gpio_modify(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask, 996 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 997 bcm_gpio_modify(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask, 998 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 999 bcm_gpio_modify(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask, 1000 mode == GPIO_INTR_LEVEL_HIGH); 1001 bcm_gpio_modify(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask, 1002 mode == GPIO_INTR_LEVEL_LOW); 1003 bgi->bgi_mode = mode; 1004 BCM_GPIO_UNLOCK(sc); 1005 } 1006 1007 static void 1008 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 1009 { 1010 struct bcm_gpio_softc *sc = device_get_softc(dev); 1011 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1012 1013 bcm_gpio_isrc_mask(sc, bgi); 1014 } 1015 1016 static void 1017 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 1018 { 1019 struct bcm_gpio_softc *sc = device_get_softc(dev); 1020 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1021 1022 arm_irq_memory_barrier(bgi->bgi_irq); 1023 bcm_gpio_isrc_unmask(sc, bgi); 1024 } 1025 1026 static int 1027 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf, 1028 u_int *irqp, uint32_t *modep) 1029 { 1030 u_int irq; 1031 uint32_t mode; 1032 1033 /* 1034 * The first cell is the interrupt number. 1035 * The second cell is used to specify flags: 1036 * bits[3:0] trigger type and level flags: 1037 * 1 = low-to-high edge triggered. 1038 * 2 = high-to-low edge triggered. 1039 * 4 = active high level-sensitive. 1040 * 8 = active low level-sensitive. 1041 */ 1042 if (daf->ncells != 2) 1043 return (EINVAL); 1044 1045 irq = daf->cells[0]; 1046 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1047 return (EINVAL); 1048 1049 /* Only reasonable modes are supported. */ 1050 if (daf->cells[1] == 1) 1051 mode = GPIO_INTR_EDGE_RISING; 1052 else if (daf->cells[1] == 2) 1053 mode = GPIO_INTR_EDGE_FALLING; 1054 else if (daf->cells[1] == 3) 1055 mode = GPIO_INTR_EDGE_BOTH; 1056 else if (daf->cells[1] == 4) 1057 mode = GPIO_INTR_LEVEL_HIGH; 1058 else if (daf->cells[1] == 8) 1059 mode = GPIO_INTR_LEVEL_LOW; 1060 else 1061 return (EINVAL); 1062 1063 *irqp = irq; 1064 if (modep != NULL) 1065 *modep = mode; 1066 return (0); 1067 } 1068 1069 static int 1070 bcm_gpio_pic_map_gpio(struct bcm_gpio_softc *sc, struct intr_map_data_gpio *dag, 1071 u_int *irqp, uint32_t *modep) 1072 { 1073 u_int irq; 1074 uint32_t mode; 1075 1076 irq = dag->gpio_pin_num; 1077 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1078 return (EINVAL); 1079 1080 mode = dag->gpio_intr_mode; 1081 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 1082 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 1083 mode != GPIO_INTR_EDGE_BOTH) 1084 return (EINVAL); 1085 1086 *irqp = irq; 1087 if (modep != NULL) 1088 *modep = mode; 1089 return (0); 1090 } 1091 1092 static int 1093 bcm_gpio_pic_map(struct bcm_gpio_softc *sc, struct intr_map_data *data, 1094 u_int *irqp, uint32_t *modep) 1095 { 1096 1097 switch (data->type) { 1098 case INTR_MAP_DATA_FDT: 1099 return (bcm_gpio_pic_map_fdt(sc, 1100 (struct intr_map_data_fdt *)data, irqp, modep)); 1101 case INTR_MAP_DATA_GPIO: 1102 return (bcm_gpio_pic_map_gpio(sc, 1103 (struct intr_map_data_gpio *)data, irqp, modep)); 1104 default: 1105 return (ENOTSUP); 1106 } 1107 } 1108 1109 static int 1110 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1111 struct intr_irqsrc **isrcp) 1112 { 1113 int error; 1114 u_int irq; 1115 struct bcm_gpio_softc *sc = device_get_softc(dev); 1116 1117 error = bcm_gpio_pic_map(sc, data, &irq, NULL); 1118 if (error == 0) 1119 *isrcp = &sc->sc_isrcs[irq].bgi_isrc; 1120 return (error); 1121 } 1122 1123 static void 1124 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1125 { 1126 struct bcm_gpio_softc *sc = device_get_softc(dev); 1127 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1128 1129 if (bcm_gpio_isrc_is_level(bgi)) 1130 bcm_gpio_isrc_eoi(sc, bgi); 1131 } 1132 1133 static void 1134 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1135 { 1136 1137 bcm_gpio_pic_enable_intr(dev, isrc); 1138 } 1139 1140 static void 1141 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1142 { 1143 struct bcm_gpio_softc *sc = device_get_softc(dev); 1144 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1145 1146 bcm_gpio_isrc_mask(sc, bgi); 1147 if (bcm_gpio_isrc_is_level(bgi)) 1148 bcm_gpio_isrc_eoi(sc, bgi); 1149 } 1150 1151 static int 1152 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1153 struct resource *res, struct intr_map_data *data) 1154 { 1155 u_int irq; 1156 uint32_t mode; 1157 struct bcm_gpio_softc *sc; 1158 struct bcm_gpio_irqsrc *bgi; 1159 1160 if (data == NULL) 1161 return (ENOTSUP); 1162 1163 sc = device_get_softc(dev); 1164 bgi = (struct bcm_gpio_irqsrc *)isrc; 1165 1166 /* Get and check config for an interrupt. */ 1167 if (bcm_gpio_pic_map(sc, data, &irq, &mode) != 0 || bgi->bgi_irq != irq) 1168 return (EINVAL); 1169 1170 /* 1171 * If this is a setup for another handler, 1172 * only check that its configuration match. 1173 */ 1174 if (isrc->isrc_handlers != 0) 1175 return (bgi->bgi_mode == mode ? 0 : EINVAL); 1176 1177 bcm_gpio_pic_config_intr(sc, bgi, mode); 1178 return (0); 1179 } 1180 1181 static int 1182 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1183 struct resource *res, struct intr_map_data *data) 1184 { 1185 struct bcm_gpio_softc *sc = device_get_softc(dev); 1186 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1187 1188 if (isrc->isrc_handlers == 0) 1189 bcm_gpio_pic_config_intr(sc, bgi, GPIO_INTR_CONFORM); 1190 return (0); 1191 } 1192 1193 static phandle_t 1194 bcm_gpio_get_node(device_t bus, device_t dev) 1195 { 1196 1197 /* We only have one child, the GPIO bus, which needs our own node. */ 1198 return (ofw_bus_get_node(bus)); 1199 } 1200 1201 static int 1202 bcm_gpio_configure_pins(device_t dev, phandle_t cfgxref) 1203 { 1204 phandle_t cfgnode; 1205 int i, pintuples, pulltuples; 1206 uint32_t pin; 1207 uint32_t *pins; 1208 uint32_t *pulls; 1209 uint32_t function; 1210 static struct bcm_gpio_softc *sc; 1211 1212 sc = device_get_softc(dev); 1213 cfgnode = OF_node_from_xref(cfgxref); 1214 1215 pins = NULL; 1216 pintuples = OF_getencprop_alloc_multi(cfgnode, "brcm,pins", 1217 sizeof(*pins), (void **)&pins); 1218 1219 char name[32]; 1220 OF_getprop(cfgnode, "name", &name, sizeof(name)); 1221 1222 if (pintuples < 0) 1223 return (ENOENT); 1224 1225 if (pintuples == 0) 1226 return (0); /* Empty property is not an error. */ 1227 1228 if (OF_getencprop(cfgnode, "brcm,function", &function, 1229 sizeof(function)) <= 0) { 1230 OF_prop_free(pins); 1231 return (EINVAL); 1232 } 1233 1234 pulls = NULL; 1235 pulltuples = OF_getencprop_alloc_multi(cfgnode, "brcm,pull", 1236 sizeof(*pulls), (void **)&pulls); 1237 1238 if ((pulls != NULL) && (pulltuples != pintuples)) { 1239 OF_prop_free(pins); 1240 OF_prop_free(pulls); 1241 return (EINVAL); 1242 } 1243 1244 for (i = 0; i < pintuples; i++) { 1245 pin = pins[i]; 1246 bcm_gpio_set_alternate(dev, pin, function); 1247 if (bootverbose) 1248 device_printf(dev, "set pin %d to func %d", pin, function); 1249 if (pulls) { 1250 if (bootverbose) 1251 printf(", pull %d", pulls[i]); 1252 switch (pulls[i]) { 1253 /* Convert to gpio(4) flags */ 1254 case BCM2835_PUD_OFF: 1255 bcm_gpio_pin_setflags(dev, pin, 0); 1256 break; 1257 case BCM2835_PUD_UP: 1258 bcm_gpio_pin_setflags(dev, pin, GPIO_PIN_PULLUP); 1259 break; 1260 case BCM2835_PUD_DOWN: 1261 bcm_gpio_pin_setflags(dev, pin, GPIO_PIN_PULLDOWN); 1262 break; 1263 default: 1264 printf("%s: invalid pull value for pin %d: %d\n", 1265 name, pin, pulls[i]); 1266 } 1267 } 1268 if (bootverbose) 1269 printf("\n"); 1270 } 1271 1272 OF_prop_free(pins); 1273 if (pulls) 1274 OF_prop_free(pulls); 1275 1276 return (0); 1277 } 1278 1279 static device_method_t bcm_gpio_methods[] = { 1280 /* Device interface */ 1281 DEVMETHOD(device_probe, bcm_gpio_probe), 1282 DEVMETHOD(device_attach, bcm_gpio_attach), 1283 DEVMETHOD(device_detach, bcm_gpio_detach), 1284 1285 /* GPIO protocol */ 1286 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus), 1287 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max), 1288 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname), 1289 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags), 1290 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps), 1291 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags), 1292 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get), 1293 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set), 1294 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle), 1295 1296 /* Interrupt controller interface */ 1297 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr), 1298 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr), 1299 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr), 1300 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter), 1301 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread), 1302 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread), 1303 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr), 1304 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr), 1305 1306 /* ofw_bus interface */ 1307 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node), 1308 1309 /* fdt_pinctrl interface */ 1310 DEVMETHOD(fdt_pinctrl_configure, bcm_gpio_configure_pins), 1311 1312 DEVMETHOD_END 1313 }; 1314 1315 static devclass_t bcm_gpio_devclass; 1316 1317 static driver_t bcm_gpio_driver = { 1318 "gpio", 1319 bcm_gpio_methods, 1320 sizeof(struct bcm_gpio_softc), 1321 }; 1322 1323 EARLY_DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, bcm_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 1324