1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_platform.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/gpio.h> 39 #include <sys/interrupt.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/proc.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/fdt/fdt_pinctrl.h> 52 #include <dev/gpio/gpiobusvar.h> 53 #include <dev/ofw/ofw_bus.h> 54 55 #include "gpio_if.h" 56 57 #include "pic_if.h" 58 59 #ifdef DEBUG 60 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 61 printf(fmt,##args); } while (0) 62 #else 63 #define dprintf(fmt, args...) 64 #endif 65 66 #define BCM_GPIO_IRQS 4 67 #define BCM_GPIO_PINS_PER_BANK 32 68 #define BCM2835_GPIO_PINS 54 69 #define BCM2711_GPIO_PINS 58 70 #define BCM_GPIO_PINS BCM2711_GPIO_PINS 71 72 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 73 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | \ 74 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 75 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 76 77 #define BCM2835_FSEL_GPIO_IN 0 78 #define BCM2835_FSEL_GPIO_OUT 1 79 #define BCM2835_FSEL_ALT5 2 80 #define BCM2835_FSEL_ALT4 3 81 #define BCM2835_FSEL_ALT0 4 82 #define BCM2835_FSEL_ALT1 5 83 #define BCM2835_FSEL_ALT2 6 84 #define BCM2835_FSEL_ALT3 7 85 86 #define BCM2835_PUD_OFF 0 87 #define BCM2835_PUD_DOWN 1 88 #define BCM2835_PUD_UP 2 89 90 #define BCM2711_PUD_OFF 0 91 #define BCM2711_PUD_DOWN 2 92 #define BCM2711_PUD_UP 1 93 94 static struct resource_spec bcm_gpio_res_spec[] = { 95 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 96 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */ 97 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */ 98 { -1, 0, 0 } 99 }; 100 101 struct bcm_gpio_sysctl { 102 struct bcm_gpio_softc *sc; 103 uint32_t pin; 104 }; 105 106 struct bcm_gpio_irqsrc { 107 struct intr_irqsrc bgi_isrc; 108 uint32_t bgi_irq; 109 uint32_t bgi_mode; 110 uint32_t bgi_mask; 111 }; 112 113 struct bcm_gpio_softc { 114 device_t sc_dev; 115 device_t sc_busdev; 116 struct mtx sc_mtx; 117 struct resource * sc_res[BCM_GPIO_IRQS + 1]; 118 bus_space_tag_t sc_bst; 119 bus_space_handle_t sc_bsh; 120 void * sc_intrhand[BCM_GPIO_IRQS]; 121 bool sc_is2711; 122 u_int sc_maxpins; 123 int sc_gpio_npins; 124 int sc_ro_npins; 125 int sc_ro_pins[BCM_GPIO_PINS]; 126 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS]; 127 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS]; 128 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS]; 129 }; 130 131 enum bcm_gpio_pud { 132 BCM_GPIO_NONE, 133 BCM_GPIO_PULLDOWN, 134 BCM_GPIO_PULLUP, 135 }; 136 137 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 138 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 139 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 140 #define BCM_GPIO_WRITE(_sc, _off, _val) \ 141 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val) 142 #define BCM_GPIO_READ(_sc, _off) \ 143 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off) 144 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \ 145 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits)) 146 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \ 147 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits) 148 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK) 149 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK)) 150 151 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */ 152 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */ 153 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */ 154 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */ 155 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */ 156 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */ 157 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */ 158 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */ 159 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */ 160 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */ 161 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */ 162 #define BCM2835_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */ 163 #define BCM2835_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */ 164 165 #define BCM2711_GPIO_GPPUD(x) (0x0e4 + (x) * sizeof(uint32_t)) /* Pin Pull up/down */ 166 #define BCM2711_GPIO_MASK (0x3) 167 #define BCM2711_GPIO_SHIFT(n) (((n) % 16) * 2) 168 #define BCM2711_GPIO_REGID(n) ((n) / 16) 169 170 static struct ofw_compat_data compat_data[] = { 171 {"broadcom,bcm2835-gpio", 1}, 172 {"brcm,bcm2835-gpio", 1}, 173 {"brcm,bcm2711-gpio", 1}, 174 {NULL, 0} 175 }; 176 177 static struct bcm_gpio_softc *bcm_gpio_sc = NULL; 178 179 static int bcm_gpio_intr_bank0(void *arg); 180 static int bcm_gpio_intr_bank1(void *arg); 181 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc); 182 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc); 183 184 static int 185 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin) 186 { 187 int i; 188 189 for (i = 0; i < sc->sc_ro_npins; i++) 190 if (pin == sc->sc_ro_pins[i]) 191 return (1); 192 return (0); 193 } 194 195 static uint32_t 196 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin) 197 { 198 uint32_t bank, func, offset; 199 200 /* Five banks, 10 pins per bank, 3 bits per pin. */ 201 bank = pin / 10; 202 offset = (pin - bank * 10) * 3; 203 204 BCM_GPIO_LOCK(sc); 205 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7; 206 BCM_GPIO_UNLOCK(sc); 207 208 return (func); 209 } 210 211 static void 212 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize) 213 { 214 215 switch (nfunc) { 216 case BCM2835_FSEL_GPIO_IN: 217 strncpy(buf, "input", bufsize); 218 break; 219 case BCM2835_FSEL_GPIO_OUT: 220 strncpy(buf, "output", bufsize); 221 break; 222 case BCM2835_FSEL_ALT0: 223 strncpy(buf, "alt0", bufsize); 224 break; 225 case BCM2835_FSEL_ALT1: 226 strncpy(buf, "alt1", bufsize); 227 break; 228 case BCM2835_FSEL_ALT2: 229 strncpy(buf, "alt2", bufsize); 230 break; 231 case BCM2835_FSEL_ALT3: 232 strncpy(buf, "alt3", bufsize); 233 break; 234 case BCM2835_FSEL_ALT4: 235 strncpy(buf, "alt4", bufsize); 236 break; 237 case BCM2835_FSEL_ALT5: 238 strncpy(buf, "alt5", bufsize); 239 break; 240 default: 241 strncpy(buf, "invalid", bufsize); 242 } 243 } 244 245 static int 246 bcm_gpio_str_func(char *func, uint32_t *nfunc) 247 { 248 249 if (strcasecmp(func, "input") == 0) 250 *nfunc = BCM2835_FSEL_GPIO_IN; 251 else if (strcasecmp(func, "output") == 0) 252 *nfunc = BCM2835_FSEL_GPIO_OUT; 253 else if (strcasecmp(func, "alt0") == 0) 254 *nfunc = BCM2835_FSEL_ALT0; 255 else if (strcasecmp(func, "alt1") == 0) 256 *nfunc = BCM2835_FSEL_ALT1; 257 else if (strcasecmp(func, "alt2") == 0) 258 *nfunc = BCM2835_FSEL_ALT2; 259 else if (strcasecmp(func, "alt3") == 0) 260 *nfunc = BCM2835_FSEL_ALT3; 261 else if (strcasecmp(func, "alt4") == 0) 262 *nfunc = BCM2835_FSEL_ALT4; 263 else if (strcasecmp(func, "alt5") == 0) 264 *nfunc = BCM2835_FSEL_ALT5; 265 else 266 return (-1); 267 268 return (0); 269 } 270 271 static uint32_t 272 bcm_gpio_func_flag(uint32_t nfunc) 273 { 274 275 switch (nfunc) { 276 case BCM2835_FSEL_GPIO_IN: 277 return (GPIO_PIN_INPUT); 278 case BCM2835_FSEL_GPIO_OUT: 279 return (GPIO_PIN_OUTPUT); 280 } 281 return (0); 282 } 283 284 static void 285 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f) 286 { 287 uint32_t bank, data, offset; 288 289 /* Must be called with lock held. */ 290 BCM_GPIO_LOCK_ASSERT(sc); 291 292 /* Five banks, 10 pins per bank, 3 bits per pin. */ 293 bank = pin / 10; 294 offset = (pin - bank * 10) * 3; 295 296 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)); 297 data &= ~(7 << offset); 298 data |= (f << offset); 299 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data); 300 } 301 302 static void 303 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state) 304 { 305 /* Must be called with lock held. */ 306 BCM_GPIO_LOCK_ASSERT(sc); 307 308 if (sc->sc_is2711) { /* BCM2711 */ 309 u_int regid = BCM2711_GPIO_REGID(pin); 310 u_int shift = BCM2711_GPIO_SHIFT(pin); 311 uint32_t reg; 312 313 switch (state) { 314 case BCM2835_PUD_OFF: 315 state = BCM2711_PUD_OFF; 316 break; 317 case BCM2835_PUD_DOWN: 318 state = BCM2711_PUD_DOWN; 319 break; 320 case BCM2835_PUD_UP: 321 state = BCM2711_PUD_UP; 322 break; 323 } 324 325 reg = BCM_GPIO_READ(sc, BCM2711_GPIO_GPPUD(regid)); 326 reg &= ~(BCM2711_GPIO_MASK << shift); 327 reg |= (state << shift); 328 BCM_GPIO_WRITE(sc, BCM2711_GPIO_GPPUD(regid), reg); 329 } else { /* BCM2835 */ 330 uint32_t bank; 331 332 bank = BCM_GPIO_BANK(pin); 333 BCM_GPIO_WRITE(sc, BCM2835_GPIO_GPPUD(0), state); 334 BCM_GPIO_WRITE(sc, BCM2835_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin)); 335 BCM_GPIO_WRITE(sc, BCM2835_GPIO_GPPUD(0), 0); 336 BCM_GPIO_WRITE(sc, BCM2835_GPIO_GPPUDCLK(bank), 0); 337 } 338 } 339 340 static void 341 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc) 342 { 343 struct bcm_gpio_softc *sc; 344 int i; 345 346 sc = device_get_softc(dev); 347 BCM_GPIO_LOCK(sc); 348 349 /* Set the pin function. */ 350 bcm_gpio_set_function(sc, pin, nfunc); 351 352 /* Update the pin flags. */ 353 for (i = 0; i < sc->sc_gpio_npins; i++) { 354 if (sc->sc_gpio_pins[i].gp_pin == pin) 355 break; 356 } 357 if (i < sc->sc_gpio_npins) 358 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc); 359 360 BCM_GPIO_UNLOCK(sc); 361 } 362 363 static void 364 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin, 365 unsigned int flags) 366 { 367 368 BCM_GPIO_LOCK(sc); 369 370 /* 371 * Manage input/output. 372 */ 373 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 374 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); 375 if (flags & GPIO_PIN_OUTPUT) { 376 pin->gp_flags |= GPIO_PIN_OUTPUT; 377 bcm_gpio_set_function(sc, pin->gp_pin, 378 BCM2835_FSEL_GPIO_OUT); 379 } else { 380 pin->gp_flags |= GPIO_PIN_INPUT; 381 bcm_gpio_set_function(sc, pin->gp_pin, 382 BCM2835_FSEL_GPIO_IN); 383 } 384 } 385 386 /* Manage Pull-up/pull-down. */ 387 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN); 388 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 389 if (flags & GPIO_PIN_PULLUP) { 390 pin->gp_flags |= GPIO_PIN_PULLUP; 391 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP); 392 } else { 393 pin->gp_flags |= GPIO_PIN_PULLDOWN; 394 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN); 395 } 396 } else 397 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE); 398 399 BCM_GPIO_UNLOCK(sc); 400 } 401 402 static device_t 403 bcm_gpio_get_bus(device_t dev) 404 { 405 struct bcm_gpio_softc *sc; 406 407 sc = device_get_softc(dev); 408 409 return (sc->sc_busdev); 410 } 411 412 static int 413 bcm_gpio_pin_max(device_t dev, int *maxpin) 414 { 415 struct bcm_gpio_softc *sc; 416 417 sc = device_get_softc(dev); 418 *maxpin = sc->sc_maxpins - 1; 419 return (0); 420 } 421 422 static int 423 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 424 { 425 struct bcm_gpio_softc *sc = device_get_softc(dev); 426 int i; 427 428 for (i = 0; i < sc->sc_gpio_npins; i++) { 429 if (sc->sc_gpio_pins[i].gp_pin == pin) 430 break; 431 } 432 433 if (i >= sc->sc_gpio_npins) 434 return (EINVAL); 435 436 BCM_GPIO_LOCK(sc); 437 *caps = sc->sc_gpio_pins[i].gp_caps; 438 BCM_GPIO_UNLOCK(sc); 439 440 return (0); 441 } 442 443 static int 444 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 445 { 446 struct bcm_gpio_softc *sc = device_get_softc(dev); 447 int i; 448 449 for (i = 0; i < sc->sc_gpio_npins; i++) { 450 if (sc->sc_gpio_pins[i].gp_pin == pin) 451 break; 452 } 453 454 if (i >= sc->sc_gpio_npins) 455 return (EINVAL); 456 457 BCM_GPIO_LOCK(sc); 458 *flags = sc->sc_gpio_pins[i].gp_flags; 459 BCM_GPIO_UNLOCK(sc); 460 461 return (0); 462 } 463 464 static int 465 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 466 { 467 struct bcm_gpio_softc *sc = device_get_softc(dev); 468 int i; 469 470 for (i = 0; i < sc->sc_gpio_npins; i++) { 471 if (sc->sc_gpio_pins[i].gp_pin == pin) 472 break; 473 } 474 475 if (i >= sc->sc_gpio_npins) 476 return (EINVAL); 477 478 BCM_GPIO_LOCK(sc); 479 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME); 480 BCM_GPIO_UNLOCK(sc); 481 482 return (0); 483 } 484 485 static int 486 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 487 { 488 struct bcm_gpio_softc *sc = device_get_softc(dev); 489 int i; 490 491 for (i = 0; i < sc->sc_gpio_npins; i++) { 492 if (sc->sc_gpio_pins[i].gp_pin == pin) 493 break; 494 } 495 496 if (i >= sc->sc_gpio_npins) 497 return (EINVAL); 498 499 /* We never touch on read-only/reserved pins. */ 500 if (bcm_gpio_pin_is_ro(sc, pin)) 501 return (EINVAL); 502 503 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags); 504 505 return (0); 506 } 507 508 static int 509 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 510 { 511 struct bcm_gpio_softc *sc = device_get_softc(dev); 512 uint32_t bank, reg; 513 int i; 514 515 for (i = 0; i < sc->sc_gpio_npins; i++) { 516 if (sc->sc_gpio_pins[i].gp_pin == pin) 517 break; 518 } 519 if (i >= sc->sc_gpio_npins) 520 return (EINVAL); 521 /* We never write to read-only/reserved pins. */ 522 if (bcm_gpio_pin_is_ro(sc, pin)) 523 return (EINVAL); 524 BCM_GPIO_LOCK(sc); 525 bank = BCM_GPIO_BANK(pin); 526 if (value) 527 reg = BCM_GPIO_GPSET(bank); 528 else 529 reg = BCM_GPIO_GPCLR(bank); 530 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 531 BCM_GPIO_UNLOCK(sc); 532 533 return (0); 534 } 535 536 static int 537 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 538 { 539 struct bcm_gpio_softc *sc = device_get_softc(dev); 540 uint32_t bank, reg_data; 541 int i; 542 543 for (i = 0; i < sc->sc_gpio_npins; i++) { 544 if (sc->sc_gpio_pins[i].gp_pin == pin) 545 break; 546 } 547 if (i >= sc->sc_gpio_npins) 548 return (EINVAL); 549 bank = BCM_GPIO_BANK(pin); 550 BCM_GPIO_LOCK(sc); 551 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 552 BCM_GPIO_UNLOCK(sc); 553 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0; 554 555 return (0); 556 } 557 558 static int 559 bcm_gpio_pin_toggle(device_t dev, uint32_t pin) 560 { 561 struct bcm_gpio_softc *sc = device_get_softc(dev); 562 uint32_t bank, data, reg; 563 int i; 564 565 for (i = 0; i < sc->sc_gpio_npins; i++) { 566 if (sc->sc_gpio_pins[i].gp_pin == pin) 567 break; 568 } 569 if (i >= sc->sc_gpio_npins) 570 return (EINVAL); 571 /* We never write to read-only/reserved pins. */ 572 if (bcm_gpio_pin_is_ro(sc, pin)) 573 return (EINVAL); 574 BCM_GPIO_LOCK(sc); 575 bank = BCM_GPIO_BANK(pin); 576 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 577 if (data & BCM_GPIO_MASK(pin)) 578 reg = BCM_GPIO_GPCLR(bank); 579 else 580 reg = BCM_GPIO_GPSET(bank); 581 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 582 BCM_GPIO_UNLOCK(sc); 583 584 return (0); 585 } 586 587 static int 588 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS) 589 { 590 char buf[16]; 591 struct bcm_gpio_softc *sc; 592 struct bcm_gpio_sysctl *sc_sysctl; 593 uint32_t nfunc; 594 int error; 595 596 sc_sysctl = arg1; 597 sc = sc_sysctl->sc; 598 599 /* Get the current pin function. */ 600 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin); 601 bcm_gpio_func_str(nfunc, buf, sizeof(buf)); 602 603 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 604 if (error != 0 || req->newptr == NULL) 605 return (error); 606 /* Ignore changes on read-only pins. */ 607 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin)) 608 return (0); 609 /* Parse the user supplied string and check for a valid pin function. */ 610 if (bcm_gpio_str_func(buf, &nfunc) != 0) 611 return (EINVAL); 612 613 /* Update the pin alternate function. */ 614 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc); 615 616 return (0); 617 } 618 619 static void 620 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc) 621 { 622 char pinbuf[3]; 623 struct bcm_gpio_sysctl *sc_sysctl; 624 struct sysctl_ctx_list *ctx; 625 struct sysctl_oid *tree_node, *pin_node, *pinN_node; 626 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree; 627 int i; 628 629 /* 630 * Add per-pin sysctl tree/handlers. 631 */ 632 ctx = device_get_sysctl_ctx(sc->sc_dev); 633 tree_node = device_get_sysctl_tree(sc->sc_dev); 634 tree = SYSCTL_CHILDREN(tree_node); 635 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin", 636 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GPIO Pins"); 637 pin_tree = SYSCTL_CHILDREN(pin_node); 638 639 for (i = 0; i < sc->sc_gpio_npins; i++) { 640 snprintf(pinbuf, sizeof(pinbuf), "%d", i); 641 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf, 642 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GPIO Pin"); 643 pinN_tree = SYSCTL_CHILDREN(pinN_node); 644 645 sc->sc_sysctl[i].sc = sc; 646 sc_sysctl = &sc->sc_sysctl[i]; 647 sc_sysctl->sc = sc; 648 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin; 649 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function", 650 CTLFLAG_RW | CTLTYPE_STRING | CTLFLAG_NEEDGIANT, sc_sysctl, 651 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc, 652 "A", "Pin Function"); 653 } 654 } 655 656 static int 657 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node, 658 const char *propname, const char *label) 659 { 660 int i, need_comma, npins, range_start, range_stop; 661 pcell_t *pins; 662 663 /* Get the property data. */ 664 npins = OF_getencprop_alloc_multi(node, propname, sizeof(*pins), 665 (void **)&pins); 666 if (npins < 0) 667 return (-1); 668 if (npins == 0) { 669 OF_prop_free(pins); 670 return (0); 671 } 672 for (i = 0; i < npins; i++) 673 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i]; 674 sc->sc_ro_npins += npins; 675 need_comma = 0; 676 device_printf(sc->sc_dev, "%s pins: ", label); 677 range_start = range_stop = pins[0]; 678 for (i = 1; i < npins; i++) { 679 if (pins[i] != range_stop + 1) { 680 if (need_comma) 681 printf(","); 682 if (range_start != range_stop) 683 printf("%d-%d", range_start, range_stop); 684 else 685 printf("%d", range_start); 686 range_start = range_stop = pins[i]; 687 need_comma = 1; 688 } else 689 range_stop++; 690 } 691 if (need_comma) 692 printf(","); 693 if (range_start != range_stop) 694 printf("%d-%d.\n", range_start, range_stop); 695 else 696 printf("%d.\n", range_start); 697 OF_prop_free(pins); 698 699 return (0); 700 } 701 702 static int 703 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc) 704 { 705 char *name; 706 phandle_t gpio, node, reserved; 707 ssize_t len; 708 709 /* Get read-only pins if they're provided */ 710 gpio = ofw_bus_get_node(sc->sc_dev); 711 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only", 712 "read-only") != 0) 713 return (0); 714 /* Traverse the GPIO subnodes to find the reserved pins node. */ 715 reserved = 0; 716 node = OF_child(gpio); 717 while ((node != 0) && (reserved == 0)) { 718 len = OF_getprop_alloc(node, "name", (void **)&name); 719 if (len == -1) 720 return (-1); 721 if (strcmp(name, "reserved") == 0) 722 reserved = node; 723 OF_prop_free(name); 724 node = OF_peer(node); 725 } 726 if (reserved == 0) 727 return (-1); 728 /* Get the reserved pins. */ 729 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins", 730 "reserved") != 0) 731 return (-1); 732 733 return (0); 734 } 735 736 static int 737 bcm_gpio_probe(device_t dev) 738 { 739 740 if (!ofw_bus_status_okay(dev)) 741 return (ENXIO); 742 743 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 744 return (ENXIO); 745 746 device_set_desc(dev, "BCM2708/2835 GPIO controller"); 747 return (BUS_PROBE_DEFAULT); 748 } 749 750 static int 751 bcm_gpio_intr_attach(device_t dev) 752 { 753 struct bcm_gpio_softc *sc; 754 755 /* 756 * Only first two interrupt lines are used. Third line is 757 * mirrored second line and forth line is common for all banks. 758 */ 759 sc = device_get_softc(dev); 760 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL) 761 return (-1); 762 763 if (bcm_gpio_pic_attach(sc) != 0) { 764 device_printf(dev, "unable to attach PIC\n"); 765 return (-1); 766 } 767 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE, 768 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0) 769 return (-1); 770 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE, 771 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0) 772 return (-1); 773 774 return (0); 775 } 776 777 static void 778 bcm_gpio_intr_detach(device_t dev) 779 { 780 struct bcm_gpio_softc *sc; 781 782 sc = device_get_softc(dev); 783 if (sc->sc_intrhand[0] != NULL) 784 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]); 785 if (sc->sc_intrhand[1] != NULL) 786 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]); 787 788 bcm_gpio_pic_detach(sc); 789 } 790 791 static int 792 bcm_gpio_attach(device_t dev) 793 { 794 int i, j; 795 phandle_t gpio; 796 struct bcm_gpio_softc *sc; 797 uint32_t func; 798 799 if (bcm_gpio_sc != NULL) 800 return (ENXIO); 801 802 bcm_gpio_sc = sc = device_get_softc(dev); 803 sc->sc_dev = dev; 804 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN); 805 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) { 806 device_printf(dev, "cannot allocate resources\n"); 807 goto fail; 808 } 809 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 810 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 811 /* Find our node. */ 812 gpio = ofw_bus_get_node(sc->sc_dev); 813 if (!OF_hasprop(gpio, "gpio-controller")) 814 /* Node is not a GPIO controller. */ 815 goto fail; 816 /* Guess I'm BCM2711 or not. */ 817 sc->sc_is2711 = ofw_bus_node_is_compatible(gpio, "brcm,bcm2711-gpio"); 818 sc->sc_maxpins = sc->sc_is2711 ? BCM2711_GPIO_PINS : BCM2835_GPIO_PINS; 819 /* Setup the GPIO interrupt handler. */ 820 if (bcm_gpio_intr_attach(dev)) { 821 device_printf(dev, "unable to setup the gpio irq handler\n"); 822 goto fail; 823 } 824 /* 825 * Find the read-only pins. These are pins we never touch or bad 826 * things could happen. 827 */ 828 if (bcm_gpio_get_reserved_pins(sc) == -1) 829 goto fail; 830 /* Initialize the software controlled pins. */ 831 for (i = 0, j = 0; j < sc->sc_maxpins; j++) { 832 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, 833 "pin %d", j); 834 func = bcm_gpio_get_function(sc, j); 835 sc->sc_gpio_pins[i].gp_pin = j; 836 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS; 837 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func); 838 i++; 839 } 840 sc->sc_gpio_npins = i; 841 bcm_gpio_sysctl_init(sc); 842 sc->sc_busdev = gpiobus_attach_bus(dev); 843 if (sc->sc_busdev == NULL) 844 goto fail; 845 846 fdt_pinctrl_register(dev, "brcm,pins"); 847 fdt_pinctrl_configure_tree(dev); 848 849 return (0); 850 851 fail: 852 bcm_gpio_intr_detach(dev); 853 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res); 854 mtx_destroy(&sc->sc_mtx); 855 856 return (ENXIO); 857 } 858 859 static int 860 bcm_gpio_detach(device_t dev) 861 { 862 863 return (EBUSY); 864 } 865 866 static inline void 867 bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask, 868 bool set_bits) 869 { 870 871 if (set_bits) 872 BCM_GPIO_SET_BITS(sc, reg, mask); 873 else 874 BCM_GPIO_CLEAR_BITS(sc, reg, mask); 875 } 876 877 static inline void 878 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 879 { 880 uint32_t bank; 881 882 /* Write 1 to clear. */ 883 bank = BCM_GPIO_BANK(bgi->bgi_irq); 884 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask); 885 } 886 887 static inline bool 888 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi) 889 { 890 891 return (bgi->bgi_mode == GPIO_INTR_LEVEL_LOW || 892 bgi->bgi_mode == GPIO_INTR_LEVEL_HIGH); 893 } 894 895 static inline void 896 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 897 { 898 uint32_t bank; 899 900 bank = BCM_GPIO_BANK(bgi->bgi_irq); 901 BCM_GPIO_LOCK(sc); 902 switch (bgi->bgi_mode) { 903 case GPIO_INTR_LEVEL_LOW: 904 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 905 break; 906 case GPIO_INTR_LEVEL_HIGH: 907 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 908 break; 909 case GPIO_INTR_EDGE_RISING: 910 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 911 break; 912 case GPIO_INTR_EDGE_FALLING: 913 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 914 break; 915 case GPIO_INTR_EDGE_BOTH: 916 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 917 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 918 break; 919 } 920 BCM_GPIO_UNLOCK(sc); 921 } 922 923 static inline void 924 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 925 { 926 uint32_t bank; 927 928 bank = BCM_GPIO_BANK(bgi->bgi_irq); 929 BCM_GPIO_LOCK(sc); 930 switch (bgi->bgi_mode) { 931 case GPIO_INTR_LEVEL_LOW: 932 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 933 break; 934 case GPIO_INTR_LEVEL_HIGH: 935 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 936 break; 937 case GPIO_INTR_EDGE_RISING: 938 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 939 break; 940 case GPIO_INTR_EDGE_FALLING: 941 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 942 break; 943 case GPIO_INTR_EDGE_BOTH: 944 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 945 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 946 break; 947 } 948 BCM_GPIO_UNLOCK(sc); 949 } 950 951 static int 952 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank) 953 { 954 u_int irq; 955 struct bcm_gpio_irqsrc *bgi; 956 uint32_t reg; 957 958 /* Do not care of spurious interrupt on GPIO. */ 959 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); 960 while (reg != 0) { 961 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1; 962 bgi = sc->sc_isrcs + irq; 963 if (!bcm_gpio_isrc_is_level(bgi)) 964 bcm_gpio_isrc_eoi(sc, bgi); 965 if (intr_isrc_dispatch(&bgi->bgi_isrc, 966 curthread->td_intr_frame) != 0) { 967 bcm_gpio_isrc_mask(sc, bgi); 968 if (bcm_gpio_isrc_is_level(bgi)) 969 bcm_gpio_isrc_eoi(sc, bgi); 970 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 971 irq); 972 } 973 reg &= ~bgi->bgi_mask; 974 } 975 return (FILTER_HANDLED); 976 } 977 978 static int 979 bcm_gpio_intr_bank0(void *arg) 980 { 981 982 return (bcm_gpio_intr_internal(arg, 0)); 983 } 984 985 static int 986 bcm_gpio_intr_bank1(void *arg) 987 { 988 989 return (bcm_gpio_intr_internal(arg, 1)); 990 } 991 992 static int 993 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc) 994 { 995 int error; 996 uint32_t irq; 997 const char *name; 998 999 name = device_get_nameunit(sc->sc_dev); 1000 for (irq = 0; irq < sc->sc_maxpins; irq++) { 1001 sc->sc_isrcs[irq].bgi_irq = irq; 1002 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq); 1003 sc->sc_isrcs[irq].bgi_mode = GPIO_INTR_CONFORM; 1004 1005 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc, 1006 sc->sc_dev, 0, "%s,%u", name, irq); 1007 if (error != 0) 1008 return (error); /* XXX deregister ISRCs */ 1009 } 1010 if (intr_pic_register(sc->sc_dev, 1011 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 1012 return (ENXIO); 1013 1014 return (0); 1015 } 1016 1017 static int 1018 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc) 1019 { 1020 1021 /* 1022 * There has not been established any procedure yet 1023 * how to detach PIC from living system correctly. 1024 */ 1025 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 1026 return (EBUSY); 1027 } 1028 1029 static void 1030 bcm_gpio_pic_config_intr(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi, 1031 uint32_t mode) 1032 { 1033 uint32_t bank; 1034 1035 bank = BCM_GPIO_BANK(bgi->bgi_irq); 1036 BCM_GPIO_LOCK(sc); 1037 bcm_gpio_modify(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask, 1038 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 1039 bcm_gpio_modify(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask, 1040 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 1041 bcm_gpio_modify(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask, 1042 mode == GPIO_INTR_LEVEL_HIGH); 1043 bcm_gpio_modify(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask, 1044 mode == GPIO_INTR_LEVEL_LOW); 1045 bgi->bgi_mode = mode; 1046 BCM_GPIO_UNLOCK(sc); 1047 } 1048 1049 static void 1050 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 1051 { 1052 struct bcm_gpio_softc *sc = device_get_softc(dev); 1053 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1054 1055 bcm_gpio_isrc_mask(sc, bgi); 1056 } 1057 1058 static void 1059 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 1060 { 1061 struct bcm_gpio_softc *sc = device_get_softc(dev); 1062 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1063 1064 arm_irq_memory_barrier(bgi->bgi_irq); 1065 bcm_gpio_isrc_unmask(sc, bgi); 1066 } 1067 1068 static int 1069 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf, 1070 u_int *irqp, uint32_t *modep) 1071 { 1072 u_int irq; 1073 uint32_t mode; 1074 1075 /* 1076 * The first cell is the interrupt number. 1077 * The second cell is used to specify flags: 1078 * bits[3:0] trigger type and level flags: 1079 * 1 = low-to-high edge triggered. 1080 * 2 = high-to-low edge triggered. 1081 * 4 = active high level-sensitive. 1082 * 8 = active low level-sensitive. 1083 */ 1084 if (daf->ncells != 2) 1085 return (EINVAL); 1086 1087 irq = daf->cells[0]; 1088 if (irq >= sc->sc_maxpins || bcm_gpio_pin_is_ro(sc, irq)) 1089 return (EINVAL); 1090 1091 /* Only reasonable modes are supported. */ 1092 if (daf->cells[1] == 1) 1093 mode = GPIO_INTR_EDGE_RISING; 1094 else if (daf->cells[1] == 2) 1095 mode = GPIO_INTR_EDGE_FALLING; 1096 else if (daf->cells[1] == 3) 1097 mode = GPIO_INTR_EDGE_BOTH; 1098 else if (daf->cells[1] == 4) 1099 mode = GPIO_INTR_LEVEL_HIGH; 1100 else if (daf->cells[1] == 8) 1101 mode = GPIO_INTR_LEVEL_LOW; 1102 else 1103 return (EINVAL); 1104 1105 *irqp = irq; 1106 if (modep != NULL) 1107 *modep = mode; 1108 return (0); 1109 } 1110 1111 static int 1112 bcm_gpio_pic_map_gpio(struct bcm_gpio_softc *sc, struct intr_map_data_gpio *dag, 1113 u_int *irqp, uint32_t *modep) 1114 { 1115 u_int irq; 1116 uint32_t mode; 1117 1118 irq = dag->gpio_pin_num; 1119 if (irq >= sc->sc_maxpins || bcm_gpio_pin_is_ro(sc, irq)) 1120 return (EINVAL); 1121 1122 mode = dag->gpio_intr_mode; 1123 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 1124 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 1125 mode != GPIO_INTR_EDGE_BOTH) 1126 return (EINVAL); 1127 1128 *irqp = irq; 1129 if (modep != NULL) 1130 *modep = mode; 1131 return (0); 1132 } 1133 1134 static int 1135 bcm_gpio_pic_map(struct bcm_gpio_softc *sc, struct intr_map_data *data, 1136 u_int *irqp, uint32_t *modep) 1137 { 1138 1139 switch (data->type) { 1140 case INTR_MAP_DATA_FDT: 1141 return (bcm_gpio_pic_map_fdt(sc, 1142 (struct intr_map_data_fdt *)data, irqp, modep)); 1143 case INTR_MAP_DATA_GPIO: 1144 return (bcm_gpio_pic_map_gpio(sc, 1145 (struct intr_map_data_gpio *)data, irqp, modep)); 1146 default: 1147 return (ENOTSUP); 1148 } 1149 } 1150 1151 static int 1152 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1153 struct intr_irqsrc **isrcp) 1154 { 1155 int error; 1156 u_int irq; 1157 struct bcm_gpio_softc *sc = device_get_softc(dev); 1158 1159 error = bcm_gpio_pic_map(sc, data, &irq, NULL); 1160 if (error == 0) 1161 *isrcp = &sc->sc_isrcs[irq].bgi_isrc; 1162 return (error); 1163 } 1164 1165 static void 1166 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1167 { 1168 struct bcm_gpio_softc *sc = device_get_softc(dev); 1169 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1170 1171 if (bcm_gpio_isrc_is_level(bgi)) 1172 bcm_gpio_isrc_eoi(sc, bgi); 1173 } 1174 1175 static void 1176 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1177 { 1178 1179 bcm_gpio_pic_enable_intr(dev, isrc); 1180 } 1181 1182 static void 1183 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1184 { 1185 struct bcm_gpio_softc *sc = device_get_softc(dev); 1186 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1187 1188 bcm_gpio_isrc_mask(sc, bgi); 1189 if (bcm_gpio_isrc_is_level(bgi)) 1190 bcm_gpio_isrc_eoi(sc, bgi); 1191 } 1192 1193 static int 1194 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1195 struct resource *res, struct intr_map_data *data) 1196 { 1197 u_int irq; 1198 uint32_t mode; 1199 struct bcm_gpio_softc *sc; 1200 struct bcm_gpio_irqsrc *bgi; 1201 1202 if (data == NULL) 1203 return (ENOTSUP); 1204 1205 sc = device_get_softc(dev); 1206 bgi = (struct bcm_gpio_irqsrc *)isrc; 1207 1208 /* Get and check config for an interrupt. */ 1209 if (bcm_gpio_pic_map(sc, data, &irq, &mode) != 0 || bgi->bgi_irq != irq) 1210 return (EINVAL); 1211 1212 /* 1213 * If this is a setup for another handler, 1214 * only check that its configuration match. 1215 */ 1216 if (isrc->isrc_handlers != 0) 1217 return (bgi->bgi_mode == mode ? 0 : EINVAL); 1218 1219 bcm_gpio_pic_config_intr(sc, bgi, mode); 1220 return (0); 1221 } 1222 1223 static int 1224 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1225 struct resource *res, struct intr_map_data *data) 1226 { 1227 struct bcm_gpio_softc *sc = device_get_softc(dev); 1228 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1229 1230 if (isrc->isrc_handlers == 0) 1231 bcm_gpio_pic_config_intr(sc, bgi, GPIO_INTR_CONFORM); 1232 return (0); 1233 } 1234 1235 static phandle_t 1236 bcm_gpio_get_node(device_t bus, device_t dev) 1237 { 1238 1239 /* We only have one child, the GPIO bus, which needs our own node. */ 1240 return (ofw_bus_get_node(bus)); 1241 } 1242 1243 static int 1244 bcm_gpio_configure_pins(device_t dev, phandle_t cfgxref) 1245 { 1246 phandle_t cfgnode; 1247 int i, pintuples, pulltuples; 1248 uint32_t pin; 1249 uint32_t *pins; 1250 uint32_t *pulls; 1251 uint32_t function; 1252 1253 cfgnode = OF_node_from_xref(cfgxref); 1254 1255 pins = NULL; 1256 pintuples = OF_getencprop_alloc_multi(cfgnode, "brcm,pins", 1257 sizeof(*pins), (void **)&pins); 1258 1259 char name[32]; 1260 OF_getprop(cfgnode, "name", &name, sizeof(name)); 1261 1262 if (pintuples < 0) 1263 return (ENOENT); 1264 1265 if (pintuples == 0) 1266 return (0); /* Empty property is not an error. */ 1267 1268 if (OF_getencprop(cfgnode, "brcm,function", &function, 1269 sizeof(function)) <= 0) { 1270 OF_prop_free(pins); 1271 return (EINVAL); 1272 } 1273 1274 pulls = NULL; 1275 pulltuples = OF_getencprop_alloc_multi(cfgnode, "brcm,pull", 1276 sizeof(*pulls), (void **)&pulls); 1277 1278 if ((pulls != NULL) && (pulltuples != pintuples)) { 1279 OF_prop_free(pins); 1280 OF_prop_free(pulls); 1281 return (EINVAL); 1282 } 1283 1284 for (i = 0; i < pintuples; i++) { 1285 pin = pins[i]; 1286 bcm_gpio_set_alternate(dev, pin, function); 1287 if (bootverbose) 1288 device_printf(dev, "set pin %d to func %d", pin, function); 1289 if (pulls) { 1290 if (bootverbose) 1291 printf(", pull %d", pulls[i]); 1292 switch (pulls[i]) { 1293 /* Convert to gpio(4) flags */ 1294 case BCM2835_PUD_OFF: 1295 bcm_gpio_pin_setflags(dev, pin, 0); 1296 break; 1297 case BCM2835_PUD_UP: 1298 bcm_gpio_pin_setflags(dev, pin, GPIO_PIN_PULLUP); 1299 break; 1300 case BCM2835_PUD_DOWN: 1301 bcm_gpio_pin_setflags(dev, pin, GPIO_PIN_PULLDOWN); 1302 break; 1303 default: 1304 printf("%s: invalid pull value for pin %d: %d\n", 1305 name, pin, pulls[i]); 1306 } 1307 } 1308 if (bootverbose) 1309 printf("\n"); 1310 } 1311 1312 OF_prop_free(pins); 1313 if (pulls) 1314 OF_prop_free(pulls); 1315 1316 return (0); 1317 } 1318 1319 static device_method_t bcm_gpio_methods[] = { 1320 /* Device interface */ 1321 DEVMETHOD(device_probe, bcm_gpio_probe), 1322 DEVMETHOD(device_attach, bcm_gpio_attach), 1323 DEVMETHOD(device_detach, bcm_gpio_detach), 1324 1325 /* GPIO protocol */ 1326 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus), 1327 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max), 1328 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname), 1329 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags), 1330 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps), 1331 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags), 1332 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get), 1333 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set), 1334 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle), 1335 1336 /* Interrupt controller interface */ 1337 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr), 1338 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr), 1339 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr), 1340 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter), 1341 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread), 1342 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread), 1343 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr), 1344 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr), 1345 1346 /* ofw_bus interface */ 1347 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node), 1348 1349 /* fdt_pinctrl interface */ 1350 DEVMETHOD(fdt_pinctrl_configure, bcm_gpio_configure_pins), 1351 1352 DEVMETHOD_END 1353 }; 1354 1355 static driver_t bcm_gpio_driver = { 1356 "gpio", 1357 bcm_gpio_methods, 1358 sizeof(struct bcm_gpio_softc), 1359 }; 1360 1361 EARLY_DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, 0, 0, 1362 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 1363