1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_platform.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/gpio.h> 37 #include <sys/interrupt.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/gpio/gpiobusvar.h> 50 #include <dev/ofw/ofw_bus.h> 51 52 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 53 54 #include "gpio_if.h" 55 56 #ifdef INTRNG 57 #include "pic_if.h" 58 #endif 59 60 #ifdef DEBUG 61 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 62 printf(fmt,##args); } while (0) 63 #else 64 #define dprintf(fmt, args...) 65 #endif 66 67 #define BCM_GPIO_IRQS 4 68 #define BCM_GPIO_PINS 54 69 #define BCM_GPIO_PINS_PER_BANK 32 70 71 #ifdef INTRNG 72 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 73 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | \ 74 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 75 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 76 #else 77 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 78 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) 79 #endif 80 81 static struct resource_spec bcm_gpio_res_spec[] = { 82 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 83 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */ 84 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */ 85 { -1, 0, 0 } 86 }; 87 88 struct bcm_gpio_sysctl { 89 struct bcm_gpio_softc *sc; 90 uint32_t pin; 91 }; 92 93 #ifdef INTRNG 94 struct bcm_gpio_irqsrc { 95 struct intr_irqsrc bgi_isrc; 96 uint32_t bgi_irq; 97 uint32_t bgi_mode; 98 uint32_t bgi_mask; 99 }; 100 #endif 101 102 struct bcm_gpio_softc { 103 device_t sc_dev; 104 device_t sc_busdev; 105 struct mtx sc_mtx; 106 struct resource * sc_res[BCM_GPIO_IRQS + 1]; 107 bus_space_tag_t sc_bst; 108 bus_space_handle_t sc_bsh; 109 void * sc_intrhand[BCM_GPIO_IRQS]; 110 int sc_gpio_npins; 111 int sc_ro_npins; 112 int sc_ro_pins[BCM_GPIO_PINS]; 113 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS]; 114 #ifndef INTRNG 115 struct intr_event * sc_events[BCM_GPIO_PINS]; 116 #endif 117 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS]; 118 #ifdef INTRNG 119 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS]; 120 #else 121 enum intr_trigger sc_irq_trigger[BCM_GPIO_PINS]; 122 enum intr_polarity sc_irq_polarity[BCM_GPIO_PINS]; 123 #endif 124 }; 125 126 enum bcm_gpio_pud { 127 BCM_GPIO_NONE, 128 BCM_GPIO_PULLDOWN, 129 BCM_GPIO_PULLUP, 130 }; 131 132 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 133 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 134 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 135 #define BCM_GPIO_WRITE(_sc, _off, _val) \ 136 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val) 137 #define BCM_GPIO_READ(_sc, _off) \ 138 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off) 139 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \ 140 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits)) 141 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \ 142 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits) 143 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK) 144 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK)) 145 146 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */ 147 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */ 148 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */ 149 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */ 150 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */ 151 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */ 152 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */ 153 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */ 154 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */ 155 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */ 156 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */ 157 #define BCM_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */ 158 #define BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */ 159 160 static struct ofw_compat_data compat_data[] = { 161 {"broadcom,bcm2835-gpio", 1}, 162 {"brcm,bcm2835-gpio", 1}, 163 {NULL, 0} 164 }; 165 166 static struct bcm_gpio_softc *bcm_gpio_sc = NULL; 167 168 #ifdef INTRNG 169 static int bcm_gpio_intr_bank0(void *arg); 170 static int bcm_gpio_intr_bank1(void *arg); 171 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc); 172 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc); 173 #endif 174 175 static int 176 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin) 177 { 178 int i; 179 180 for (i = 0; i < sc->sc_ro_npins; i++) 181 if (pin == sc->sc_ro_pins[i]) 182 return (1); 183 return (0); 184 } 185 186 static uint32_t 187 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin) 188 { 189 uint32_t bank, func, offset; 190 191 /* Five banks, 10 pins per bank, 3 bits per pin. */ 192 bank = pin / 10; 193 offset = (pin - bank * 10) * 3; 194 195 BCM_GPIO_LOCK(sc); 196 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7; 197 BCM_GPIO_UNLOCK(sc); 198 199 return (func); 200 } 201 202 static void 203 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize) 204 { 205 206 switch (nfunc) { 207 case BCM_GPIO_INPUT: 208 strncpy(buf, "input", bufsize); 209 break; 210 case BCM_GPIO_OUTPUT: 211 strncpy(buf, "output", bufsize); 212 break; 213 case BCM_GPIO_ALT0: 214 strncpy(buf, "alt0", bufsize); 215 break; 216 case BCM_GPIO_ALT1: 217 strncpy(buf, "alt1", bufsize); 218 break; 219 case BCM_GPIO_ALT2: 220 strncpy(buf, "alt2", bufsize); 221 break; 222 case BCM_GPIO_ALT3: 223 strncpy(buf, "alt3", bufsize); 224 break; 225 case BCM_GPIO_ALT4: 226 strncpy(buf, "alt4", bufsize); 227 break; 228 case BCM_GPIO_ALT5: 229 strncpy(buf, "alt5", bufsize); 230 break; 231 default: 232 strncpy(buf, "invalid", bufsize); 233 } 234 } 235 236 static int 237 bcm_gpio_str_func(char *func, uint32_t *nfunc) 238 { 239 240 if (strcasecmp(func, "input") == 0) 241 *nfunc = BCM_GPIO_INPUT; 242 else if (strcasecmp(func, "output") == 0) 243 *nfunc = BCM_GPIO_OUTPUT; 244 else if (strcasecmp(func, "alt0") == 0) 245 *nfunc = BCM_GPIO_ALT0; 246 else if (strcasecmp(func, "alt1") == 0) 247 *nfunc = BCM_GPIO_ALT1; 248 else if (strcasecmp(func, "alt2") == 0) 249 *nfunc = BCM_GPIO_ALT2; 250 else if (strcasecmp(func, "alt3") == 0) 251 *nfunc = BCM_GPIO_ALT3; 252 else if (strcasecmp(func, "alt4") == 0) 253 *nfunc = BCM_GPIO_ALT4; 254 else if (strcasecmp(func, "alt5") == 0) 255 *nfunc = BCM_GPIO_ALT5; 256 else 257 return (-1); 258 259 return (0); 260 } 261 262 static uint32_t 263 bcm_gpio_func_flag(uint32_t nfunc) 264 { 265 266 switch (nfunc) { 267 case BCM_GPIO_INPUT: 268 return (GPIO_PIN_INPUT); 269 case BCM_GPIO_OUTPUT: 270 return (GPIO_PIN_OUTPUT); 271 } 272 return (0); 273 } 274 275 static void 276 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f) 277 { 278 uint32_t bank, data, offset; 279 280 /* Must be called with lock held. */ 281 BCM_GPIO_LOCK_ASSERT(sc); 282 283 /* Five banks, 10 pins per bank, 3 bits per pin. */ 284 bank = pin / 10; 285 offset = (pin - bank * 10) * 3; 286 287 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)); 288 data &= ~(7 << offset); 289 data |= (f << offset); 290 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data); 291 } 292 293 static void 294 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state) 295 { 296 uint32_t bank; 297 298 /* Must be called with lock held. */ 299 BCM_GPIO_LOCK_ASSERT(sc); 300 301 bank = BCM_GPIO_BANK(pin); 302 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), state); 303 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin)); 304 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), 0); 305 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), 0); 306 } 307 308 void 309 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc) 310 { 311 struct bcm_gpio_softc *sc; 312 int i; 313 314 sc = device_get_softc(dev); 315 BCM_GPIO_LOCK(sc); 316 317 /* Disable pull-up or pull-down on pin. */ 318 bcm_gpio_set_pud(sc, pin, BCM_GPIO_NONE); 319 320 /* And now set the pin function. */ 321 bcm_gpio_set_function(sc, pin, nfunc); 322 323 /* Update the pin flags. */ 324 for (i = 0; i < sc->sc_gpio_npins; i++) { 325 if (sc->sc_gpio_pins[i].gp_pin == pin) 326 break; 327 } 328 if (i < sc->sc_gpio_npins) 329 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc); 330 331 BCM_GPIO_UNLOCK(sc); 332 } 333 334 static void 335 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin, 336 unsigned int flags) 337 { 338 339 BCM_GPIO_LOCK(sc); 340 341 /* 342 * Manage input/output. 343 */ 344 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 345 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); 346 if (flags & GPIO_PIN_OUTPUT) { 347 pin->gp_flags |= GPIO_PIN_OUTPUT; 348 bcm_gpio_set_function(sc, pin->gp_pin, 349 BCM_GPIO_OUTPUT); 350 } else { 351 pin->gp_flags |= GPIO_PIN_INPUT; 352 bcm_gpio_set_function(sc, pin->gp_pin, 353 BCM_GPIO_INPUT); 354 } 355 } 356 357 /* Manage Pull-up/pull-down. */ 358 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN); 359 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 360 if (flags & GPIO_PIN_PULLUP) { 361 pin->gp_flags |= GPIO_PIN_PULLUP; 362 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP); 363 } else { 364 pin->gp_flags |= GPIO_PIN_PULLDOWN; 365 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN); 366 } 367 } else 368 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE); 369 370 BCM_GPIO_UNLOCK(sc); 371 } 372 373 static device_t 374 bcm_gpio_get_bus(device_t dev) 375 { 376 struct bcm_gpio_softc *sc; 377 378 sc = device_get_softc(dev); 379 380 return (sc->sc_busdev); 381 } 382 383 static int 384 bcm_gpio_pin_max(device_t dev, int *maxpin) 385 { 386 387 *maxpin = BCM_GPIO_PINS - 1; 388 return (0); 389 } 390 391 static int 392 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 393 { 394 struct bcm_gpio_softc *sc = device_get_softc(dev); 395 int i; 396 397 for (i = 0; i < sc->sc_gpio_npins; i++) { 398 if (sc->sc_gpio_pins[i].gp_pin == pin) 399 break; 400 } 401 402 if (i >= sc->sc_gpio_npins) 403 return (EINVAL); 404 405 BCM_GPIO_LOCK(sc); 406 *caps = sc->sc_gpio_pins[i].gp_caps; 407 BCM_GPIO_UNLOCK(sc); 408 409 return (0); 410 } 411 412 static int 413 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 414 { 415 struct bcm_gpio_softc *sc = device_get_softc(dev); 416 int i; 417 418 for (i = 0; i < sc->sc_gpio_npins; i++) { 419 if (sc->sc_gpio_pins[i].gp_pin == pin) 420 break; 421 } 422 423 if (i >= sc->sc_gpio_npins) 424 return (EINVAL); 425 426 BCM_GPIO_LOCK(sc); 427 *flags = sc->sc_gpio_pins[i].gp_flags; 428 BCM_GPIO_UNLOCK(sc); 429 430 return (0); 431 } 432 433 static int 434 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 435 { 436 struct bcm_gpio_softc *sc = device_get_softc(dev); 437 int i; 438 439 for (i = 0; i < sc->sc_gpio_npins; i++) { 440 if (sc->sc_gpio_pins[i].gp_pin == pin) 441 break; 442 } 443 444 if (i >= sc->sc_gpio_npins) 445 return (EINVAL); 446 447 BCM_GPIO_LOCK(sc); 448 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME); 449 BCM_GPIO_UNLOCK(sc); 450 451 return (0); 452 } 453 454 static int 455 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 456 { 457 struct bcm_gpio_softc *sc = device_get_softc(dev); 458 int i; 459 460 for (i = 0; i < sc->sc_gpio_npins; i++) { 461 if (sc->sc_gpio_pins[i].gp_pin == pin) 462 break; 463 } 464 465 if (i >= sc->sc_gpio_npins) 466 return (EINVAL); 467 468 /* We never touch on read-only/reserved pins. */ 469 if (bcm_gpio_pin_is_ro(sc, pin)) 470 return (EINVAL); 471 472 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags); 473 474 return (0); 475 } 476 477 static int 478 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 479 { 480 struct bcm_gpio_softc *sc = device_get_softc(dev); 481 uint32_t bank, reg; 482 int i; 483 484 for (i = 0; i < sc->sc_gpio_npins; i++) { 485 if (sc->sc_gpio_pins[i].gp_pin == pin) 486 break; 487 } 488 if (i >= sc->sc_gpio_npins) 489 return (EINVAL); 490 /* We never write to read-only/reserved pins. */ 491 if (bcm_gpio_pin_is_ro(sc, pin)) 492 return (EINVAL); 493 BCM_GPIO_LOCK(sc); 494 bank = BCM_GPIO_BANK(pin); 495 if (value) 496 reg = BCM_GPIO_GPSET(bank); 497 else 498 reg = BCM_GPIO_GPCLR(bank); 499 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 500 BCM_GPIO_UNLOCK(sc); 501 502 return (0); 503 } 504 505 static int 506 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 507 { 508 struct bcm_gpio_softc *sc = device_get_softc(dev); 509 uint32_t bank, reg_data; 510 int i; 511 512 for (i = 0; i < sc->sc_gpio_npins; i++) { 513 if (sc->sc_gpio_pins[i].gp_pin == pin) 514 break; 515 } 516 if (i >= sc->sc_gpio_npins) 517 return (EINVAL); 518 bank = BCM_GPIO_BANK(pin); 519 BCM_GPIO_LOCK(sc); 520 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 521 BCM_GPIO_UNLOCK(sc); 522 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0; 523 524 return (0); 525 } 526 527 static int 528 bcm_gpio_pin_toggle(device_t dev, uint32_t pin) 529 { 530 struct bcm_gpio_softc *sc = device_get_softc(dev); 531 uint32_t bank, data, reg; 532 int i; 533 534 for (i = 0; i < sc->sc_gpio_npins; i++) { 535 if (sc->sc_gpio_pins[i].gp_pin == pin) 536 break; 537 } 538 if (i >= sc->sc_gpio_npins) 539 return (EINVAL); 540 /* We never write to read-only/reserved pins. */ 541 if (bcm_gpio_pin_is_ro(sc, pin)) 542 return (EINVAL); 543 BCM_GPIO_LOCK(sc); 544 bank = BCM_GPIO_BANK(pin); 545 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 546 if (data & BCM_GPIO_MASK(pin)) 547 reg = BCM_GPIO_GPCLR(bank); 548 else 549 reg = BCM_GPIO_GPSET(bank); 550 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 551 BCM_GPIO_UNLOCK(sc); 552 553 return (0); 554 } 555 556 static int 557 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS) 558 { 559 char buf[16]; 560 struct bcm_gpio_softc *sc; 561 struct bcm_gpio_sysctl *sc_sysctl; 562 uint32_t nfunc; 563 int error; 564 565 sc_sysctl = arg1; 566 sc = sc_sysctl->sc; 567 568 /* Get the current pin function. */ 569 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin); 570 bcm_gpio_func_str(nfunc, buf, sizeof(buf)); 571 572 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 573 if (error != 0 || req->newptr == NULL) 574 return (error); 575 /* Ignore changes on read-only pins. */ 576 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin)) 577 return (0); 578 /* Parse the user supplied string and check for a valid pin function. */ 579 if (bcm_gpio_str_func(buf, &nfunc) != 0) 580 return (EINVAL); 581 582 /* Update the pin alternate function. */ 583 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc); 584 585 return (0); 586 } 587 588 static void 589 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc) 590 { 591 char pinbuf[3]; 592 struct bcm_gpio_sysctl *sc_sysctl; 593 struct sysctl_ctx_list *ctx; 594 struct sysctl_oid *tree_node, *pin_node, *pinN_node; 595 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree; 596 int i; 597 598 /* 599 * Add per-pin sysctl tree/handlers. 600 */ 601 ctx = device_get_sysctl_ctx(sc->sc_dev); 602 tree_node = device_get_sysctl_tree(sc->sc_dev); 603 tree = SYSCTL_CHILDREN(tree_node); 604 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin", 605 CTLFLAG_RD, NULL, "GPIO Pins"); 606 pin_tree = SYSCTL_CHILDREN(pin_node); 607 608 for (i = 0; i < sc->sc_gpio_npins; i++) { 609 610 snprintf(pinbuf, sizeof(pinbuf), "%d", i); 611 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf, 612 CTLFLAG_RD, NULL, "GPIO Pin"); 613 pinN_tree = SYSCTL_CHILDREN(pinN_node); 614 615 sc->sc_sysctl[i].sc = sc; 616 sc_sysctl = &sc->sc_sysctl[i]; 617 sc_sysctl->sc = sc; 618 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin; 619 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function", 620 CTLFLAG_RW | CTLTYPE_STRING, sc_sysctl, 621 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc, 622 "A", "Pin Function"); 623 } 624 } 625 626 static int 627 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node, 628 const char *propname, const char *label) 629 { 630 int i, need_comma, npins, range_start, range_stop; 631 pcell_t *pins; 632 633 /* Get the property data. */ 634 npins = OF_getencprop_alloc(node, propname, sizeof(*pins), 635 (void **)&pins); 636 if (npins < 0) 637 return (-1); 638 if (npins == 0) { 639 OF_prop_free(pins); 640 return (0); 641 } 642 for (i = 0; i < npins; i++) 643 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i]; 644 sc->sc_ro_npins += npins; 645 need_comma = 0; 646 device_printf(sc->sc_dev, "%s pins: ", label); 647 range_start = range_stop = pins[0]; 648 for (i = 1; i < npins; i++) { 649 if (pins[i] != range_stop + 1) { 650 if (need_comma) 651 printf(","); 652 if (range_start != range_stop) 653 printf("%d-%d", range_start, range_stop); 654 else 655 printf("%d", range_start); 656 range_start = range_stop = pins[i]; 657 need_comma = 1; 658 } else 659 range_stop++; 660 } 661 if (need_comma) 662 printf(","); 663 if (range_start != range_stop) 664 printf("%d-%d.\n", range_start, range_stop); 665 else 666 printf("%d.\n", range_start); 667 OF_prop_free(pins); 668 669 return (0); 670 } 671 672 static int 673 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc) 674 { 675 char *name; 676 phandle_t gpio, node, reserved; 677 ssize_t len; 678 679 /* Get read-only pins if they're provided */ 680 gpio = ofw_bus_get_node(sc->sc_dev); 681 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only", 682 "read-only") != 0) 683 return (0); 684 /* Traverse the GPIO subnodes to find the reserved pins node. */ 685 reserved = 0; 686 node = OF_child(gpio); 687 while ((node != 0) && (reserved == 0)) { 688 len = OF_getprop_alloc(node, "name", 1, (void **)&name); 689 if (len == -1) 690 return (-1); 691 if (strcmp(name, "reserved") == 0) 692 reserved = node; 693 OF_prop_free(name); 694 node = OF_peer(node); 695 } 696 if (reserved == 0) 697 return (-1); 698 /* Get the reserved pins. */ 699 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins", 700 "reserved") != 0) 701 return (-1); 702 703 return (0); 704 } 705 706 #ifndef INTRNG 707 static int 708 bcm_gpio_intr(void *arg) 709 { 710 int bank_last, irq; 711 struct bcm_gpio_softc *sc; 712 struct intr_event *event; 713 uint32_t bank, mask, reg; 714 715 sc = (struct bcm_gpio_softc *)arg; 716 reg = 0; 717 bank_last = -1; 718 for (irq = 0; irq < BCM_GPIO_PINS; irq++) { 719 bank = BCM_GPIO_BANK(irq); 720 mask = BCM_GPIO_MASK(irq); 721 if (bank != bank_last) { 722 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); 723 bank_last = bank; 724 } 725 if (reg & mask) { 726 event = sc->sc_events[irq]; 727 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers)) 728 intr_event_handle(event, NULL); 729 else { 730 device_printf(sc->sc_dev, "Stray IRQ %d\n", 731 irq); 732 } 733 /* Clear the Status bit by writing '1' to it. */ 734 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), mask); 735 } 736 } 737 738 return (FILTER_HANDLED); 739 } 740 #endif 741 742 static int 743 bcm_gpio_probe(device_t dev) 744 { 745 746 if (!ofw_bus_status_okay(dev)) 747 return (ENXIO); 748 749 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 750 return (ENXIO); 751 752 device_set_desc(dev, "BCM2708/2835 GPIO controller"); 753 return (BUS_PROBE_DEFAULT); 754 } 755 756 #ifdef INTRNG 757 static int 758 bcm_gpio_intr_attach(device_t dev) 759 { 760 struct bcm_gpio_softc *sc; 761 762 /* 763 * Only first two interrupt lines are used. Third line is 764 * mirrored second line and forth line is common for all banks. 765 */ 766 sc = device_get_softc(dev); 767 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL) 768 return (-1); 769 770 if (bcm_gpio_pic_attach(sc) != 0) { 771 device_printf(dev, "unable to attach PIC\n"); 772 return (-1); 773 } 774 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE, 775 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0) 776 return (-1); 777 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE, 778 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0) 779 return (-1); 780 781 return (0); 782 } 783 784 static void 785 bcm_gpio_intr_detach(device_t dev) 786 { 787 struct bcm_gpio_softc *sc; 788 789 sc = device_get_softc(dev); 790 if (sc->sc_intrhand[0] != NULL) 791 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]); 792 if (sc->sc_intrhand[1] != NULL) 793 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]); 794 795 bcm_gpio_pic_detach(sc); 796 } 797 798 #else 799 static int 800 bcm_gpio_intr_attach(device_t dev) 801 { 802 struct bcm_gpio_softc *sc; 803 int i; 804 805 sc = device_get_softc(dev); 806 for (i = 0; i < BCM_GPIO_IRQS; i++) { 807 if (bus_setup_intr(dev, sc->sc_res[i + 1], 808 INTR_TYPE_MISC | INTR_MPSAFE, bcm_gpio_intr, 809 NULL, sc, &sc->sc_intrhand[i]) != 0) { 810 return (-1); 811 } 812 } 813 814 return (0); 815 } 816 817 static void 818 bcm_gpio_intr_detach(device_t dev) 819 { 820 struct bcm_gpio_softc *sc; 821 int i; 822 823 sc = device_get_softc(dev); 824 for (i = 0; i < BCM_GPIO_IRQS; i++) { 825 if (sc->sc_intrhand[i]) { 826 bus_teardown_intr(dev, sc->sc_res[i + 1], 827 sc->sc_intrhand[i]); 828 } 829 } 830 } 831 #endif 832 833 static int 834 bcm_gpio_attach(device_t dev) 835 { 836 int i, j; 837 phandle_t gpio; 838 struct bcm_gpio_softc *sc; 839 uint32_t func; 840 841 if (bcm_gpio_sc != NULL) 842 return (ENXIO); 843 844 bcm_gpio_sc = sc = device_get_softc(dev); 845 sc->sc_dev = dev; 846 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN); 847 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) { 848 device_printf(dev, "cannot allocate resources\n"); 849 goto fail; 850 } 851 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 852 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 853 /* Setup the GPIO interrupt handler. */ 854 if (bcm_gpio_intr_attach(dev)) { 855 device_printf(dev, "unable to setup the gpio irq handler\n"); 856 goto fail; 857 } 858 /* Find our node. */ 859 gpio = ofw_bus_get_node(sc->sc_dev); 860 if (!OF_hasprop(gpio, "gpio-controller")) 861 /* Node is not a GPIO controller. */ 862 goto fail; 863 /* 864 * Find the read-only pins. These are pins we never touch or bad 865 * things could happen. 866 */ 867 if (bcm_gpio_get_reserved_pins(sc) == -1) 868 goto fail; 869 /* Initialize the software controlled pins. */ 870 for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) { 871 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, 872 "pin %d", j); 873 func = bcm_gpio_get_function(sc, j); 874 sc->sc_gpio_pins[i].gp_pin = j; 875 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS; 876 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func); 877 #ifndef INTRNG 878 /* The default is active-low interrupts. */ 879 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL; 880 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW; 881 #endif 882 i++; 883 } 884 sc->sc_gpio_npins = i; 885 bcm_gpio_sysctl_init(sc); 886 sc->sc_busdev = gpiobus_attach_bus(dev); 887 if (sc->sc_busdev == NULL) 888 goto fail; 889 890 return (0); 891 892 fail: 893 bcm_gpio_intr_detach(dev); 894 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res); 895 mtx_destroy(&sc->sc_mtx); 896 897 return (ENXIO); 898 } 899 900 static int 901 bcm_gpio_detach(device_t dev) 902 { 903 904 return (EBUSY); 905 } 906 907 #ifdef INTRNG 908 static inline void 909 bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask, 910 bool set_bits) 911 { 912 913 if (set_bits) 914 BCM_GPIO_SET_BITS(sc, reg, mask); 915 else 916 BCM_GPIO_CLEAR_BITS(sc, reg, mask); 917 } 918 919 static inline void 920 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 921 { 922 uint32_t bank; 923 924 /* Write 1 to clear. */ 925 bank = BCM_GPIO_BANK(bgi->bgi_irq); 926 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask); 927 } 928 929 static inline bool 930 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi) 931 { 932 933 return (bgi->bgi_mode == GPIO_INTR_LEVEL_LOW || 934 bgi->bgi_mode == GPIO_INTR_LEVEL_HIGH); 935 } 936 937 static inline void 938 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 939 { 940 uint32_t bank; 941 942 bank = BCM_GPIO_BANK(bgi->bgi_irq); 943 BCM_GPIO_LOCK(sc); 944 switch (bgi->bgi_mode) { 945 case GPIO_INTR_LEVEL_LOW: 946 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 947 break; 948 case GPIO_INTR_LEVEL_HIGH: 949 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 950 break; 951 case GPIO_INTR_EDGE_RISING: 952 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 953 break; 954 case GPIO_INTR_EDGE_FALLING: 955 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 956 break; 957 case GPIO_INTR_EDGE_BOTH: 958 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 959 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 960 break; 961 } 962 BCM_GPIO_UNLOCK(sc); 963 } 964 965 static inline void 966 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 967 { 968 uint32_t bank; 969 970 bank = BCM_GPIO_BANK(bgi->bgi_irq); 971 BCM_GPIO_LOCK(sc); 972 switch (bgi->bgi_mode) { 973 case GPIO_INTR_LEVEL_LOW: 974 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 975 break; 976 case GPIO_INTR_LEVEL_HIGH: 977 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 978 break; 979 case GPIO_INTR_EDGE_RISING: 980 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 981 break; 982 case GPIO_INTR_EDGE_FALLING: 983 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 984 break; 985 case GPIO_INTR_EDGE_BOTH: 986 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 987 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 988 break; 989 } 990 BCM_GPIO_UNLOCK(sc); 991 } 992 993 static int 994 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank) 995 { 996 u_int irq; 997 struct bcm_gpio_irqsrc *bgi; 998 uint32_t reg; 999 1000 /* Do not care of spurious interrupt on GPIO. */ 1001 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); 1002 while (reg != 0) { 1003 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1; 1004 bgi = sc->sc_isrcs + irq; 1005 if (!bcm_gpio_isrc_is_level(bgi)) 1006 bcm_gpio_isrc_eoi(sc, bgi); 1007 if (intr_isrc_dispatch(&bgi->bgi_isrc, 1008 curthread->td_intr_frame) != 0) { 1009 bcm_gpio_isrc_mask(sc, bgi); 1010 if (bcm_gpio_isrc_is_level(bgi)) 1011 bcm_gpio_isrc_eoi(sc, bgi); 1012 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 1013 irq); 1014 } 1015 reg &= ~bgi->bgi_mask; 1016 } 1017 return (FILTER_HANDLED); 1018 } 1019 1020 static int 1021 bcm_gpio_intr_bank0(void *arg) 1022 { 1023 1024 return (bcm_gpio_intr_internal(arg, 0)); 1025 } 1026 1027 static int 1028 bcm_gpio_intr_bank1(void *arg) 1029 { 1030 1031 return (bcm_gpio_intr_internal(arg, 1)); 1032 } 1033 1034 static int 1035 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc) 1036 { 1037 int error; 1038 uint32_t irq; 1039 const char *name; 1040 1041 name = device_get_nameunit(sc->sc_dev); 1042 for (irq = 0; irq < BCM_GPIO_PINS; irq++) { 1043 sc->sc_isrcs[irq].bgi_irq = irq; 1044 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq); 1045 sc->sc_isrcs[irq].bgi_mode = GPIO_INTR_CONFORM; 1046 1047 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc, 1048 sc->sc_dev, 0, "%s,%u", name, irq); 1049 if (error != 0) 1050 return (error); /* XXX deregister ISRCs */ 1051 } 1052 if (intr_pic_register(sc->sc_dev, 1053 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 1054 return (ENXIO); 1055 1056 return (0); 1057 } 1058 1059 static int 1060 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc) 1061 { 1062 1063 /* 1064 * There has not been established any procedure yet 1065 * how to detach PIC from living system correctly. 1066 */ 1067 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 1068 return (EBUSY); 1069 } 1070 1071 static void 1072 bcm_gpio_pic_config_intr(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi, 1073 uint32_t mode) 1074 { 1075 uint32_t bank; 1076 1077 bank = BCM_GPIO_BANK(bgi->bgi_irq); 1078 BCM_GPIO_LOCK(sc); 1079 bcm_gpio_modify(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask, 1080 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 1081 bcm_gpio_modify(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask, 1082 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 1083 bcm_gpio_modify(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask, 1084 mode == GPIO_INTR_LEVEL_HIGH); 1085 bcm_gpio_modify(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask, 1086 mode == GPIO_INTR_LEVEL_LOW); 1087 bgi->bgi_mode = mode; 1088 BCM_GPIO_UNLOCK(sc); 1089 } 1090 1091 static void 1092 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 1093 { 1094 struct bcm_gpio_softc *sc = device_get_softc(dev); 1095 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1096 1097 bcm_gpio_isrc_mask(sc, bgi); 1098 } 1099 1100 static void 1101 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 1102 { 1103 struct bcm_gpio_softc *sc = device_get_softc(dev); 1104 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1105 1106 arm_irq_memory_barrier(bgi->bgi_irq); 1107 bcm_gpio_isrc_unmask(sc, bgi); 1108 } 1109 1110 static int 1111 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf, 1112 u_int *irqp, uint32_t *modep) 1113 { 1114 u_int irq; 1115 uint32_t mode, bank; 1116 1117 /* 1118 * The first cell is the interrupt number. 1119 * The second cell is used to specify flags: 1120 * bits[3:0] trigger type and level flags: 1121 * 1 = low-to-high edge triggered. 1122 * 2 = high-to-low edge triggered. 1123 * 4 = active high level-sensitive. 1124 * 8 = active low level-sensitive. 1125 */ 1126 if (daf->ncells != 2) 1127 return (EINVAL); 1128 1129 irq = daf->cells[0]; 1130 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1131 return (EINVAL); 1132 1133 /* Only reasonable modes are supported. */ 1134 bank = BCM_GPIO_BANK(irq); 1135 if (daf->cells[1] == 1) 1136 mode = GPIO_INTR_EDGE_RISING; 1137 else if (daf->cells[1] == 2) 1138 mode = GPIO_INTR_EDGE_FALLING; 1139 else if (daf->cells[1] == 3) 1140 mode = GPIO_INTR_EDGE_BOTH; 1141 else if (daf->cells[1] == 4) 1142 mode = GPIO_INTR_LEVEL_HIGH; 1143 else if (daf->cells[1] == 8) 1144 mode = GPIO_INTR_LEVEL_LOW; 1145 else 1146 return (EINVAL); 1147 1148 *irqp = irq; 1149 if (modep != NULL) 1150 *modep = mode; 1151 return (0); 1152 } 1153 1154 static int 1155 bcm_gpio_pic_map_gpio(struct bcm_gpio_softc *sc, struct intr_map_data_gpio *dag, 1156 u_int *irqp, uint32_t *modep) 1157 { 1158 u_int irq; 1159 uint32_t mode; 1160 1161 irq = dag->gpio_pin_num; 1162 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1163 return (EINVAL); 1164 1165 mode = dag->gpio_intr_mode; 1166 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 1167 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 1168 mode != GPIO_INTR_EDGE_BOTH) 1169 return (EINVAL); 1170 1171 *irqp = irq; 1172 if (modep != NULL) 1173 *modep = mode; 1174 return (0); 1175 } 1176 1177 static int 1178 bcm_gpio_pic_map(struct bcm_gpio_softc *sc, struct intr_map_data *data, 1179 u_int *irqp, uint32_t *modep) 1180 { 1181 1182 switch (data->type) { 1183 case INTR_MAP_DATA_FDT: 1184 return (bcm_gpio_pic_map_fdt(sc, 1185 (struct intr_map_data_fdt *)data, irqp, modep)); 1186 case INTR_MAP_DATA_GPIO: 1187 return (bcm_gpio_pic_map_gpio(sc, 1188 (struct intr_map_data_gpio *)data, irqp, modep)); 1189 default: 1190 return (ENOTSUP); 1191 } 1192 } 1193 1194 static int 1195 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1196 struct intr_irqsrc **isrcp) 1197 { 1198 int error; 1199 u_int irq; 1200 struct bcm_gpio_softc *sc = device_get_softc(dev); 1201 1202 error = bcm_gpio_pic_map(sc, data, &irq, NULL); 1203 if (error == 0) 1204 *isrcp = &sc->sc_isrcs[irq].bgi_isrc; 1205 return (error); 1206 } 1207 1208 static void 1209 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1210 { 1211 struct bcm_gpio_softc *sc = device_get_softc(dev); 1212 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1213 1214 if (bcm_gpio_isrc_is_level(bgi)) 1215 bcm_gpio_isrc_eoi(sc, bgi); 1216 } 1217 1218 static void 1219 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1220 { 1221 1222 bcm_gpio_pic_enable_intr(dev, isrc); 1223 } 1224 1225 static void 1226 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1227 { 1228 struct bcm_gpio_softc *sc = device_get_softc(dev); 1229 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1230 1231 bcm_gpio_isrc_mask(sc, bgi); 1232 if (bcm_gpio_isrc_is_level(bgi)) 1233 bcm_gpio_isrc_eoi(sc, bgi); 1234 } 1235 1236 static int 1237 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1238 struct resource *res, struct intr_map_data *data) 1239 { 1240 u_int irq; 1241 uint32_t mode; 1242 struct bcm_gpio_softc *sc; 1243 struct bcm_gpio_irqsrc *bgi; 1244 1245 if (data == NULL) 1246 return (ENOTSUP); 1247 1248 sc = device_get_softc(dev); 1249 bgi = (struct bcm_gpio_irqsrc *)isrc; 1250 1251 /* Get and check config for an interrupt. */ 1252 if (bcm_gpio_pic_map(sc, data, &irq, &mode) != 0 || bgi->bgi_irq != irq) 1253 return (EINVAL); 1254 1255 /* 1256 * If this is a setup for another handler, 1257 * only check that its configuration match. 1258 */ 1259 if (isrc->isrc_handlers != 0) 1260 return (bgi->bgi_mode == mode ? 0 : EINVAL); 1261 1262 bcm_gpio_pic_config_intr(sc, bgi, mode); 1263 return (0); 1264 } 1265 1266 static int 1267 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1268 struct resource *res, struct intr_map_data *data) 1269 { 1270 struct bcm_gpio_softc *sc = device_get_softc(dev); 1271 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1272 1273 if (isrc->isrc_handlers == 0) 1274 bcm_gpio_pic_config_intr(sc, bgi, GPIO_INTR_CONFORM); 1275 return (0); 1276 } 1277 1278 #else 1279 static uint32_t 1280 bcm_gpio_intr_reg(struct bcm_gpio_softc *sc, unsigned int irq, uint32_t bank) 1281 { 1282 1283 if (irq > BCM_GPIO_PINS) 1284 return (0); 1285 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) { 1286 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1287 return (BCM_GPIO_GPLEN(bank)); 1288 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1289 return (BCM_GPIO_GPHEN(bank)); 1290 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) { 1291 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1292 return (BCM_GPIO_GPFEN(bank)); 1293 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1294 return (BCM_GPIO_GPREN(bank)); 1295 } 1296 1297 return (0); 1298 } 1299 1300 static void 1301 bcm_gpio_mask_irq(void *source) 1302 { 1303 uint32_t bank, mask, reg; 1304 unsigned int irq; 1305 1306 irq = (unsigned int)source; 1307 if (irq > BCM_GPIO_PINS) 1308 return; 1309 if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq)) 1310 return; 1311 bank = BCM_GPIO_BANK(irq); 1312 mask = BCM_GPIO_MASK(irq); 1313 BCM_GPIO_LOCK(bcm_gpio_sc); 1314 reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank); 1315 if (reg != 0) 1316 BCM_GPIO_CLEAR_BITS(bcm_gpio_sc, reg, mask); 1317 BCM_GPIO_UNLOCK(bcm_gpio_sc); 1318 } 1319 1320 static void 1321 bcm_gpio_unmask_irq(void *source) 1322 { 1323 uint32_t bank, mask, reg; 1324 unsigned int irq; 1325 1326 irq = (unsigned int)source; 1327 if (irq > BCM_GPIO_PINS) 1328 return; 1329 if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq)) 1330 return; 1331 bank = BCM_GPIO_BANK(irq); 1332 mask = BCM_GPIO_MASK(irq); 1333 BCM_GPIO_LOCK(bcm_gpio_sc); 1334 reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank); 1335 if (reg != 0) 1336 BCM_GPIO_SET_BITS(bcm_gpio_sc, reg, mask); 1337 BCM_GPIO_UNLOCK(bcm_gpio_sc); 1338 } 1339 1340 static int 1341 bcm_gpio_activate_resource(device_t bus, device_t child, int type, int rid, 1342 struct resource *res) 1343 { 1344 int pin; 1345 1346 if (type != SYS_RES_IRQ) 1347 return (ENXIO); 1348 /* Unmask the interrupt. */ 1349 pin = rman_get_start(res); 1350 bcm_gpio_unmask_irq((void *)pin); 1351 1352 return (0); 1353 } 1354 1355 static int 1356 bcm_gpio_deactivate_resource(device_t bus, device_t child, int type, int rid, 1357 struct resource *res) 1358 { 1359 int pin; 1360 1361 if (type != SYS_RES_IRQ) 1362 return (ENXIO); 1363 /* Mask the interrupt. */ 1364 pin = rman_get_start(res); 1365 bcm_gpio_mask_irq((void *)pin); 1366 1367 return (0); 1368 } 1369 1370 static int 1371 bcm_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, 1372 enum intr_polarity pol) 1373 { 1374 int bank; 1375 struct bcm_gpio_softc *sc; 1376 uint32_t mask, oldreg, reg; 1377 1378 if (irq > BCM_GPIO_PINS) 1379 return (EINVAL); 1380 /* There is no standard trigger or polarity. */ 1381 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) 1382 return (EINVAL); 1383 sc = device_get_softc(dev); 1384 if (bcm_gpio_pin_is_ro(sc, irq)) 1385 return (EINVAL); 1386 bank = BCM_GPIO_BANK(irq); 1387 mask = BCM_GPIO_MASK(irq); 1388 BCM_GPIO_LOCK(sc); 1389 oldreg = bcm_gpio_intr_reg(sc, irq, bank); 1390 sc->sc_irq_trigger[irq] = trig; 1391 sc->sc_irq_polarity[irq] = pol; 1392 reg = bcm_gpio_intr_reg(sc, irq, bank); 1393 if (reg != 0) 1394 BCM_GPIO_SET_BITS(sc, reg, mask); 1395 if (reg != oldreg && oldreg != 0) 1396 BCM_GPIO_CLEAR_BITS(sc, oldreg, mask); 1397 BCM_GPIO_UNLOCK(sc); 1398 1399 return (0); 1400 } 1401 1402 static int 1403 bcm_gpio_setup_intr(device_t bus, device_t child, struct resource *ires, 1404 int flags, driver_filter_t *filt, driver_intr_t *handler, 1405 void *arg, void **cookiep) 1406 { 1407 struct bcm_gpio_softc *sc; 1408 struct intr_event *event; 1409 int pin, error; 1410 1411 sc = device_get_softc(bus); 1412 pin = rman_get_start(ires); 1413 if (pin > BCM_GPIO_PINS) 1414 panic("%s: bad pin %d", __func__, pin); 1415 event = sc->sc_events[pin]; 1416 if (event == NULL) { 1417 error = intr_event_create(&event, (void *)pin, 0, pin, 1418 bcm_gpio_mask_irq, bcm_gpio_unmask_irq, NULL, NULL, 1419 "gpio%d pin%d:", device_get_unit(bus), pin); 1420 if (error != 0) 1421 return (error); 1422 sc->sc_events[pin] = event; 1423 } 1424 intr_event_add_handler(event, device_get_nameunit(child), filt, 1425 handler, arg, intr_priority(flags), flags, cookiep); 1426 1427 return (0); 1428 } 1429 1430 static int 1431 bcm_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires, 1432 void *cookie) 1433 { 1434 struct bcm_gpio_softc *sc; 1435 int pin, err; 1436 1437 sc = device_get_softc(dev); 1438 pin = rman_get_start(ires); 1439 if (pin > BCM_GPIO_PINS) 1440 panic("%s: bad pin %d", __func__, pin); 1441 if (sc->sc_events[pin] == NULL) 1442 panic("Trying to teardown unoccupied IRQ"); 1443 err = intr_event_remove_handler(cookie); 1444 if (!err) 1445 sc->sc_events[pin] = NULL; 1446 1447 return (err); 1448 } 1449 #endif 1450 1451 static phandle_t 1452 bcm_gpio_get_node(device_t bus, device_t dev) 1453 { 1454 1455 /* We only have one child, the GPIO bus, which needs our own node. */ 1456 return (ofw_bus_get_node(bus)); 1457 } 1458 1459 static device_method_t bcm_gpio_methods[] = { 1460 /* Device interface */ 1461 DEVMETHOD(device_probe, bcm_gpio_probe), 1462 DEVMETHOD(device_attach, bcm_gpio_attach), 1463 DEVMETHOD(device_detach, bcm_gpio_detach), 1464 1465 /* GPIO protocol */ 1466 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus), 1467 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max), 1468 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname), 1469 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags), 1470 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps), 1471 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags), 1472 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get), 1473 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set), 1474 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle), 1475 1476 #ifdef INTRNG 1477 /* Interrupt controller interface */ 1478 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr), 1479 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr), 1480 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr), 1481 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter), 1482 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread), 1483 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread), 1484 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr), 1485 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr), 1486 #else 1487 /* Bus interface */ 1488 DEVMETHOD(bus_activate_resource, bcm_gpio_activate_resource), 1489 DEVMETHOD(bus_deactivate_resource, bcm_gpio_deactivate_resource), 1490 DEVMETHOD(bus_config_intr, bcm_gpio_config_intr), 1491 DEVMETHOD(bus_setup_intr, bcm_gpio_setup_intr), 1492 DEVMETHOD(bus_teardown_intr, bcm_gpio_teardown_intr), 1493 #endif 1494 /* ofw_bus interface */ 1495 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node), 1496 1497 DEVMETHOD_END 1498 }; 1499 1500 static devclass_t bcm_gpio_devclass; 1501 1502 static driver_t bcm_gpio_driver = { 1503 "gpio", 1504 bcm_gpio_methods, 1505 sizeof(struct bcm_gpio_softc), 1506 }; 1507 1508 DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, bcm_gpio_devclass, 0, 0); 1509