1 /* 2 * Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp> 3 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/queue.h> 40 #include <sys/resource.h> 41 #include <sys/rman.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 #include <machine/bus.h> 51 52 #include "bcm2835_dma.h" 53 #include "bcm2835_vcbus.h" 54 55 #define MAX_REG 9 56 57 /* private flags */ 58 #define BCM_DMA_CH_USED 0x00000001 59 #define BCM_DMA_CH_FREE 0x40000000 60 #define BCM_DMA_CH_UNMAP 0x80000000 61 62 /* Register Map (4.2.1.2) */ 63 #define BCM_DMA_CS(n) (0x100*(n) + 0x00) 64 #define CS_ACTIVE (1 << 0) 65 #define CS_END (1 << 1) 66 #define CS_INT (1 << 2) 67 #define CS_DREQ (1 << 3) 68 #define CS_ISPAUSED (1 << 4) 69 #define CS_ISHELD (1 << 5) 70 #define CS_ISWAIT (1 << 6) 71 #define CS_ERR (1 << 8) 72 #define CS_WAITWRT (1 << 28) 73 #define CS_DISDBG (1 << 29) 74 #define CS_ABORT (1 << 30) 75 #define CS_RESET (1U << 31) 76 #define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04) 77 #define BCM_DMA_INFO(n) (0x100*(n) + 0x08) 78 #define INFO_INT_EN (1 << 0) 79 #define INFO_TDMODE (1 << 1) 80 #define INFO_WAIT_RESP (1 << 3) 81 #define INFO_D_INC (1 << 4) 82 #define INFO_D_WIDTH (1 << 5) 83 #define INFO_D_DREQ (1 << 6) 84 #define INFO_S_INC (1 << 8) 85 #define INFO_S_WIDTH (1 << 9) 86 #define INFO_S_DREQ (1 << 10) 87 #define INFO_WAITS_SHIFT (21) 88 #define INFO_PERMAP_SHIFT (16) 89 #define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT) 90 91 #define BCM_DMA_SRC(n) (0x100*(n) + 0x0C) 92 #define BCM_DMA_DST(n) (0x100*(n) + 0x10) 93 #define BCM_DMA_LEN(n) (0x100*(n) + 0x14) 94 #define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18) 95 #define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C) 96 #define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20) 97 #define DEBUG_ERROR_MASK (7) 98 99 #define BCM_DMA_INT_STATUS 0xfe0 100 #define BCM_DMA_ENABLE 0xff0 101 102 /* relative offset from BCM_VC_DMA0_BASE (p.39) */ 103 #define BCM_DMA_CH(n) (0x100*(n)) 104 105 /* channels used by GPU */ 106 #define BCM_DMA_CH_BULK 0 107 #define BCM_DMA_CH_FAST1 2 108 #define BCM_DMA_CH_FAST2 3 109 110 #define BCM_DMA_CH_GPU_MASK ((1 << BCM_DMA_CH_BULK) | \ 111 (1 << BCM_DMA_CH_FAST1) | \ 112 (1 << BCM_DMA_CH_FAST2)) 113 114 /* DMA Control Block - 256bit aligned (p.40) */ 115 struct bcm_dma_cb { 116 uint32_t info; /* Transfer Information */ 117 uint32_t src; /* Source Address */ 118 uint32_t dst; /* Destination Address */ 119 uint32_t len; /* Transfer Length */ 120 uint32_t stride; /* 2D Mode Stride */ 121 uint32_t next; /* Next Control Block Address */ 122 uint32_t rsvd1; /* Reserved */ 123 uint32_t rsvd2; /* Reserved */ 124 }; 125 126 #ifdef DEBUG 127 static void bcm_dma_cb_dump(struct bcm_dma_cb *cb); 128 static void bcm_dma_reg_dump(int ch); 129 #endif 130 131 /* DMA channel private info */ 132 struct bcm_dma_ch { 133 int ch; 134 uint32_t flags; 135 struct bcm_dma_cb * cb; 136 uint32_t vc_cb; 137 bus_dmamap_t dma_map; 138 void (*intr_func)(int, void *); 139 void * intr_arg; 140 }; 141 142 struct bcm_dma_softc { 143 device_t sc_dev; 144 struct mtx sc_mtx; 145 struct resource * sc_mem; 146 struct resource * sc_irq[BCM_DMA_CH_MAX]; 147 void * sc_intrhand[BCM_DMA_CH_MAX]; 148 struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX]; 149 bus_dma_tag_t sc_dma_tag; 150 }; 151 152 static struct bcm_dma_softc *bcm_dma_sc = NULL; 153 static uint32_t bcm_dma_channel_mask; 154 155 static struct ofw_compat_data compat_data[] = { 156 {"broadcom,bcm2835-dma", 1}, 157 {"brcm,bcm2835-dma", 1}, 158 {NULL, 0} 159 }; 160 161 static void 162 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 163 int nseg, int err) 164 { 165 bus_addr_t *addr; 166 167 if (err) 168 return; 169 170 addr = (bus_addr_t*)arg; 171 *addr = PHYS_TO_VCBUS(segs[0].ds_addr); 172 } 173 174 static void 175 bcm_dma_reset(device_t dev, int ch) 176 { 177 struct bcm_dma_softc *sc = device_get_softc(dev); 178 struct bcm_dma_cb *cb; 179 uint32_t cs; 180 int count; 181 182 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 183 return; 184 185 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 186 187 if (cs & CS_ACTIVE) { 188 /* pause current task */ 189 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0); 190 191 count = 1000; 192 do { 193 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 194 } while (!(cs & CS_ISPAUSED) && (count-- > 0)); 195 196 if (!(cs & CS_ISPAUSED)) { 197 device_printf(dev, 198 "Can't abort DMA transfer at channel %d\n", ch); 199 } 200 201 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 202 203 /* Complete everything, clear interrupt */ 204 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 205 CS_ABORT | CS_INT | CS_END| CS_ACTIVE); 206 } 207 208 /* clear control blocks */ 209 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0); 210 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 211 212 /* Reset control block */ 213 cb = sc->sc_dma_ch[ch].cb; 214 bzero(cb, sizeof(*cb)); 215 cb->info = INFO_WAIT_RESP; 216 } 217 218 static int 219 bcm_dma_init(device_t dev) 220 { 221 struct bcm_dma_softc *sc = device_get_softc(dev); 222 uint32_t reg; 223 struct bcm_dma_ch *ch; 224 void *cb_virt; 225 vm_paddr_t cb_phys; 226 int err; 227 int i; 228 229 /* 230 * Only channels set in bcm_dma_channel_mask can be controlled by us. 231 * The others are out of our control as well as the corresponding bits 232 * in both BCM_DMA_ENABLE and BCM_DMA_INT_STATUS global registers. As 233 * these registers are RW ones, there is no safe way how to write only 234 * the bits which can be controlled by us. 235 * 236 * Fortunately, after reset, all channels are enabled in BCM_DMA_ENABLE 237 * register and all statuses are cleared in BCM_DMA_INT_STATUS one. 238 * Not touching these registers is a trade off between correct 239 * initialization which does not count on anything and not messing up 240 * something we have no control over. 241 */ 242 reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE); 243 if ((reg & bcm_dma_channel_mask) != bcm_dma_channel_mask) 244 device_printf(dev, "channels are not enabled\n"); 245 reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS); 246 if ((reg & bcm_dma_channel_mask) != 0) 247 device_printf(dev, "statuses are not cleared\n"); 248 249 /* Allocate DMA chunks control blocks */ 250 /* p.40 of spec - control block should be 32-bit aligned */ 251 err = bus_dma_tag_create(bus_get_dma_tag(dev), 252 1, 0, BUS_SPACE_MAXADDR_32BIT, 253 BUS_SPACE_MAXADDR, NULL, NULL, 254 sizeof(struct bcm_dma_cb), 1, 255 sizeof(struct bcm_dma_cb), 256 BUS_DMA_ALLOCNOW, NULL, NULL, 257 &sc->sc_dma_tag); 258 259 if (err) { 260 device_printf(dev, "failed allocate DMA tag\n"); 261 return (err); 262 } 263 264 /* setup initial settings */ 265 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 266 ch = &sc->sc_dma_ch[i]; 267 268 bzero(ch, sizeof(struct bcm_dma_ch)); 269 ch->ch = i; 270 ch->flags = BCM_DMA_CH_UNMAP; 271 272 if ((bcm_dma_channel_mask & (1 << i)) == 0) 273 continue; 274 275 err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt, 276 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 277 &ch->dma_map); 278 if (err) { 279 device_printf(dev, "cannot allocate DMA memory\n"); 280 break; 281 } 282 283 /* 284 * Least alignment for busdma-allocated stuff is cache 285 * line size, so just make sure nothing stupid happened 286 * and we got properly aligned address 287 */ 288 if ((uintptr_t)cb_virt & 0x1f) { 289 device_printf(dev, 290 "DMA address is not 32-bytes aligned: %p\n", 291 (void*)cb_virt); 292 break; 293 } 294 295 err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt, 296 sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys, 297 BUS_DMA_WAITOK); 298 if (err) { 299 device_printf(dev, "cannot load DMA memory\n"); 300 break; 301 } 302 303 ch->cb = cb_virt; 304 ch->vc_cb = cb_phys; 305 ch->flags = BCM_DMA_CH_FREE; 306 ch->cb->info = INFO_WAIT_RESP; 307 308 /* reset DMA engine */ 309 bus_write_4(sc->sc_mem, BCM_DMA_CS(i), CS_RESET); 310 } 311 312 return (0); 313 } 314 315 /* 316 * Allocate DMA channel for further use, returns channel # or 317 * BCM_DMA_CH_INVALID 318 */ 319 int 320 bcm_dma_allocate(int req_ch) 321 { 322 struct bcm_dma_softc *sc = bcm_dma_sc; 323 int ch = BCM_DMA_CH_INVALID; 324 int i; 325 326 if (req_ch >= BCM_DMA_CH_MAX) 327 return (BCM_DMA_CH_INVALID); 328 329 /* Auto(req_ch < 0) or CH specified */ 330 mtx_lock(&sc->sc_mtx); 331 332 if (req_ch < 0) { 333 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 334 if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) { 335 ch = i; 336 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 337 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 338 break; 339 } 340 } 341 } 342 else { 343 if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) { 344 ch = req_ch; 345 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 346 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 347 } 348 } 349 350 mtx_unlock(&sc->sc_mtx); 351 return (ch); 352 } 353 354 /* 355 * Frees allocated channel. Returns 0 on success, -1 otherwise 356 */ 357 int 358 bcm_dma_free(int ch) 359 { 360 struct bcm_dma_softc *sc = bcm_dma_sc; 361 362 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 363 return (-1); 364 365 mtx_lock(&sc->sc_mtx); 366 if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) { 367 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE; 368 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED; 369 sc->sc_dma_ch[ch].intr_func = NULL; 370 sc->sc_dma_ch[ch].intr_arg = NULL; 371 372 /* reset DMA engine */ 373 bcm_dma_reset(sc->sc_dev, ch); 374 } 375 376 mtx_unlock(&sc->sc_mtx); 377 return (0); 378 } 379 380 /* 381 * Assign handler function for channel interrupt 382 * Returns 0 on success, -1 otherwise 383 */ 384 int 385 bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg) 386 { 387 struct bcm_dma_softc *sc = bcm_dma_sc; 388 struct bcm_dma_cb *cb; 389 390 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 391 return (-1); 392 393 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 394 return (-1); 395 396 sc->sc_dma_ch[ch].intr_func = func; 397 sc->sc_dma_ch[ch].intr_arg = arg; 398 cb = sc->sc_dma_ch[ch].cb; 399 cb->info |= INFO_INT_EN; 400 401 return (0); 402 } 403 404 /* 405 * Setup DMA source parameters 406 * ch - channel number 407 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 408 * source is physical memory 409 * inc_addr - BCM_DMA_INC_ADDR if source address 410 * should be increased after each access or 411 * BCM_DMA_SAME_ADDR if address should remain 412 * the same 413 * width - size of read operation, BCM_DMA_32BIT 414 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 415 * 416 * Returns 0 on success, -1 otherwise 417 */ 418 int 419 bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width) 420 { 421 struct bcm_dma_softc *sc = bcm_dma_sc; 422 uint32_t info; 423 424 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 425 return (-1); 426 427 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 428 return (-1); 429 430 info = sc->sc_dma_ch[ch].cb->info; 431 info &= ~INFO_PERMAP_MASK; 432 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 433 434 if (dreq) 435 info |= INFO_S_DREQ; 436 else 437 info &= ~INFO_S_DREQ; 438 439 if (width == BCM_DMA_128BIT) 440 info |= INFO_S_WIDTH; 441 else 442 info &= ~INFO_S_WIDTH; 443 444 if (inc_addr == BCM_DMA_INC_ADDR) 445 info |= INFO_S_INC; 446 else 447 info &= ~INFO_S_INC; 448 449 sc->sc_dma_ch[ch].cb->info = info; 450 451 return (0); 452 } 453 454 /* 455 * Setup DMA destination parameters 456 * ch - channel number 457 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 458 * destination is physical memory 459 * inc_addr - BCM_DMA_INC_ADDR if source address 460 * should be increased after each access or 461 * BCM_DMA_SAME_ADDR if address should remain 462 * the same 463 * width - size of write operation, BCM_DMA_32BIT 464 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 465 * 466 * Returns 0 on success, -1 otherwise 467 */ 468 int 469 bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width) 470 { 471 struct bcm_dma_softc *sc = bcm_dma_sc; 472 uint32_t info; 473 474 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 475 return (-1); 476 477 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 478 return (-1); 479 480 info = sc->sc_dma_ch[ch].cb->info; 481 info &= ~INFO_PERMAP_MASK; 482 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 483 484 if (dreq) 485 info |= INFO_D_DREQ; 486 else 487 info &= ~INFO_D_DREQ; 488 489 if (width == BCM_DMA_128BIT) 490 info |= INFO_D_WIDTH; 491 else 492 info &= ~INFO_D_WIDTH; 493 494 if (inc_addr == BCM_DMA_INC_ADDR) 495 info |= INFO_D_INC; 496 else 497 info &= ~INFO_D_INC; 498 499 sc->sc_dma_ch[ch].cb->info = info; 500 501 return (0); 502 } 503 504 #ifdef DEBUG 505 void 506 bcm_dma_cb_dump(struct bcm_dma_cb *cb) 507 { 508 509 printf("DMA CB "); 510 printf("INFO: %8.8x ", cb->info); 511 printf("SRC: %8.8x ", cb->src); 512 printf("DST: %8.8x ", cb->dst); 513 printf("LEN: %8.8x ", cb->len); 514 printf("\n"); 515 printf("STRIDE: %8.8x ", cb->stride); 516 printf("NEXT: %8.8x ", cb->next); 517 printf("RSVD1: %8.8x ", cb->rsvd1); 518 printf("RSVD2: %8.8x ", cb->rsvd2); 519 printf("\n"); 520 } 521 522 void 523 bcm_dma_reg_dump(int ch) 524 { 525 struct bcm_dma_softc *sc = bcm_dma_sc; 526 int i; 527 uint32_t reg; 528 529 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 530 return; 531 532 printf("DMA%d: ", ch); 533 for (i = 0; i < MAX_REG; i++) { 534 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4); 535 printf("%8.8x ", reg); 536 } 537 printf("\n"); 538 } 539 #endif 540 541 /* 542 * Start DMA transaction 543 * ch - channel number 544 * src, dst - source and destination address in 545 * ARM physical memory address space. 546 * len - amount of bytes to be transferred 547 * 548 * Returns 0 on success, -1 otherwise 549 */ 550 int 551 bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len) 552 { 553 struct bcm_dma_softc *sc = bcm_dma_sc; 554 struct bcm_dma_cb *cb; 555 556 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 557 return (-1); 558 559 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 560 return (-1); 561 562 cb = sc->sc_dma_ch[ch].cb; 563 if (BCM2835_ARM_IS_IO(src)) 564 cb->src = IO_TO_VCBUS(src); 565 else 566 cb->src = PHYS_TO_VCBUS(src); 567 if (BCM2835_ARM_IS_IO(dst)) 568 cb->dst = IO_TO_VCBUS(dst); 569 else 570 cb->dst = PHYS_TO_VCBUS(dst); 571 cb->len = len; 572 573 bus_dmamap_sync(sc->sc_dma_tag, 574 sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE); 575 576 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 577 sc->sc_dma_ch[ch].vc_cb); 578 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE); 579 580 #ifdef DEBUG 581 bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb); 582 bcm_dma_reg_dump(ch); 583 #endif 584 585 return (0); 586 } 587 588 /* 589 * Get length requested for DMA transaction 590 * ch - channel number 591 * 592 * Returns size of transaction, 0 if channel is invalid 593 */ 594 uint32_t 595 bcm_dma_length(int ch) 596 { 597 struct bcm_dma_softc *sc = bcm_dma_sc; 598 struct bcm_dma_cb *cb; 599 600 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 601 return (0); 602 603 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 604 return (0); 605 606 cb = sc->sc_dma_ch[ch].cb; 607 608 return (cb->len); 609 } 610 611 static void 612 bcm_dma_intr(void *arg) 613 { 614 struct bcm_dma_softc *sc = bcm_dma_sc; 615 struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg; 616 uint32_t cs, debug; 617 618 /* my interrupt? */ 619 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch)); 620 621 if (!(cs & (CS_INT | CS_ERR))) { 622 device_printf(sc->sc_dev, 623 "unexpected DMA intr CH=%d, CS=%x\n", ch->ch, cs); 624 return; 625 } 626 627 /* running? */ 628 if (!(ch->flags & BCM_DMA_CH_USED)) { 629 device_printf(sc->sc_dev, 630 "unused DMA intr CH=%d, CS=%x\n", ch->ch, cs); 631 return; 632 } 633 634 if (cs & CS_ERR) { 635 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch)); 636 device_printf(sc->sc_dev, "DMA error %d on CH%d\n", 637 debug & DEBUG_ERROR_MASK, ch->ch); 638 bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch), 639 debug & DEBUG_ERROR_MASK); 640 bcm_dma_reset(sc->sc_dev, ch->ch); 641 } 642 643 if (cs & CS_INT) { 644 /* acknowledge interrupt */ 645 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch), 646 CS_INT | CS_END); 647 648 /* Prepare for possible access to len field */ 649 bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map, 650 BUS_DMASYNC_POSTWRITE); 651 652 /* save callback function and argument */ 653 if (ch->intr_func) 654 ch->intr_func(ch->ch, ch->intr_arg); 655 } 656 } 657 658 static int 659 bcm_dma_probe(device_t dev) 660 { 661 662 if (!ofw_bus_status_okay(dev)) 663 return (ENXIO); 664 665 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 666 return (ENXIO); 667 668 device_set_desc(dev, "BCM2835 DMA Controller"); 669 return (BUS_PROBE_DEFAULT); 670 } 671 672 static int 673 bcm_dma_attach(device_t dev) 674 { 675 struct bcm_dma_softc *sc = device_get_softc(dev); 676 phandle_t node; 677 int rid, err = 0; 678 int i; 679 680 sc->sc_dev = dev; 681 682 if (bcm_dma_sc) 683 return (ENXIO); 684 685 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 686 sc->sc_irq[i] = NULL; 687 sc->sc_intrhand[i] = NULL; 688 } 689 690 /* Get DMA channel mask. */ 691 node = ofw_bus_get_node(sc->sc_dev); 692 if (OF_getencprop(node, "brcm,dma-channel-mask", &bcm_dma_channel_mask, 693 sizeof(bcm_dma_channel_mask)) == -1 && 694 OF_getencprop(node, "broadcom,channels", &bcm_dma_channel_mask, 695 sizeof(bcm_dma_channel_mask)) == -1) { 696 device_printf(dev, "could not get channel mask property\n"); 697 return (ENXIO); 698 } 699 700 /* Mask out channels used by GPU. */ 701 bcm_dma_channel_mask &= ~BCM_DMA_CH_GPU_MASK; 702 703 /* DMA0 - DMA14 */ 704 rid = 0; 705 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 706 if (sc->sc_mem == NULL) { 707 device_printf(dev, "could not allocate memory resource\n"); 708 return (ENXIO); 709 } 710 711 /* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */ 712 for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) { 713 if ((bcm_dma_channel_mask & (1 << rid)) == 0) 714 continue; 715 716 sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 717 RF_ACTIVE); 718 if (sc->sc_irq[rid] == NULL) { 719 device_printf(dev, "cannot allocate interrupt\n"); 720 err = ENXIO; 721 goto fail; 722 } 723 if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE, 724 NULL, bcm_dma_intr, &sc->sc_dma_ch[rid], 725 &sc->sc_intrhand[rid])) { 726 device_printf(dev, "cannot setup interrupt handler\n"); 727 err = ENXIO; 728 goto fail; 729 } 730 } 731 732 mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF); 733 bcm_dma_sc = sc; 734 735 err = bcm_dma_init(dev); 736 if (err) 737 goto fail; 738 739 return (err); 740 741 fail: 742 if (sc->sc_mem) 743 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem); 744 745 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 746 if (sc->sc_intrhand[i]) 747 bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]); 748 if (sc->sc_irq[i]) 749 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]); 750 } 751 752 return (err); 753 } 754 755 static device_method_t bcm_dma_methods[] = { 756 DEVMETHOD(device_probe, bcm_dma_probe), 757 DEVMETHOD(device_attach, bcm_dma_attach), 758 { 0, 0 } 759 }; 760 761 static driver_t bcm_dma_driver = { 762 "bcm_dma", 763 bcm_dma_methods, 764 sizeof(struct bcm_dma_softc), 765 }; 766 767 static devclass_t bcm_dma_devclass; 768 769 DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, bcm_dma_devclass, 0, 0); 770 MODULE_VERSION(bcm_dma, 1); 771