1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp> 5 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/resource.h> 43 #include <sys/rman.h> 44 45 #include <dev/ofw/openfirm.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 #include <machine/bus.h> 52 53 #include "bcm2835_dma.h" 54 #include "bcm2835_vcbus.h" 55 56 #define MAX_REG 9 57 58 /* private flags */ 59 #define BCM_DMA_CH_USED 0x00000001 60 #define BCM_DMA_CH_FREE 0x40000000 61 #define BCM_DMA_CH_UNMAP 0x80000000 62 63 /* Register Map (4.2.1.2) */ 64 #define BCM_DMA_CS(n) (0x100*(n) + 0x00) 65 #define CS_ACTIVE (1 << 0) 66 #define CS_END (1 << 1) 67 #define CS_INT (1 << 2) 68 #define CS_DREQ (1 << 3) 69 #define CS_ISPAUSED (1 << 4) 70 #define CS_ISHELD (1 << 5) 71 #define CS_ISWAIT (1 << 6) 72 #define CS_ERR (1 << 8) 73 #define CS_WAITWRT (1 << 28) 74 #define CS_DISDBG (1 << 29) 75 #define CS_ABORT (1 << 30) 76 #define CS_RESET (1U << 31) 77 #define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04) 78 #define BCM_DMA_INFO(n) (0x100*(n) + 0x08) 79 #define INFO_INT_EN (1 << 0) 80 #define INFO_TDMODE (1 << 1) 81 #define INFO_WAIT_RESP (1 << 3) 82 #define INFO_D_INC (1 << 4) 83 #define INFO_D_WIDTH (1 << 5) 84 #define INFO_D_DREQ (1 << 6) 85 #define INFO_S_INC (1 << 8) 86 #define INFO_S_WIDTH (1 << 9) 87 #define INFO_S_DREQ (1 << 10) 88 #define INFO_WAITS_SHIFT (21) 89 #define INFO_PERMAP_SHIFT (16) 90 #define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT) 91 92 #define BCM_DMA_SRC(n) (0x100*(n) + 0x0C) 93 #define BCM_DMA_DST(n) (0x100*(n) + 0x10) 94 #define BCM_DMA_LEN(n) (0x100*(n) + 0x14) 95 #define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18) 96 #define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C) 97 #define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20) 98 #define DEBUG_ERROR_MASK (7) 99 100 #define BCM_DMA_INT_STATUS 0xfe0 101 #define BCM_DMA_ENABLE 0xff0 102 103 /* relative offset from BCM_VC_DMA0_BASE (p.39) */ 104 #define BCM_DMA_CH(n) (0x100*(n)) 105 106 /* channels used by GPU */ 107 #define BCM_DMA_CH_BULK 0 108 #define BCM_DMA_CH_FAST1 2 109 #define BCM_DMA_CH_FAST2 3 110 111 #define BCM_DMA_CH_GPU_MASK ((1 << BCM_DMA_CH_BULK) | \ 112 (1 << BCM_DMA_CH_FAST1) | \ 113 (1 << BCM_DMA_CH_FAST2)) 114 115 /* DMA Control Block - 256bit aligned (p.40) */ 116 struct bcm_dma_cb { 117 uint32_t info; /* Transfer Information */ 118 uint32_t src; /* Source Address */ 119 uint32_t dst; /* Destination Address */ 120 uint32_t len; /* Transfer Length */ 121 uint32_t stride; /* 2D Mode Stride */ 122 uint32_t next; /* Next Control Block Address */ 123 uint32_t rsvd1; /* Reserved */ 124 uint32_t rsvd2; /* Reserved */ 125 }; 126 127 #ifdef DEBUG 128 static void bcm_dma_cb_dump(struct bcm_dma_cb *cb); 129 static void bcm_dma_reg_dump(int ch); 130 #endif 131 132 /* DMA channel private info */ 133 struct bcm_dma_ch { 134 int ch; 135 uint32_t flags; 136 struct bcm_dma_cb * cb; 137 uint32_t vc_cb; 138 bus_dmamap_t dma_map; 139 void (*intr_func)(int, void *); 140 void * intr_arg; 141 }; 142 143 struct bcm_dma_softc { 144 device_t sc_dev; 145 struct mtx sc_mtx; 146 struct resource * sc_mem; 147 struct resource * sc_irq[BCM_DMA_CH_MAX]; 148 void * sc_intrhand[BCM_DMA_CH_MAX]; 149 struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX]; 150 bus_dma_tag_t sc_dma_tag; 151 }; 152 153 static struct bcm_dma_softc *bcm_dma_sc = NULL; 154 static uint32_t bcm_dma_channel_mask; 155 156 static struct ofw_compat_data compat_data[] = { 157 {"broadcom,bcm2835-dma", 1}, 158 {"brcm,bcm2835-dma", 1}, 159 {NULL, 0} 160 }; 161 162 static void 163 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 164 int nseg, int err) 165 { 166 bus_addr_t *addr; 167 168 if (err) 169 return; 170 171 addr = (bus_addr_t*)arg; 172 *addr = PHYS_TO_VCBUS(segs[0].ds_addr); 173 } 174 175 static void 176 bcm_dma_reset(device_t dev, int ch) 177 { 178 struct bcm_dma_softc *sc = device_get_softc(dev); 179 struct bcm_dma_cb *cb; 180 uint32_t cs; 181 int count; 182 183 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 184 return; 185 186 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 187 188 if (cs & CS_ACTIVE) { 189 /* pause current task */ 190 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0); 191 192 count = 1000; 193 do { 194 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 195 } while (!(cs & CS_ISPAUSED) && (count-- > 0)); 196 197 if (!(cs & CS_ISPAUSED)) { 198 device_printf(dev, 199 "Can't abort DMA transfer at channel %d\n", ch); 200 } 201 202 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 203 204 /* Complete everything, clear interrupt */ 205 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 206 CS_ABORT | CS_INT | CS_END| CS_ACTIVE); 207 } 208 209 /* clear control blocks */ 210 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0); 211 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 212 213 /* Reset control block */ 214 cb = sc->sc_dma_ch[ch].cb; 215 bzero(cb, sizeof(*cb)); 216 cb->info = INFO_WAIT_RESP; 217 } 218 219 static int 220 bcm_dma_init(device_t dev) 221 { 222 struct bcm_dma_softc *sc = device_get_softc(dev); 223 uint32_t reg; 224 struct bcm_dma_ch *ch; 225 void *cb_virt; 226 vm_paddr_t cb_phys; 227 int err; 228 int i; 229 230 /* 231 * Only channels set in bcm_dma_channel_mask can be controlled by us. 232 * The others are out of our control as well as the corresponding bits 233 * in both BCM_DMA_ENABLE and BCM_DMA_INT_STATUS global registers. As 234 * these registers are RW ones, there is no safe way how to write only 235 * the bits which can be controlled by us. 236 * 237 * Fortunately, after reset, all channels are enabled in BCM_DMA_ENABLE 238 * register and all statuses are cleared in BCM_DMA_INT_STATUS one. 239 * Not touching these registers is a trade off between correct 240 * initialization which does not count on anything and not messing up 241 * something we have no control over. 242 */ 243 reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE); 244 if ((reg & bcm_dma_channel_mask) != bcm_dma_channel_mask) 245 device_printf(dev, "channels are not enabled\n"); 246 reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS); 247 if ((reg & bcm_dma_channel_mask) != 0) 248 device_printf(dev, "statuses are not cleared\n"); 249 250 /* Allocate DMA chunks control blocks */ 251 /* p.40 of spec - control block should be 32-bit aligned */ 252 err = bus_dma_tag_create(bus_get_dma_tag(dev), 253 1, 0, BUS_SPACE_MAXADDR_32BIT, 254 BUS_SPACE_MAXADDR, NULL, NULL, 255 sizeof(struct bcm_dma_cb), 1, 256 sizeof(struct bcm_dma_cb), 257 BUS_DMA_ALLOCNOW, NULL, NULL, 258 &sc->sc_dma_tag); 259 260 if (err) { 261 device_printf(dev, "failed allocate DMA tag\n"); 262 return (err); 263 } 264 265 /* setup initial settings */ 266 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 267 ch = &sc->sc_dma_ch[i]; 268 269 bzero(ch, sizeof(struct bcm_dma_ch)); 270 ch->ch = i; 271 ch->flags = BCM_DMA_CH_UNMAP; 272 273 if ((bcm_dma_channel_mask & (1 << i)) == 0) 274 continue; 275 276 err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt, 277 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 278 &ch->dma_map); 279 if (err) { 280 device_printf(dev, "cannot allocate DMA memory\n"); 281 break; 282 } 283 284 /* 285 * Least alignment for busdma-allocated stuff is cache 286 * line size, so just make sure nothing stupid happened 287 * and we got properly aligned address 288 */ 289 if ((uintptr_t)cb_virt & 0x1f) { 290 device_printf(dev, 291 "DMA address is not 32-bytes aligned: %p\n", 292 (void*)cb_virt); 293 break; 294 } 295 296 err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt, 297 sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys, 298 BUS_DMA_WAITOK); 299 if (err) { 300 device_printf(dev, "cannot load DMA memory\n"); 301 break; 302 } 303 304 ch->cb = cb_virt; 305 ch->vc_cb = cb_phys; 306 ch->flags = BCM_DMA_CH_FREE; 307 ch->cb->info = INFO_WAIT_RESP; 308 309 /* reset DMA engine */ 310 bus_write_4(sc->sc_mem, BCM_DMA_CS(i), CS_RESET); 311 } 312 313 return (0); 314 } 315 316 /* 317 * Allocate DMA channel for further use, returns channel # or 318 * BCM_DMA_CH_INVALID 319 */ 320 int 321 bcm_dma_allocate(int req_ch) 322 { 323 struct bcm_dma_softc *sc = bcm_dma_sc; 324 int ch = BCM_DMA_CH_INVALID; 325 int i; 326 327 if (req_ch >= BCM_DMA_CH_MAX) 328 return (BCM_DMA_CH_INVALID); 329 330 /* Auto(req_ch < 0) or CH specified */ 331 mtx_lock(&sc->sc_mtx); 332 333 if (req_ch < 0) { 334 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 335 if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) { 336 ch = i; 337 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 338 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 339 break; 340 } 341 } 342 } 343 else { 344 if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) { 345 ch = req_ch; 346 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 347 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 348 } 349 } 350 351 mtx_unlock(&sc->sc_mtx); 352 return (ch); 353 } 354 355 /* 356 * Frees allocated channel. Returns 0 on success, -1 otherwise 357 */ 358 int 359 bcm_dma_free(int ch) 360 { 361 struct bcm_dma_softc *sc = bcm_dma_sc; 362 363 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 364 return (-1); 365 366 mtx_lock(&sc->sc_mtx); 367 if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) { 368 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE; 369 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED; 370 sc->sc_dma_ch[ch].intr_func = NULL; 371 sc->sc_dma_ch[ch].intr_arg = NULL; 372 373 /* reset DMA engine */ 374 bcm_dma_reset(sc->sc_dev, ch); 375 } 376 377 mtx_unlock(&sc->sc_mtx); 378 return (0); 379 } 380 381 /* 382 * Assign handler function for channel interrupt 383 * Returns 0 on success, -1 otherwise 384 */ 385 int 386 bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg) 387 { 388 struct bcm_dma_softc *sc = bcm_dma_sc; 389 struct bcm_dma_cb *cb; 390 391 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 392 return (-1); 393 394 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 395 return (-1); 396 397 sc->sc_dma_ch[ch].intr_func = func; 398 sc->sc_dma_ch[ch].intr_arg = arg; 399 cb = sc->sc_dma_ch[ch].cb; 400 cb->info |= INFO_INT_EN; 401 402 return (0); 403 } 404 405 /* 406 * Setup DMA source parameters 407 * ch - channel number 408 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 409 * source is physical memory 410 * inc_addr - BCM_DMA_INC_ADDR if source address 411 * should be increased after each access or 412 * BCM_DMA_SAME_ADDR if address should remain 413 * the same 414 * width - size of read operation, BCM_DMA_32BIT 415 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 416 * 417 * Returns 0 on success, -1 otherwise 418 */ 419 int 420 bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width) 421 { 422 struct bcm_dma_softc *sc = bcm_dma_sc; 423 uint32_t info; 424 425 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 426 return (-1); 427 428 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 429 return (-1); 430 431 info = sc->sc_dma_ch[ch].cb->info; 432 info &= ~INFO_PERMAP_MASK; 433 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 434 435 if (dreq) 436 info |= INFO_S_DREQ; 437 else 438 info &= ~INFO_S_DREQ; 439 440 if (width == BCM_DMA_128BIT) 441 info |= INFO_S_WIDTH; 442 else 443 info &= ~INFO_S_WIDTH; 444 445 if (inc_addr == BCM_DMA_INC_ADDR) 446 info |= INFO_S_INC; 447 else 448 info &= ~INFO_S_INC; 449 450 sc->sc_dma_ch[ch].cb->info = info; 451 452 return (0); 453 } 454 455 /* 456 * Setup DMA destination parameters 457 * ch - channel number 458 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 459 * destination is physical memory 460 * inc_addr - BCM_DMA_INC_ADDR if source address 461 * should be increased after each access or 462 * BCM_DMA_SAME_ADDR if address should remain 463 * the same 464 * width - size of write operation, BCM_DMA_32BIT 465 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 466 * 467 * Returns 0 on success, -1 otherwise 468 */ 469 int 470 bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width) 471 { 472 struct bcm_dma_softc *sc = bcm_dma_sc; 473 uint32_t info; 474 475 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 476 return (-1); 477 478 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 479 return (-1); 480 481 info = sc->sc_dma_ch[ch].cb->info; 482 info &= ~INFO_PERMAP_MASK; 483 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 484 485 if (dreq) 486 info |= INFO_D_DREQ; 487 else 488 info &= ~INFO_D_DREQ; 489 490 if (width == BCM_DMA_128BIT) 491 info |= INFO_D_WIDTH; 492 else 493 info &= ~INFO_D_WIDTH; 494 495 if (inc_addr == BCM_DMA_INC_ADDR) 496 info |= INFO_D_INC; 497 else 498 info &= ~INFO_D_INC; 499 500 sc->sc_dma_ch[ch].cb->info = info; 501 502 return (0); 503 } 504 505 #ifdef DEBUG 506 void 507 bcm_dma_cb_dump(struct bcm_dma_cb *cb) 508 { 509 510 printf("DMA CB "); 511 printf("INFO: %8.8x ", cb->info); 512 printf("SRC: %8.8x ", cb->src); 513 printf("DST: %8.8x ", cb->dst); 514 printf("LEN: %8.8x ", cb->len); 515 printf("\n"); 516 printf("STRIDE: %8.8x ", cb->stride); 517 printf("NEXT: %8.8x ", cb->next); 518 printf("RSVD1: %8.8x ", cb->rsvd1); 519 printf("RSVD2: %8.8x ", cb->rsvd2); 520 printf("\n"); 521 } 522 523 void 524 bcm_dma_reg_dump(int ch) 525 { 526 struct bcm_dma_softc *sc = bcm_dma_sc; 527 int i; 528 uint32_t reg; 529 530 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 531 return; 532 533 printf("DMA%d: ", ch); 534 for (i = 0; i < MAX_REG; i++) { 535 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4); 536 printf("%8.8x ", reg); 537 } 538 printf("\n"); 539 } 540 #endif 541 542 /* 543 * Start DMA transaction 544 * ch - channel number 545 * src, dst - source and destination address in 546 * ARM physical memory address space. 547 * len - amount of bytes to be transferred 548 * 549 * Returns 0 on success, -1 otherwise 550 */ 551 int 552 bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len) 553 { 554 struct bcm_dma_softc *sc = bcm_dma_sc; 555 struct bcm_dma_cb *cb; 556 557 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 558 return (-1); 559 560 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 561 return (-1); 562 563 cb = sc->sc_dma_ch[ch].cb; 564 if (BCM2835_ARM_IS_IO(src)) 565 cb->src = IO_TO_VCBUS(src); 566 else 567 cb->src = PHYS_TO_VCBUS(src); 568 if (BCM2835_ARM_IS_IO(dst)) 569 cb->dst = IO_TO_VCBUS(dst); 570 else 571 cb->dst = PHYS_TO_VCBUS(dst); 572 cb->len = len; 573 574 bus_dmamap_sync(sc->sc_dma_tag, 575 sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE); 576 577 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 578 sc->sc_dma_ch[ch].vc_cb); 579 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE); 580 581 #ifdef DEBUG 582 bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb); 583 bcm_dma_reg_dump(ch); 584 #endif 585 586 return (0); 587 } 588 589 /* 590 * Get length requested for DMA transaction 591 * ch - channel number 592 * 593 * Returns size of transaction, 0 if channel is invalid 594 */ 595 uint32_t 596 bcm_dma_length(int ch) 597 { 598 struct bcm_dma_softc *sc = bcm_dma_sc; 599 struct bcm_dma_cb *cb; 600 601 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 602 return (0); 603 604 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 605 return (0); 606 607 cb = sc->sc_dma_ch[ch].cb; 608 609 return (cb->len); 610 } 611 612 static void 613 bcm_dma_intr(void *arg) 614 { 615 struct bcm_dma_softc *sc = bcm_dma_sc; 616 struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg; 617 uint32_t cs, debug; 618 619 /* my interrupt? */ 620 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch)); 621 622 if (!(cs & (CS_INT | CS_ERR))) { 623 device_printf(sc->sc_dev, 624 "unexpected DMA intr CH=%d, CS=%x\n", ch->ch, cs); 625 return; 626 } 627 628 /* running? */ 629 if (!(ch->flags & BCM_DMA_CH_USED)) { 630 device_printf(sc->sc_dev, 631 "unused DMA intr CH=%d, CS=%x\n", ch->ch, cs); 632 return; 633 } 634 635 if (cs & CS_ERR) { 636 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch)); 637 device_printf(sc->sc_dev, "DMA error %d on CH%d\n", 638 debug & DEBUG_ERROR_MASK, ch->ch); 639 bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch), 640 debug & DEBUG_ERROR_MASK); 641 bcm_dma_reset(sc->sc_dev, ch->ch); 642 } 643 644 if (cs & CS_INT) { 645 /* acknowledge interrupt */ 646 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch), 647 CS_INT | CS_END); 648 649 /* Prepare for possible access to len field */ 650 bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map, 651 BUS_DMASYNC_POSTWRITE); 652 653 /* save callback function and argument */ 654 if (ch->intr_func) 655 ch->intr_func(ch->ch, ch->intr_arg); 656 } 657 } 658 659 static int 660 bcm_dma_probe(device_t dev) 661 { 662 663 if (!ofw_bus_status_okay(dev)) 664 return (ENXIO); 665 666 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 667 return (ENXIO); 668 669 device_set_desc(dev, "BCM2835 DMA Controller"); 670 return (BUS_PROBE_DEFAULT); 671 } 672 673 static int 674 bcm_dma_attach(device_t dev) 675 { 676 struct bcm_dma_softc *sc = device_get_softc(dev); 677 phandle_t node; 678 int rid, err = 0; 679 int i; 680 681 sc->sc_dev = dev; 682 683 if (bcm_dma_sc) 684 return (ENXIO); 685 686 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 687 sc->sc_irq[i] = NULL; 688 sc->sc_intrhand[i] = NULL; 689 } 690 691 /* Get DMA channel mask. */ 692 node = ofw_bus_get_node(sc->sc_dev); 693 if (OF_getencprop(node, "brcm,dma-channel-mask", &bcm_dma_channel_mask, 694 sizeof(bcm_dma_channel_mask)) == -1 && 695 OF_getencprop(node, "broadcom,channels", &bcm_dma_channel_mask, 696 sizeof(bcm_dma_channel_mask)) == -1) { 697 device_printf(dev, "could not get channel mask property\n"); 698 return (ENXIO); 699 } 700 701 /* Mask out channels used by GPU. */ 702 bcm_dma_channel_mask &= ~BCM_DMA_CH_GPU_MASK; 703 704 /* DMA0 - DMA14 */ 705 rid = 0; 706 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 707 if (sc->sc_mem == NULL) { 708 device_printf(dev, "could not allocate memory resource\n"); 709 return (ENXIO); 710 } 711 712 /* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */ 713 for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) { 714 if ((bcm_dma_channel_mask & (1 << rid)) == 0) 715 continue; 716 717 sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 718 RF_ACTIVE); 719 if (sc->sc_irq[rid] == NULL) { 720 device_printf(dev, "cannot allocate interrupt\n"); 721 err = ENXIO; 722 goto fail; 723 } 724 if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE, 725 NULL, bcm_dma_intr, &sc->sc_dma_ch[rid], 726 &sc->sc_intrhand[rid])) { 727 device_printf(dev, "cannot setup interrupt handler\n"); 728 err = ENXIO; 729 goto fail; 730 } 731 } 732 733 mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF); 734 bcm_dma_sc = sc; 735 736 err = bcm_dma_init(dev); 737 if (err) 738 goto fail; 739 740 return (err); 741 742 fail: 743 if (sc->sc_mem) 744 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem); 745 746 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 747 if (sc->sc_intrhand[i]) 748 bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]); 749 if (sc->sc_irq[i]) 750 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]); 751 } 752 753 return (err); 754 } 755 756 static device_method_t bcm_dma_methods[] = { 757 DEVMETHOD(device_probe, bcm_dma_probe), 758 DEVMETHOD(device_attach, bcm_dma_attach), 759 { 0, 0 } 760 }; 761 762 static driver_t bcm_dma_driver = { 763 "bcm_dma", 764 bcm_dma_methods, 765 sizeof(struct bcm_dma_softc), 766 }; 767 768 static devclass_t bcm_dma_devclass; 769 770 DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, bcm_dma_devclass, 0, 0); 771 MODULE_VERSION(bcm_dma, 1); 772