1 /* 2 * Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp> 3 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/queue.h> 40 #include <sys/resource.h> 41 #include <sys/rman.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/cpufunc.h> 53 54 #include "bcm2835_dma.h" 55 #include "bcm2835_vcbus.h" 56 57 #define MAX_REG 9 58 59 /* private flags */ 60 #define BCM_DMA_CH_USED 0x00000001 61 #define BCM_DMA_CH_FREE 0x40000000 62 #define BCM_DMA_CH_UNMAP 0x80000000 63 64 /* Register Map (4.2.1.2) */ 65 #define BCM_DMA_CS(n) (0x100*(n) + 0x00) 66 #define CS_ACTIVE (1 << 0) 67 #define CS_END (1 << 1) 68 #define CS_INT (1 << 2) 69 #define CS_DREQ (1 << 3) 70 #define CS_ISPAUSED (1 << 4) 71 #define CS_ISHELD (1 << 5) 72 #define CS_ISWAIT (1 << 6) 73 #define CS_ERR (1 << 8) 74 #define CS_WAITWRT (1 << 28) 75 #define CS_DISDBG (1 << 29) 76 #define CS_ABORT (1 << 30) 77 #define CS_RESET (1U << 31) 78 #define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04) 79 #define BCM_DMA_INFO(n) (0x100*(n) + 0x08) 80 #define INFO_INT_EN (1 << 0) 81 #define INFO_TDMODE (1 << 1) 82 #define INFO_WAIT_RESP (1 << 3) 83 #define INFO_D_INC (1 << 4) 84 #define INFO_D_WIDTH (1 << 5) 85 #define INFO_D_DREQ (1 << 6) 86 #define INFO_S_INC (1 << 8) 87 #define INFO_S_WIDTH (1 << 9) 88 #define INFO_S_DREQ (1 << 10) 89 #define INFO_WAITS_SHIFT (21) 90 #define INFO_PERMAP_SHIFT (16) 91 #define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT) 92 93 #define BCM_DMA_SRC(n) (0x100*(n) + 0x0C) 94 #define BCM_DMA_DST(n) (0x100*(n) + 0x10) 95 #define BCM_DMA_LEN(n) (0x100*(n) + 0x14) 96 #define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18) 97 #define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C) 98 #define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20) 99 #define DEBUG_ERROR_MASK (7) 100 101 #define BCM_DMA_INT_STATUS 0xfe0 102 #define BCM_DMA_ENABLE 0xff0 103 104 /* relative offset from BCM_VC_DMA0_BASE (p.39) */ 105 #define BCM_DMA_CH(n) (0x100*(n)) 106 107 /* channels used by GPU */ 108 #define BCM_DMA_CH_BULK 0 109 #define BCM_DMA_CH_FAST1 2 110 #define BCM_DMA_CH_FAST2 3 111 112 #define BCM_DMA_CH_GPU_MASK ((1 << BCM_DMA_CH_BULK) | \ 113 (1 << BCM_DMA_CH_FAST1) | \ 114 (1 << BCM_DMA_CH_FAST2)) 115 116 /* DMA Control Block - 256bit aligned (p.40) */ 117 struct bcm_dma_cb { 118 uint32_t info; /* Transfer Information */ 119 uint32_t src; /* Source Address */ 120 uint32_t dst; /* Destination Address */ 121 uint32_t len; /* Transfer Length */ 122 uint32_t stride; /* 2D Mode Stride */ 123 uint32_t next; /* Next Control Block Address */ 124 uint32_t rsvd1; /* Reserved */ 125 uint32_t rsvd2; /* Reserved */ 126 }; 127 128 #ifdef DEBUG 129 static void bcm_dma_cb_dump(struct bcm_dma_cb *cb); 130 static void bcm_dma_reg_dump(int ch); 131 #endif 132 133 /* DMA channel private info */ 134 struct bcm_dma_ch { 135 int ch; 136 uint32_t flags; 137 struct bcm_dma_cb * cb; 138 uint32_t vc_cb; 139 bus_dmamap_t dma_map; 140 void (*intr_func)(int, void *); 141 void * intr_arg; 142 }; 143 144 struct bcm_dma_softc { 145 device_t sc_dev; 146 struct mtx sc_mtx; 147 struct resource * sc_mem; 148 struct resource * sc_irq[BCM_DMA_CH_MAX]; 149 void * sc_intrhand[BCM_DMA_CH_MAX]; 150 struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX]; 151 bus_dma_tag_t sc_dma_tag; 152 }; 153 154 static struct bcm_dma_softc *bcm_dma_sc = NULL; 155 static uint32_t bcm_dma_channel_mask; 156 157 static void 158 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 159 int nseg, int err) 160 { 161 bus_addr_t *addr; 162 163 if (err) 164 return; 165 166 addr = (bus_addr_t*)arg; 167 *addr = PHYS_TO_VCBUS(segs[0].ds_addr); 168 } 169 170 static void 171 bcm_dma_reset(device_t dev, int ch) 172 { 173 struct bcm_dma_softc *sc = device_get_softc(dev); 174 struct bcm_dma_cb *cb; 175 uint32_t cs; 176 int count; 177 178 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 179 return; 180 181 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 182 183 if (cs & CS_ACTIVE) { 184 /* pause current task */ 185 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0); 186 187 count = 1000; 188 do { 189 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 190 } while (!(cs & CS_ISPAUSED) && (count-- > 0)); 191 192 if (!(cs & CS_ISPAUSED)) { 193 device_printf(dev, 194 "Can't abort DMA transfer at channel %d\n", ch); 195 } 196 197 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 198 199 /* Complete everything, clear interrupt */ 200 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 201 CS_ABORT | CS_INT | CS_END| CS_ACTIVE); 202 } 203 204 /* clear control blocks */ 205 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0); 206 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 207 208 /* Reset control block */ 209 cb = sc->sc_dma_ch[ch].cb; 210 bzero(cb, sizeof(*cb)); 211 cb->info = INFO_WAIT_RESP; 212 } 213 214 static int 215 bcm_dma_init(device_t dev) 216 { 217 struct bcm_dma_softc *sc = device_get_softc(dev); 218 uint32_t reg; 219 struct bcm_dma_ch *ch; 220 void *cb_virt; 221 vm_paddr_t cb_phys; 222 int err; 223 int i; 224 225 /* 226 * Only channels set in bcm_dma_channel_mask can be controlled by us. 227 * The others are out of our control as well as the corresponding bits 228 * in both BCM_DMA_ENABLE and BCM_DMA_INT_STATUS global registers. As 229 * these registers are RW ones, there is no safe way how to write only 230 * the bits which can be controlled by us. 231 * 232 * Fortunately, after reset, all channels are enabled in BCM_DMA_ENABLE 233 * register and all statuses are cleared in BCM_DMA_INT_STATUS one. 234 * Not touching these registers is a trade off between correct 235 * initialization which does not count on anything and not messing up 236 * something we have no control over. 237 */ 238 reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE); 239 if ((reg & bcm_dma_channel_mask) != bcm_dma_channel_mask) 240 device_printf(dev, "channels are not enabled\n"); 241 reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS); 242 if ((reg & bcm_dma_channel_mask) != 0) 243 device_printf(dev, "statuses are not cleared\n"); 244 245 /* Allocate DMA chunks control blocks */ 246 /* p.40 of spec - control block should be 32-bit aligned */ 247 err = bus_dma_tag_create(bus_get_dma_tag(dev), 248 1, 0, BUS_SPACE_MAXADDR_32BIT, 249 BUS_SPACE_MAXADDR, NULL, NULL, 250 sizeof(struct bcm_dma_cb), 1, 251 sizeof(struct bcm_dma_cb), 252 BUS_DMA_ALLOCNOW, NULL, NULL, 253 &sc->sc_dma_tag); 254 255 if (err) { 256 device_printf(dev, "failed allocate DMA tag\n"); 257 return (err); 258 } 259 260 /* setup initial settings */ 261 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 262 ch = &sc->sc_dma_ch[i]; 263 264 bzero(ch, sizeof(struct bcm_dma_ch)); 265 ch->ch = i; 266 ch->flags = BCM_DMA_CH_UNMAP; 267 268 if ((bcm_dma_channel_mask & (1 << i)) == 0) 269 continue; 270 271 err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt, 272 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 273 &ch->dma_map); 274 if (err) { 275 device_printf(dev, "cannot allocate DMA memory\n"); 276 break; 277 } 278 279 /* 280 * Least alignment for busdma-allocated stuff is cache 281 * line size, so just make sure nothing stupid happend 282 * and we got properly aligned address 283 */ 284 if ((uintptr_t)cb_virt & 0x1f) { 285 device_printf(dev, 286 "DMA address is not 32-bytes aligned: %p\n", 287 (void*)cb_virt); 288 break; 289 } 290 291 err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt, 292 sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys, 293 BUS_DMA_WAITOK); 294 if (err) { 295 device_printf(dev, "cannot load DMA memory\n"); 296 break; 297 } 298 299 ch->cb = cb_virt; 300 ch->vc_cb = cb_phys; 301 ch->flags = BCM_DMA_CH_FREE; 302 ch->cb->info = INFO_WAIT_RESP; 303 304 /* reset DMA engine */ 305 bus_write_4(sc->sc_mem, BCM_DMA_CS(i), CS_RESET); 306 } 307 308 return (0); 309 } 310 311 /* 312 * Allocate DMA channel for further use, returns channel # or 313 * BCM_DMA_CH_INVALID 314 */ 315 int 316 bcm_dma_allocate(int req_ch) 317 { 318 struct bcm_dma_softc *sc = bcm_dma_sc; 319 int ch = BCM_DMA_CH_INVALID; 320 int i; 321 322 if (req_ch >= BCM_DMA_CH_MAX) 323 return (BCM_DMA_CH_INVALID); 324 325 /* Auto(req_ch < 0) or CH specified */ 326 mtx_lock(&sc->sc_mtx); 327 328 if (req_ch < 0) { 329 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 330 if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) { 331 ch = i; 332 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 333 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 334 break; 335 } 336 } 337 } 338 else { 339 if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) { 340 ch = req_ch; 341 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 342 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 343 } 344 } 345 346 mtx_unlock(&sc->sc_mtx); 347 return (ch); 348 } 349 350 /* 351 * Frees allocated channel. Returns 0 on success, -1 otherwise 352 */ 353 int 354 bcm_dma_free(int ch) 355 { 356 struct bcm_dma_softc *sc = bcm_dma_sc; 357 358 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 359 return (-1); 360 361 mtx_lock(&sc->sc_mtx); 362 if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) { 363 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE; 364 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED; 365 sc->sc_dma_ch[ch].intr_func = NULL; 366 sc->sc_dma_ch[ch].intr_arg = NULL; 367 368 /* reset DMA engine */ 369 bcm_dma_reset(sc->sc_dev, ch); 370 } 371 372 mtx_unlock(&sc->sc_mtx); 373 return (0); 374 } 375 376 /* 377 * Assign handler function for channel interrupt 378 * Returns 0 on success, -1 otherwise 379 */ 380 int 381 bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg) 382 { 383 struct bcm_dma_softc *sc = bcm_dma_sc; 384 struct bcm_dma_cb *cb; 385 386 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 387 return (-1); 388 389 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 390 return (-1); 391 392 sc->sc_dma_ch[ch].intr_func = func; 393 sc->sc_dma_ch[ch].intr_arg = arg; 394 cb = sc->sc_dma_ch[ch].cb; 395 cb->info |= INFO_INT_EN; 396 397 return (0); 398 } 399 400 /* 401 * Setup DMA source parameters 402 * ch - channel number 403 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 404 * source is physical memory 405 * inc_addr - BCM_DMA_INC_ADDR if source address 406 * should be increased after each access or 407 * BCM_DMA_SAME_ADDR if address should remain 408 * the same 409 * width - size of read operation, BCM_DMA_32BIT 410 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 411 * 412 * Returns 0 on success, -1 otherwise 413 */ 414 int 415 bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width) 416 { 417 struct bcm_dma_softc *sc = bcm_dma_sc; 418 uint32_t info; 419 420 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 421 return (-1); 422 423 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 424 return (-1); 425 426 info = sc->sc_dma_ch[ch].cb->info; 427 info &= ~INFO_PERMAP_MASK; 428 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 429 430 if (dreq) 431 info |= INFO_S_DREQ; 432 else 433 info &= ~INFO_S_DREQ; 434 435 if (width == BCM_DMA_128BIT) 436 info |= INFO_S_WIDTH; 437 else 438 info &= ~INFO_S_WIDTH; 439 440 if (inc_addr == BCM_DMA_INC_ADDR) 441 info |= INFO_S_INC; 442 else 443 info &= ~INFO_S_INC; 444 445 sc->sc_dma_ch[ch].cb->info = info; 446 447 return (0); 448 } 449 450 /* 451 * Setup DMA destination parameters 452 * ch - channel number 453 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 454 * destination is physical memory 455 * inc_addr - BCM_DMA_INC_ADDR if source address 456 * should be increased after each access or 457 * BCM_DMA_SAME_ADDR if address should remain 458 * the same 459 * width - size of write operation, BCM_DMA_32BIT 460 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 461 * 462 * Returns 0 on success, -1 otherwise 463 */ 464 int 465 bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width) 466 { 467 struct bcm_dma_softc *sc = bcm_dma_sc; 468 uint32_t info; 469 470 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 471 return (-1); 472 473 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 474 return (-1); 475 476 info = sc->sc_dma_ch[ch].cb->info; 477 info &= ~INFO_PERMAP_MASK; 478 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 479 480 if (dreq) 481 info |= INFO_D_DREQ; 482 else 483 info &= ~INFO_D_DREQ; 484 485 if (width == BCM_DMA_128BIT) 486 info |= INFO_D_WIDTH; 487 else 488 info &= ~INFO_D_WIDTH; 489 490 if (inc_addr == BCM_DMA_INC_ADDR) 491 info |= INFO_D_INC; 492 else 493 info &= ~INFO_D_INC; 494 495 sc->sc_dma_ch[ch].cb->info = info; 496 497 return (0); 498 } 499 500 #ifdef DEBUG 501 void 502 bcm_dma_cb_dump(struct bcm_dma_cb *cb) 503 { 504 505 printf("DMA CB "); 506 printf("INFO: %8.8x ", cb->info); 507 printf("SRC: %8.8x ", cb->src); 508 printf("DST: %8.8x ", cb->dst); 509 printf("LEN: %8.8x ", cb->len); 510 printf("\n"); 511 printf("STRIDE: %8.8x ", cb->stride); 512 printf("NEXT: %8.8x ", cb->next); 513 printf("RSVD1: %8.8x ", cb->rsvd1); 514 printf("RSVD2: %8.8x ", cb->rsvd2); 515 printf("\n"); 516 } 517 518 void 519 bcm_dma_reg_dump(int ch) 520 { 521 struct bcm_dma_softc *sc = bcm_dma_sc; 522 int i; 523 uint32_t reg; 524 525 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 526 return; 527 528 printf("DMA%d: ", ch); 529 for (i = 0; i < MAX_REG; i++) { 530 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4); 531 printf("%8.8x ", reg); 532 } 533 printf("\n"); 534 } 535 #endif 536 537 /* 538 * Start DMA transaction 539 * ch - channel number 540 * src, dst - source and destination address in 541 * ARM physical memory address space. 542 * len - amount of bytes to be transfered 543 * 544 * Returns 0 on success, -1 otherwise 545 */ 546 int 547 bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len) 548 { 549 struct bcm_dma_softc *sc = bcm_dma_sc; 550 struct bcm_dma_cb *cb; 551 552 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 553 return (-1); 554 555 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 556 return (-1); 557 558 cb = sc->sc_dma_ch[ch].cb; 559 if (BCM2835_ARM_IS_IO(src)) 560 cb->src = IO_TO_VCBUS(src); 561 else 562 cb->src = PHYS_TO_VCBUS(src); 563 if (BCM2835_ARM_IS_IO(dst)) 564 cb->dst = IO_TO_VCBUS(dst); 565 else 566 cb->dst = PHYS_TO_VCBUS(dst); 567 cb->len = len; 568 569 bus_dmamap_sync(sc->sc_dma_tag, 570 sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE); 571 572 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 573 sc->sc_dma_ch[ch].vc_cb); 574 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE); 575 576 #ifdef DEBUG 577 bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb); 578 bcm_dma_reg_dump(ch); 579 #endif 580 581 return (0); 582 } 583 584 /* 585 * Get length requested for DMA transaction 586 * ch - channel number 587 * 588 * Returns size of transaction, 0 if channel is invalid 589 */ 590 uint32_t 591 bcm_dma_length(int ch) 592 { 593 struct bcm_dma_softc *sc = bcm_dma_sc; 594 struct bcm_dma_cb *cb; 595 596 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 597 return (0); 598 599 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 600 return (0); 601 602 cb = sc->sc_dma_ch[ch].cb; 603 604 return (cb->len); 605 } 606 607 static void 608 bcm_dma_intr(void *arg) 609 { 610 struct bcm_dma_softc *sc = bcm_dma_sc; 611 struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg; 612 uint32_t cs, debug; 613 614 /* my interrupt? */ 615 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch)); 616 617 if (!(cs & (CS_INT | CS_ERR))) { 618 device_printf(sc->sc_dev, 619 "unexpected DMA intr CH=%d, CS=%x\n", ch->ch, cs); 620 return; 621 } 622 623 /* running? */ 624 if (!(ch->flags & BCM_DMA_CH_USED)) { 625 device_printf(sc->sc_dev, 626 "unused DMA intr CH=%d, CS=%x\n", ch->ch, cs); 627 return; 628 } 629 630 if (cs & CS_ERR) { 631 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch)); 632 device_printf(sc->sc_dev, "DMA error %d on CH%d\n", 633 debug & DEBUG_ERROR_MASK, ch->ch); 634 bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch), 635 debug & DEBUG_ERROR_MASK); 636 bcm_dma_reset(sc->sc_dev, ch->ch); 637 } 638 639 if (cs & CS_INT) { 640 /* acknowledge interrupt */ 641 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch), 642 CS_INT | CS_END); 643 644 /* Prepare for possible access to len field */ 645 bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map, 646 BUS_DMASYNC_POSTWRITE); 647 648 /* save callback function and argument */ 649 if (ch->intr_func) 650 ch->intr_func(ch->ch, ch->intr_arg); 651 } 652 } 653 654 static int 655 bcm_dma_probe(device_t dev) 656 { 657 658 if (!ofw_bus_status_okay(dev)) 659 return (ENXIO); 660 661 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-dma")) 662 return (ENXIO); 663 664 device_set_desc(dev, "BCM2835 DMA Controller"); 665 return (BUS_PROBE_DEFAULT); 666 } 667 668 static int 669 bcm_dma_attach(device_t dev) 670 { 671 struct bcm_dma_softc *sc = device_get_softc(dev); 672 phandle_t node; 673 int rid, err = 0; 674 int i; 675 676 sc->sc_dev = dev; 677 678 if (bcm_dma_sc) 679 return (ENXIO); 680 681 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 682 sc->sc_irq[i] = NULL; 683 sc->sc_intrhand[i] = NULL; 684 } 685 686 /* Get DMA channel mask. */ 687 node = ofw_bus_get_node(sc->sc_dev); 688 if (OF_getencprop(node, "brcm,dma-channel-mask", &bcm_dma_channel_mask, 689 sizeof(bcm_dma_channel_mask)) == -1 && 690 OF_getencprop(node, "broadcom,channels", &bcm_dma_channel_mask, 691 sizeof(bcm_dma_channel_mask)) == -1) { 692 device_printf(dev, "could not get channel mask property\n"); 693 return (ENXIO); 694 } 695 696 /* Mask out channels used by GPU. */ 697 bcm_dma_channel_mask &= ~BCM_DMA_CH_GPU_MASK; 698 699 /* DMA0 - DMA14 */ 700 rid = 0; 701 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 702 if (sc->sc_mem == NULL) { 703 device_printf(dev, "could not allocate memory resource\n"); 704 return (ENXIO); 705 } 706 707 /* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */ 708 for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) { 709 if ((bcm_dma_channel_mask & (1 << rid)) == 0) 710 continue; 711 712 sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 713 RF_ACTIVE); 714 if (sc->sc_irq[rid] == NULL) { 715 device_printf(dev, "cannot allocate interrupt\n"); 716 err = ENXIO; 717 goto fail; 718 } 719 if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE, 720 NULL, bcm_dma_intr, &sc->sc_dma_ch[rid], 721 &sc->sc_intrhand[rid])) { 722 device_printf(dev, "cannot setup interrupt handler\n"); 723 err = ENXIO; 724 goto fail; 725 } 726 } 727 728 mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF); 729 bcm_dma_sc = sc; 730 731 err = bcm_dma_init(dev); 732 if (err) 733 goto fail; 734 735 return (err); 736 737 fail: 738 if (sc->sc_mem) 739 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem); 740 741 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 742 if (sc->sc_intrhand[i]) 743 bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]); 744 if (sc->sc_irq[i]) 745 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]); 746 } 747 748 return (err); 749 } 750 751 static device_method_t bcm_dma_methods[] = { 752 DEVMETHOD(device_probe, bcm_dma_probe), 753 DEVMETHOD(device_attach, bcm_dma_attach), 754 { 0, 0 } 755 }; 756 757 static driver_t bcm_dma_driver = { 758 "bcm_dma", 759 bcm_dma_methods, 760 sizeof(struct bcm_dma_softc), 761 }; 762 763 static devclass_t bcm_dma_devclass; 764 765 DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, bcm_dma_devclass, 0, 0); 766 MODULE_VERSION(bcm_dma, 1); 767