1 /*- 2 * Copyright (c) 2001 Tsubai Masanari. 3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 4 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 5 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for bcm2835 i2c-compatible two-wire bus, named 'BSC' on this SoC. 35 * 36 * This controller can only perform complete transfers, it does not provide 37 * low-level control over sending start/repeat-start/stop sequences on the bus. 38 * In addition, bugs in the silicon make it somewhat difficult to perform a 39 * repeat-start, and limit the repeat-start to a read following a write on 40 * the same slave device. (The i2c protocol allows a repeat start to change 41 * direction or not, and change slave address or not at any time.) 42 * 43 * The repeat-start bug and workaround are described in a problem report at 44 * https://github.com/raspberrypi/linux/issues/254 with the crucial part being 45 * in a comment block from a fragment of a GPU i2c driver, containing this: 46 * 47 * ----------------------------------------------------------------------------- 48 * - See i2c.v: The I2C peripheral samples the values for rw_bit and xfer_count 49 * - in the IDLE state if start is set. 50 * - 51 * - We want to generate a ReSTART not a STOP at the end of the TX phase. In 52 * - order to do that we must ensure the state machine goes RACK1 -> RACK2 -> 53 * - SRSTRT1 (not RACK1 -> RACK2 -> SSTOP1). 54 * - 55 * - So, in the RACK2 state when (TX) xfer_count==0 we must therefore have 56 * - already set, ready to be sampled: 57 * - READ ; rw_bit <= I2CC bit 0 -- must be "read" 58 * - ST; start <= I2CC bit 7 -- must be "Go" in order to not issue STOP 59 * - DLEN; xfer_count <= I2CDLEN -- must be equal to our read amount 60 * - 61 * - The plan to do this is: 62 * - 1. Start the sub-address write, but don't let it finish 63 * - (keep xfer_count > 0) 64 * - 2. Populate READ, DLEN and ST in preparation for ReSTART read sequence 65 * - 3. Let TX finish (write the rest of the data) 66 * - 4. Read back data as it arrives 67 * ----------------------------------------------------------------------------- 68 * 69 * The transfer function below scans the list of messages passed to it, looking 70 * for a read following a write to the same slave. When it finds that, it 71 * starts the write without prefilling the tx fifo, which holds xfer_count>0, 72 * then presets the direction, length, and start command for the following read, 73 * as described above. Then the tx fifo is filled and the rest of the transfer 74 * proceeds as normal, with the controller automatically supplying a 75 * repeat-start on the bus when the write operation finishes. 76 * 77 * XXX I suspect the controller may be able to do a repeat-start on any 78 * write->read or write->write transition, even when the slave addresses differ. 79 * It's unclear whether the slave address can be prestaged along with the 80 * direction and length while the write xfer_count is being held at zero. In 81 * fact, if it can't do this, then it couldn't be used to read EDID data. 82 */ 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/kernel.h> 87 #include <sys/lock.h> 88 #include <sys/module.h> 89 #include <sys/mutex.h> 90 #include <sys/bus.h> 91 #include <machine/resource.h> 92 #include <machine/bus.h> 93 #include <sys/rman.h> 94 #include <sys/sysctl.h> 95 96 #include <dev/iicbus/iicbus.h> 97 #include <dev/iicbus/iiconf.h> 98 #include <dev/ofw/ofw_bus.h> 99 #include <dev/ofw/ofw_bus_subr.h> 100 101 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 102 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h> 103 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h> 104 105 #include "iicbus_if.h" 106 107 static struct ofw_compat_data compat_data[] = { 108 {"broadcom,bcm2835-bsc", 1}, 109 {"brcm,bcm2708-i2c", 1}, 110 {"brcm,bcm2835-i2c", 1}, 111 {NULL, 0} 112 }; 113 114 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 115 if ((lvl) <= (sc)->sc_debug) \ 116 device_printf((sc)->sc_dev, fmt, ##args) 117 118 #define DEBUGF(sc, lvl, fmt, args...) \ 119 if ((lvl) <= (sc)->sc_debug) \ 120 printf(fmt, ##args) 121 122 static void bcm_bsc_intr(void *); 123 static int bcm_bsc_detach(device_t); 124 125 static void 126 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, 127 uint32_t value) 128 { 129 uint32_t reg; 130 131 mtx_assert(&sc->sc_mtx, MA_OWNED); 132 reg = BCM_BSC_READ(sc, off); 133 reg &= ~mask; 134 reg |= value; 135 BCM_BSC_WRITE(sc, off, reg); 136 } 137 138 static int 139 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) 140 { 141 struct bcm_bsc_softc *sc; 142 uint32_t clk; 143 144 sc = (struct bcm_bsc_softc *)arg1; 145 BCM_BSC_LOCK(sc); 146 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 147 BCM_BSC_UNLOCK(sc); 148 clk &= 0xffff; 149 if (clk == 0) 150 clk = 32768; 151 clk = BCM_BSC_CORE_CLK / clk; 152 153 return (sysctl_handle_int(oidp, &clk, 0, req)); 154 } 155 156 static int 157 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) 158 { 159 struct bcm_bsc_softc *sc; 160 uint32_t clkt; 161 int error; 162 163 sc = (struct bcm_bsc_softc *)arg1; 164 165 BCM_BSC_LOCK(sc); 166 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); 167 BCM_BSC_UNLOCK(sc); 168 clkt &= 0xffff; 169 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); 170 if (error != 0 || req->newptr == NULL) 171 return (error); 172 173 BCM_BSC_LOCK(sc); 174 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); 175 BCM_BSC_UNLOCK(sc); 176 177 return (0); 178 } 179 180 static int 181 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) 182 { 183 struct bcm_bsc_softc *sc; 184 uint32_t clk, reg; 185 int error; 186 187 sc = (struct bcm_bsc_softc *)arg1; 188 189 BCM_BSC_LOCK(sc); 190 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 191 BCM_BSC_UNLOCK(sc); 192 reg >>= 16; 193 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 194 if (error != 0 || req->newptr == NULL) 195 return (error); 196 197 BCM_BSC_LOCK(sc); 198 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 199 clk = BCM_BSC_CORE_CLK / clk; 200 if (reg > clk / 2) 201 reg = clk / 2 - 1; 202 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); 203 BCM_BSC_UNLOCK(sc); 204 205 return (0); 206 } 207 208 static int 209 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) 210 { 211 struct bcm_bsc_softc *sc; 212 uint32_t clk, reg; 213 int error; 214 215 sc = (struct bcm_bsc_softc *)arg1; 216 217 BCM_BSC_LOCK(sc); 218 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 219 BCM_BSC_UNLOCK(sc); 220 reg &= 0xffff; 221 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 222 if (error != 0 || req->newptr == NULL) 223 return (error); 224 225 BCM_BSC_LOCK(sc); 226 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 227 clk = BCM_BSC_CORE_CLK / clk; 228 if (reg > clk / 2) 229 reg = clk / 2 - 1; 230 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); 231 BCM_BSC_UNLOCK(sc); 232 233 return (0); 234 } 235 236 static void 237 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) 238 { 239 struct sysctl_ctx_list *ctx; 240 struct sysctl_oid *tree_node; 241 struct sysctl_oid_list *tree; 242 243 /* 244 * Add system sysctl tree/handlers. 245 */ 246 ctx = device_get_sysctl_ctx(sc->sc_dev); 247 tree_node = device_get_sysctl_tree(sc->sc_dev); 248 tree = SYSCTL_CHILDREN(tree_node); 249 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency", 250 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 251 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); 252 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", 253 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 254 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); 255 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", 256 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 257 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); 258 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", 259 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 260 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); 261 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "debug", 262 CTLFLAG_RWTUN, &sc->sc_debug, 0, 263 "Enable debug; 1=reads/writes, 2=add starts/stops"); 264 } 265 266 static void 267 bcm_bsc_reset(struct bcm_bsc_softc *sc) 268 { 269 270 /* Enable the BSC Controller, disable interrupts. */ 271 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 272 /* Clear pending interrupts. */ 273 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | 274 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); 275 /* Clear the FIFO. */ 276 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, 277 BCM_BSC_CTRL_CLEAR0); 278 } 279 280 static int 281 bcm_bsc_probe(device_t dev) 282 { 283 284 if (!ofw_bus_status_okay(dev)) 285 return (ENXIO); 286 287 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 288 return (ENXIO); 289 290 device_set_desc(dev, "BCM2708/2835 BSC controller"); 291 292 return (BUS_PROBE_DEFAULT); 293 } 294 295 static int 296 bcm_bsc_attach(device_t dev) 297 { 298 struct bcm_bsc_softc *sc; 299 unsigned long start; 300 device_t gpio; 301 int i, rid; 302 303 sc = device_get_softc(dev); 304 sc->sc_dev = dev; 305 306 rid = 0; 307 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 308 RF_ACTIVE); 309 if (!sc->sc_mem_res) { 310 device_printf(dev, "cannot allocate memory window\n"); 311 return (ENXIO); 312 } 313 314 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 315 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 316 317 /* Check the unit we are attaching by its base address. */ 318 start = rman_get_start(sc->sc_mem_res); 319 for (i = 0; i < nitems(bcm_bsc_pins); i++) { 320 if (bcm_bsc_pins[i].start == (start & BCM_BSC_BASE_MASK)) 321 break; 322 } 323 if (i == nitems(bcm_bsc_pins)) { 324 device_printf(dev, "only bsc0 and bsc1 are supported\n"); 325 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 326 return (ENXIO); 327 } 328 329 /* 330 * Configure the GPIO pins to ALT0 function to enable BSC control 331 * over the pins. 332 */ 333 gpio = devclass_get_device(devclass_find("gpio"), 0); 334 if (!gpio) { 335 device_printf(dev, "cannot find gpio0\n"); 336 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 337 return (ENXIO); 338 } 339 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0); 340 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0); 341 342 rid = 0; 343 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 344 RF_ACTIVE | RF_SHAREABLE); 345 if (!sc->sc_irq_res) { 346 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 347 device_printf(dev, "cannot allocate interrupt\n"); 348 return (ENXIO); 349 } 350 351 /* Hook up our interrupt handler. */ 352 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 353 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { 354 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 355 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 356 device_printf(dev, "cannot setup the interrupt handler\n"); 357 return (ENXIO); 358 } 359 360 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); 361 362 bcm_bsc_sysctl_init(sc); 363 364 /* Enable the BSC controller. Flush the FIFO. */ 365 BCM_BSC_LOCK(sc); 366 bcm_bsc_reset(sc); 367 BCM_BSC_UNLOCK(sc); 368 369 sc->sc_iicbus = device_add_child(dev, "iicbus", -1); 370 if (sc->sc_iicbus == NULL) { 371 bcm_bsc_detach(dev); 372 return (ENXIO); 373 } 374 375 /* Probe and attach the iicbus when interrupts are available. */ 376 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); 377 378 return (0); 379 } 380 381 static int 382 bcm_bsc_detach(device_t dev) 383 { 384 struct bcm_bsc_softc *sc; 385 386 bus_generic_detach(dev); 387 388 sc = device_get_softc(dev); 389 if (sc->sc_iicbus != NULL) 390 device_delete_child(dev, sc->sc_iicbus); 391 mtx_destroy(&sc->sc_mtx); 392 if (sc->sc_intrhand) 393 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 394 if (sc->sc_irq_res) 395 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 396 if (sc->sc_mem_res) 397 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 398 399 return (0); 400 } 401 402 static void 403 bcm_bsc_empty_rx_fifo(struct bcm_bsc_softc *sc) 404 { 405 uint32_t status; 406 407 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_RXD is asserted on entry. */ 408 do { 409 if (sc->sc_resid == 0) { 410 sc->sc_data = sc->sc_curmsg->buf; 411 sc->sc_dlen = sc->sc_curmsg->len; 412 sc->sc_resid = sc->sc_dlen; 413 ++sc->sc_curmsg; 414 } 415 do { 416 *sc->sc_data = BCM_BSC_READ(sc, BCM_BSC_DATA); 417 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); 418 ++sc->sc_data; 419 --sc->sc_resid; 420 --sc->sc_totlen; 421 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 422 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)); 423 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_RXD)); 424 } 425 426 static void 427 bcm_bsc_fill_tx_fifo(struct bcm_bsc_softc *sc) 428 { 429 uint32_t status; 430 431 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_TXD is asserted on entry. */ 432 do { 433 if (sc->sc_resid == 0) { 434 sc->sc_data = sc->sc_curmsg->buf; 435 sc->sc_dlen = sc->sc_curmsg->len; 436 sc->sc_resid = sc->sc_dlen; 437 ++sc->sc_curmsg; 438 } 439 do { 440 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); 441 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); 442 ++sc->sc_data; 443 --sc->sc_resid; 444 --sc->sc_totlen; 445 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 446 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)); 447 /* 448 * If a repeat-start was pending and we just hit the end of a tx 449 * buffer, see if it's also the end of the writes that preceeded 450 * the repeat-start. If so, log the repeat-start and the start 451 * of the following read, and return because we're not writing 452 * anymore (and TXD will be true because there's room to write 453 * in the fifo). 454 */ 455 if (sc->sc_replen > 0 && sc->sc_resid == 0) { 456 sc->sc_replen -= sc->sc_dlen; 457 if (sc->sc_replen == 0) { 458 DEBUGF(sc, 1, " err=0\n"); 459 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", 460 sc->sc_curmsg->slave | 0x01); 461 DEVICE_DEBUGF(sc, 1, 462 "read 0x%02x len %d: ", 463 sc->sc_curmsg->slave | 0x01, 464 sc->sc_totlen); 465 sc->sc_flags |= BCM_I2C_READ; 466 return; 467 } 468 } 469 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_TXD)); 470 } 471 472 static void 473 bcm_bsc_intr(void *arg) 474 { 475 struct bcm_bsc_softc *sc; 476 uint32_t status; 477 478 sc = (struct bcm_bsc_softc *)arg; 479 480 BCM_BSC_LOCK(sc); 481 482 /* The I2C interrupt is shared among all the BSC controllers. */ 483 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { 484 BCM_BSC_UNLOCK(sc); 485 return; 486 } 487 488 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 489 DEBUGF(sc, 4, " <intrstatus=0x%08x> ", status); 490 491 /* RXD and DONE can assert together, empty fifo before checking done. */ 492 if ((sc->sc_flags & BCM_I2C_READ) && (status & BCM_BSC_STATUS_RXD)) 493 bcm_bsc_empty_rx_fifo(sc); 494 495 /* Check for completion. */ 496 if (status & (BCM_BSC_STATUS_ERRBITS | BCM_BSC_STATUS_DONE)) { 497 sc->sc_flags |= BCM_I2C_DONE; 498 if (status & BCM_BSC_STATUS_ERRBITS) 499 sc->sc_flags |= BCM_I2C_ERROR; 500 /* Disable interrupts. */ 501 bcm_bsc_reset(sc); 502 wakeup(sc); 503 } else if (!(sc->sc_flags & BCM_I2C_READ)) { 504 /* 505 * Don't check for TXD until after determining whether the 506 * transfer is complete; TXD will be asserted along with ERR or 507 * DONE if there is room in the fifo. 508 */ 509 if (status & BCM_BSC_STATUS_TXD) 510 bcm_bsc_fill_tx_fifo(sc); 511 } 512 513 BCM_BSC_UNLOCK(sc); 514 } 515 516 static int 517 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 518 { 519 struct bcm_bsc_softc *sc; 520 struct iic_msg *endmsgs, *nxtmsg; 521 uint32_t readctl, status; 522 int err; 523 uint16_t curlen; 524 uint8_t curisread, curslave, nxtisread, nxtslave; 525 526 sc = device_get_softc(dev); 527 BCM_BSC_LOCK(sc); 528 529 /* If the controller is busy wait until it is available. */ 530 while (sc->sc_flags & BCM_I2C_BUSY) 531 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0); 532 533 /* Now we have control over the BSC controller. */ 534 sc->sc_flags = BCM_I2C_BUSY; 535 536 DEVICE_DEBUGF(sc, 3, "Transfer %d msgs\n", nmsgs); 537 538 /* Clear the FIFO and the pending interrupts. */ 539 bcm_bsc_reset(sc); 540 541 /* 542 * Perform all the transfers requested in the array of msgs. Note that 543 * it is bcm_bsc_empty_rx_fifo() and bcm_bsc_fill_tx_fifo() that advance 544 * sc->sc_curmsg through the array of messages, as the data from each 545 * message is fully consumed, but it is this loop that notices when we 546 * have no more messages to process. 547 */ 548 err = 0; 549 sc->sc_resid = 0; 550 sc->sc_curmsg = msgs; 551 endmsgs = &msgs[nmsgs]; 552 while (sc->sc_curmsg < endmsgs) { 553 readctl = 0; 554 curslave = sc->sc_curmsg->slave >> 1; 555 curisread = sc->sc_curmsg->flags & IIC_M_RD; 556 sc->sc_replen = 0; 557 sc->sc_totlen = sc->sc_curmsg->len; 558 /* 559 * Scan for scatter/gather IO (same slave and direction) or 560 * repeat-start (read following write for the same slave). 561 */ 562 for (nxtmsg = sc->sc_curmsg + 1; nxtmsg < endmsgs; ++nxtmsg) { 563 nxtslave = nxtmsg->slave >> 1; 564 if (curslave == nxtslave) { 565 nxtisread = nxtmsg->flags & IIC_M_RD; 566 if (curisread == nxtisread) { 567 /* 568 * Same slave and direction, this 569 * message will be part of the same 570 * transfer as the previous one. 571 */ 572 sc->sc_totlen += nxtmsg->len; 573 continue; 574 } else if (curisread == IIC_M_WR) { 575 /* 576 * Read after write to same slave means 577 * repeat-start, remember how many bytes 578 * come before the repeat-start, switch 579 * the direction to IIC_M_RD, and gather 580 * up following reads to the same slave. 581 */ 582 curisread = IIC_M_RD; 583 sc->sc_replen = sc->sc_totlen; 584 sc->sc_totlen += nxtmsg->len; 585 continue; 586 } 587 } 588 break; 589 } 590 591 /* 592 * curslave and curisread temporaries from above may refer to 593 * the after-repstart msg, reset them to reflect sc_curmsg. 594 */ 595 curisread = (sc->sc_curmsg->flags & IIC_M_RD) ? 1 : 0; 596 curslave = sc->sc_curmsg->slave | curisread; 597 598 /* Write the slave address. */ 599 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, curslave >> 1); 600 601 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", curslave); 602 603 /* 604 * Either set up read length and direction variables for a 605 * simple transfer or get the hardware started on the first 606 * piece of a transfer that involves a repeat-start and set up 607 * the read length and direction vars for the second piece. 608 */ 609 if (sc->sc_replen == 0) { 610 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", 611 (curisread) ? "readctl" : "write", curslave, 612 sc->sc_totlen); 613 curlen = sc->sc_totlen; 614 if (curisread) { 615 readctl = BCM_BSC_CTRL_READ; 616 sc->sc_flags |= BCM_I2C_READ; 617 } else { 618 readctl = 0; 619 sc->sc_flags &= ~BCM_I2C_READ; 620 } 621 } else { 622 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", 623 (curisread) ? "readctl" : "write", curslave, 624 sc->sc_replen); 625 626 /* 627 * Start the write transfer with an empty fifo and wait 628 * for the 'transfer active' status bit to light up; 629 * that indicates that the hardware has latched the 630 * direction and length for the write, and we can safely 631 * reload those registers and issue the start for the 632 * following read; interrupts are not enabled here. 633 */ 634 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, sc->sc_replen); 635 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | 636 BCM_BSC_CTRL_ST); 637 do { 638 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 639 if (status & BCM_BSC_STATUS_ERR) { 640 /* no ACK on slave addr */ 641 err = EIO; 642 goto xfer_done; 643 } 644 } while ((status & BCM_BSC_STATUS_TA) == 0); 645 /* 646 * Set curlen and readctl for the repeat-start read that 647 * we need to set up below, but set sc_flags to write, 648 * because that is the operation in progress right now. 649 */ 650 curlen = sc->sc_totlen - sc->sc_replen; 651 readctl = BCM_BSC_CTRL_READ; 652 sc->sc_flags &= ~BCM_I2C_READ; 653 } 654 655 /* 656 * Start the transfer with interrupts enabled, then if doing a 657 * write, fill the tx fifo. Not prefilling the fifo until after 658 * this start command is the key workaround for making 659 * repeat-start work, and it's harmless to do it in this order 660 * for a regular write too. 661 */ 662 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, curlen); 663 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, readctl | BCM_BSC_CTRL_I2CEN | 664 BCM_BSC_CTRL_ST | BCM_BSC_CTRL_INT_ALL); 665 666 if (!(sc->sc_curmsg->flags & IIC_M_RD)) { 667 bcm_bsc_fill_tx_fifo(sc); 668 } 669 670 /* Wait for the transaction to complete. */ 671 while (err == 0 && !(sc->sc_flags & BCM_I2C_DONE)) { 672 err = mtx_sleep(sc, &sc->sc_mtx, 0, "bsciow", hz); 673 } 674 /* Check for errors. */ 675 if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR)) 676 err = EIO; 677 xfer_done: 678 DEBUGF(sc, 1, " err=%d\n", err); 679 DEVICE_DEBUGF(sc, 2, "stop\n"); 680 if (err != 0) 681 break; 682 } 683 684 /* Disable interrupts, clean fifo, etc. */ 685 bcm_bsc_reset(sc); 686 687 /* Clean the controller flags. */ 688 sc->sc_flags = 0; 689 690 /* Wake up the threads waiting for bus. */ 691 wakeup(dev); 692 693 BCM_BSC_UNLOCK(sc); 694 695 return (err); 696 } 697 698 static int 699 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 700 { 701 struct bcm_bsc_softc *sc; 702 uint32_t busfreq; 703 704 sc = device_get_softc(dev); 705 BCM_BSC_LOCK(sc); 706 bcm_bsc_reset(sc); 707 if (sc->sc_iicbus == NULL) 708 busfreq = 100000; 709 else 710 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 711 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq); 712 BCM_BSC_UNLOCK(sc); 713 714 return (IIC_ENOADDR); 715 } 716 717 static phandle_t 718 bcm_bsc_get_node(device_t bus, device_t dev) 719 { 720 721 /* We only have one child, the I2C bus, which needs our own node. */ 722 return (ofw_bus_get_node(bus)); 723 } 724 725 static device_method_t bcm_bsc_methods[] = { 726 /* Device interface */ 727 DEVMETHOD(device_probe, bcm_bsc_probe), 728 DEVMETHOD(device_attach, bcm_bsc_attach), 729 DEVMETHOD(device_detach, bcm_bsc_detach), 730 731 /* iicbus interface */ 732 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset), 733 DEVMETHOD(iicbus_callback, iicbus_null_callback), 734 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), 735 736 /* ofw_bus interface */ 737 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), 738 739 DEVMETHOD_END 740 }; 741 742 static devclass_t bcm_bsc_devclass; 743 744 static driver_t bcm_bsc_driver = { 745 "iichb", 746 bcm_bsc_methods, 747 sizeof(struct bcm_bsc_softc), 748 }; 749 750 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0); 751 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); 752