1 /*- 2 * Copyright (c) 2001 Tsubai Masanari. 3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 4 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/bus.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 44 #include <dev/iicbus/iicbus.h> 45 #include <dev/iicbus/iiconf.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 50 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h> 51 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h> 52 53 #include "iicbus_if.h" 54 55 static void bcm_bsc_intr(void *); 56 57 static void 58 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, 59 uint32_t value) 60 { 61 uint32_t reg; 62 63 mtx_assert(&sc->sc_mtx, MA_OWNED); 64 reg = BCM_BSC_READ(sc, off); 65 reg &= ~mask; 66 reg |= value; 67 BCM_BSC_WRITE(sc, off, reg); 68 } 69 70 static int 71 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) 72 { 73 struct bcm_bsc_softc *sc; 74 uint32_t clk; 75 int error; 76 77 sc = (struct bcm_bsc_softc *)arg1; 78 79 BCM_BSC_LOCK(sc); 80 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 81 BCM_BSC_UNLOCK(sc); 82 clk &= 0xffff; 83 if (clk == 0) 84 clk = 32768; 85 clk = BCM_BSC_CORE_CLK / clk; 86 error = sysctl_handle_int(oidp, &clk, sizeof(clk), req); 87 if (error != 0 || req->newptr == NULL) 88 return (error); 89 90 clk = BCM_BSC_CORE_CLK / clk; 91 if (clk % 2) 92 clk--; 93 if (clk > 0xffff) 94 clk = 0xffff; 95 BCM_BSC_LOCK(sc); 96 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, clk); 97 BCM_BSC_UNLOCK(sc); 98 99 return (0); 100 } 101 102 static int 103 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) 104 { 105 struct bcm_bsc_softc *sc; 106 uint32_t clkt; 107 int error; 108 109 sc = (struct bcm_bsc_softc *)arg1; 110 111 BCM_BSC_LOCK(sc); 112 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); 113 BCM_BSC_UNLOCK(sc); 114 clkt &= 0xffff; 115 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); 116 if (error != 0 || req->newptr == NULL) 117 return (error); 118 119 BCM_BSC_LOCK(sc); 120 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); 121 BCM_BSC_UNLOCK(sc); 122 123 return (0); 124 } 125 126 static int 127 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) 128 { 129 struct bcm_bsc_softc *sc; 130 uint32_t clk, reg; 131 int error; 132 133 sc = (struct bcm_bsc_softc *)arg1; 134 135 BCM_BSC_LOCK(sc); 136 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 137 BCM_BSC_UNLOCK(sc); 138 reg >>= 16; 139 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 140 if (error != 0 || req->newptr == NULL) 141 return (error); 142 143 BCM_BSC_LOCK(sc); 144 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 145 clk = BCM_BSC_CORE_CLK / clk; 146 if (reg > clk / 2) 147 reg = clk / 2 - 1; 148 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); 149 BCM_BSC_UNLOCK(sc); 150 151 return (0); 152 } 153 154 static int 155 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) 156 { 157 struct bcm_bsc_softc *sc; 158 uint32_t clk, reg; 159 int error; 160 161 sc = (struct bcm_bsc_softc *)arg1; 162 163 BCM_BSC_LOCK(sc); 164 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 165 BCM_BSC_UNLOCK(sc); 166 reg &= 0xffff; 167 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 168 if (error != 0 || req->newptr == NULL) 169 return (error); 170 171 BCM_BSC_LOCK(sc); 172 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 173 clk = BCM_BSC_CORE_CLK / clk; 174 if (reg > clk / 2) 175 reg = clk / 2 - 1; 176 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); 177 BCM_BSC_UNLOCK(sc); 178 179 return (0); 180 } 181 182 static void 183 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) 184 { 185 struct sysctl_ctx_list *ctx; 186 struct sysctl_oid *tree_node; 187 struct sysctl_oid_list *tree; 188 189 /* 190 * Add system sysctl tree/handlers. 191 */ 192 ctx = device_get_sysctl_ctx(sc->sc_dev); 193 tree_node = device_get_sysctl_tree(sc->sc_dev); 194 tree = SYSCTL_CHILDREN(tree_node); 195 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock", 196 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 197 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); 198 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", 199 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 200 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); 201 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", 202 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 203 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); 204 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", 205 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 206 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); 207 } 208 209 static void 210 bcm_bsc_reset(struct bcm_bsc_softc *sc) 211 { 212 213 /* Clear pending interrupts. */ 214 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | 215 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); 216 /* Clear the FIFO. */ 217 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, 218 BCM_BSC_CTRL_CLEAR0); 219 } 220 221 static int 222 bcm_bsc_probe(device_t dev) 223 { 224 225 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-bsc")) 226 return (ENXIO); 227 228 device_set_desc(dev, "BCM2708/2835 BSC controller"); 229 230 return (BUS_PROBE_DEFAULT); 231 } 232 233 static int 234 bcm_bsc_attach(device_t dev) 235 { 236 struct bcm_bsc_softc *sc; 237 unsigned long start; 238 device_t gpio; 239 int i, rid; 240 241 sc = device_get_softc(dev); 242 sc->sc_dev = dev; 243 244 rid = 0; 245 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 246 RF_ACTIVE); 247 if (!sc->sc_mem_res) { 248 device_printf(dev, "cannot allocate memory window\n"); 249 return (ENXIO); 250 } 251 252 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 253 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 254 255 /* Check the unit we are attaching by its base address. */ 256 start = rman_get_start(sc->sc_mem_res); 257 for (i = 0; i < nitems(bcm_bsc_pins); i++) { 258 if (bcm_bsc_pins[i].start == start) 259 break; 260 } 261 if (i == nitems(bcm_bsc_pins)) { 262 device_printf(dev, "only bsc0 and bsc1 are supported\n"); 263 return (ENXIO); 264 } 265 266 /* 267 * Configure the GPIO pins to ALT0 function to enable BSC control 268 * over the pins. 269 */ 270 gpio = devclass_get_device(devclass_find("gpio"), 0); 271 if (!gpio) { 272 device_printf(dev, "cannot find gpio0\n"); 273 return (ENXIO); 274 } 275 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0); 276 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0); 277 278 rid = 0; 279 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 280 RF_ACTIVE | RF_SHAREABLE); 281 if (!sc->sc_irq_res) { 282 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 283 device_printf(dev, "cannot allocate interrupt\n"); 284 return (ENXIO); 285 } 286 287 /* Hook up our interrupt handler. */ 288 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 289 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { 290 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 291 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 292 device_printf(dev, "cannot setup the interrupt handler\n"); 293 return (ENXIO); 294 } 295 296 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); 297 298 bcm_bsc_sysctl_init(sc); 299 300 /* Enable the BSC controller. Flush the FIFO. */ 301 BCM_BSC_LOCK(sc); 302 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 303 bcm_bsc_reset(sc); 304 BCM_BSC_UNLOCK(sc); 305 306 device_add_child(dev, "iicbus", -1); 307 308 return (bus_generic_attach(dev)); 309 } 310 311 static int 312 bcm_bsc_detach(device_t dev) 313 { 314 struct bcm_bsc_softc *sc; 315 316 bus_generic_detach(dev); 317 318 sc = device_get_softc(dev); 319 mtx_destroy(&sc->sc_mtx); 320 if (sc->sc_intrhand) 321 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 322 if (sc->sc_irq_res) 323 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 324 if (sc->sc_mem_res) 325 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 326 327 return (0); 328 } 329 330 static void 331 bcm_bsc_intr(void *arg) 332 { 333 struct bcm_bsc_softc *sc; 334 uint32_t status; 335 336 sc = (struct bcm_bsc_softc *)arg; 337 338 BCM_BSC_LOCK(sc); 339 340 /* The I2C interrupt is shared among all the BSC controllers. */ 341 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { 342 BCM_BSC_UNLOCK(sc); 343 return; 344 } 345 346 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 347 348 /* Check for errors. */ 349 if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) { 350 /* Disable interrupts. */ 351 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 352 sc->sc_flags |= BCM_I2C_ERROR; 353 bcm_bsc_reset(sc); 354 wakeup(sc->sc_dev); 355 BCM_BSC_UNLOCK(sc); 356 return; 357 } 358 359 if (sc->sc_flags & BCM_I2C_READ) { 360 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) { 361 *sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA); 362 sc->sc_resid--; 363 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 364 } 365 } else { 366 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) { 367 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++); 368 sc->sc_resid--; 369 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 370 } 371 } 372 373 if (status & BCM_BSC_STATUS_DONE) { 374 /* Disable interrupts. */ 375 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 376 bcm_bsc_reset(sc); 377 wakeup(sc->sc_dev); 378 } 379 380 BCM_BSC_UNLOCK(sc); 381 } 382 383 static int 384 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 385 { 386 struct bcm_bsc_softc *sc; 387 uint32_t intr, read, status; 388 int i, err; 389 390 sc = device_get_softc(dev); 391 BCM_BSC_LOCK(sc); 392 393 /* If the controller is busy wait until it is available. */ 394 while (sc->sc_flags & BCM_I2C_BUSY) 395 mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_bsc", 0); 396 397 /* Now we have control over the BSC controller. */ 398 sc->sc_flags = BCM_I2C_BUSY; 399 400 /* Clear the FIFO and the pending interrupts. */ 401 bcm_bsc_reset(sc); 402 403 err = 0; 404 for (i = 0; i < nmsgs; i++) { 405 406 /* Write the slave address. */ 407 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, (msgs[i].slave >> 1) & 0x7f); 408 409 /* Write the data length. */ 410 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len); 411 412 sc->sc_data = msgs[i].buf; 413 sc->sc_resid = msgs[i].len; 414 if ((msgs[i].flags & IIC_M_RD) == 0) { 415 /* Fill up the TX FIFO. */ 416 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 417 while (sc->sc_resid > 0 && 418 (status & BCM_BSC_STATUS_TXD)) { 419 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); 420 sc->sc_data++; 421 sc->sc_resid--; 422 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 423 } 424 read = 0; 425 intr = BCM_BSC_CTRL_INTT; 426 sc->sc_flags &= ~BCM_I2C_READ; 427 } else { 428 sc->sc_flags |= BCM_I2C_READ; 429 read = BCM_BSC_CTRL_READ; 430 intr = BCM_BSC_CTRL_INTR; 431 } 432 intr |= BCM_BSC_CTRL_INTD; 433 434 /* Start the transfer. */ 435 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | 436 BCM_BSC_CTRL_ST | read | intr); 437 438 /* Wait for the transaction to complete. */ 439 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_bsc", hz); 440 441 /* Check if we have a timeout or an I2C error. */ 442 if ((sc->sc_flags & BCM_I2C_ERROR) || err == EWOULDBLOCK) { 443 device_printf(sc->sc_dev, "I2C error\n"); 444 err = EIO; 445 break; 446 } 447 } 448 449 /* Clean the controller flags. */ 450 sc->sc_flags = 0; 451 452 BCM_BSC_UNLOCK(sc); 453 454 return (err); 455 } 456 457 static phandle_t 458 bcm_bsc_get_node(device_t bus, device_t dev) 459 { 460 461 /* We only have one child, the I2C bus, which needs our own node. */ 462 return (ofw_bus_get_node(bus)); 463 } 464 465 static device_method_t bcm_bsc_methods[] = { 466 /* Device interface */ 467 DEVMETHOD(device_probe, bcm_bsc_probe), 468 DEVMETHOD(device_attach, bcm_bsc_attach), 469 DEVMETHOD(device_detach, bcm_bsc_detach), 470 471 /* iicbus interface */ 472 DEVMETHOD(iicbus_callback, iicbus_null_callback), 473 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), 474 475 /* ofw_bus interface */ 476 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), 477 478 DEVMETHOD_END 479 }; 480 481 static devclass_t bcm_bsc_devclass; 482 483 static driver_t bcm_bsc_driver = { 484 "iichb", 485 bcm_bsc_methods, 486 sizeof(struct bcm_bsc_softc), 487 }; 488 489 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0); 490 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); 491