xref: /freebsd/sys/arm/broadcom/bcm2835/bcm2835_bsc.c (revision 86c9d9918f1db7cdd968b60f8902466887bcd9e9)
1 /*-
2  * Copyright (c) 2001 Tsubai Masanari.
3  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4  * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  */
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/lock.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/bus.h>
39 #include <machine/resource.h>
40 #include <machine/bus.h>
41 #include <sys/rman.h>
42 #include <sys/sysctl.h>
43 
44 #include <dev/iicbus/iicbus.h>
45 #include <dev/iicbus/iiconf.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48 
49 #include <arm/broadcom/bcm2835/bcm2835_gpio.h>
50 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h>
51 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h>
52 
53 #include "iicbus_if.h"
54 
55 static void bcm_bsc_intr(void *);
56 static int bcm_bsc_detach(device_t);
57 
58 static void
59 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask,
60 	uint32_t value)
61 {
62 	uint32_t reg;
63 
64 	mtx_assert(&sc->sc_mtx, MA_OWNED);
65 	reg = BCM_BSC_READ(sc, off);
66 	reg &= ~mask;
67 	reg |= value;
68 	BCM_BSC_WRITE(sc, off, reg);
69 }
70 
71 static int
72 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS)
73 {
74 	struct bcm_bsc_softc *sc;
75 	uint32_t clk;
76 
77 	sc = (struct bcm_bsc_softc *)arg1;
78 	BCM_BSC_LOCK(sc);
79 	clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
80 	BCM_BSC_UNLOCK(sc);
81 	clk &= 0xffff;
82 	if (clk == 0)
83 		clk = 32768;
84 	clk = BCM_BSC_CORE_CLK / clk;
85 
86 	return (sysctl_handle_int(oidp, &clk, 0, req));
87 }
88 
89 static int
90 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS)
91 {
92 	struct bcm_bsc_softc *sc;
93 	uint32_t clkt;
94 	int error;
95 
96 	sc = (struct bcm_bsc_softc *)arg1;
97 
98 	BCM_BSC_LOCK(sc);
99 	clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT);
100 	BCM_BSC_UNLOCK(sc);
101 	clkt &= 0xffff;
102 	error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req);
103 	if (error != 0 || req->newptr == NULL)
104 		return (error);
105 
106 	BCM_BSC_LOCK(sc);
107 	BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff);
108 	BCM_BSC_UNLOCK(sc);
109 
110 	return (0);
111 }
112 
113 static int
114 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS)
115 {
116 	struct bcm_bsc_softc *sc;
117 	uint32_t clk, reg;
118 	int error;
119 
120 	sc = (struct bcm_bsc_softc *)arg1;
121 
122 	BCM_BSC_LOCK(sc);
123 	reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
124 	BCM_BSC_UNLOCK(sc);
125 	reg >>= 16;
126 	error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);
127 	if (error != 0 || req->newptr == NULL)
128 		return (error);
129 
130 	BCM_BSC_LOCK(sc);
131 	clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
132 	clk = BCM_BSC_CORE_CLK / clk;
133 	if (reg > clk / 2)
134 		reg = clk / 2 - 1;
135 	bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16);
136 	BCM_BSC_UNLOCK(sc);
137 
138 	return (0);
139 }
140 
141 static int
142 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS)
143 {
144 	struct bcm_bsc_softc *sc;
145 	uint32_t clk, reg;
146 	int error;
147 
148 	sc = (struct bcm_bsc_softc *)arg1;
149 
150 	BCM_BSC_LOCK(sc);
151 	reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
152 	BCM_BSC_UNLOCK(sc);
153 	reg &= 0xffff;
154 	error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);
155 	if (error != 0 || req->newptr == NULL)
156 		return (error);
157 
158 	BCM_BSC_LOCK(sc);
159 	clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
160 	clk = BCM_BSC_CORE_CLK / clk;
161 	if (reg > clk / 2)
162 		reg = clk / 2 - 1;
163 	bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg);
164 	BCM_BSC_UNLOCK(sc);
165 
166 	return (0);
167 }
168 
169 static void
170 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc)
171 {
172 	struct sysctl_ctx_list *ctx;
173 	struct sysctl_oid *tree_node;
174 	struct sysctl_oid_list *tree;
175 
176 	/*
177 	 * Add system sysctl tree/handlers.
178 	 */
179 	ctx = device_get_sysctl_ctx(sc->sc_dev);
180 	tree_node = device_get_sysctl_tree(sc->sc_dev);
181 	tree = SYSCTL_CHILDREN(tree_node);
182 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency",
183 	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
184 	    bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency");
185 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch",
186 	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
187 	    bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout");
188 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay",
189 	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
190 	    bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay");
191 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay",
192 	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
193 	    bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay");
194 }
195 
196 static void
197 bcm_bsc_reset(struct bcm_bsc_softc *sc)
198 {
199 
200 	/* Enable the BSC Controller, disable interrupts. */
201 	BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN);
202 	/* Clear pending interrupts. */
203 	BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT |
204 	    BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE);
205 	/* Clear the FIFO. */
206 	bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0,
207 	    BCM_BSC_CTRL_CLEAR0);
208 }
209 
210 static int
211 bcm_bsc_probe(device_t dev)
212 {
213 
214 	if (!ofw_bus_status_okay(dev))
215 		return (ENXIO);
216 
217 	if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-bsc"))
218 		return (ENXIO);
219 
220 	device_set_desc(dev, "BCM2708/2835 BSC controller");
221 
222 	return (BUS_PROBE_DEFAULT);
223 }
224 
225 static int
226 bcm_bsc_attach(device_t dev)
227 {
228 	struct bcm_bsc_softc *sc;
229 	unsigned long start;
230 	device_t gpio;
231 	int i, rid;
232 
233 	sc = device_get_softc(dev);
234 	sc->sc_dev = dev;
235 
236 	rid = 0;
237 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
238 	    RF_ACTIVE);
239 	if (!sc->sc_mem_res) {
240 		device_printf(dev, "cannot allocate memory window\n");
241 		return (ENXIO);
242 	}
243 
244 	sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
245 	sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
246 
247 	/* Check the unit we are attaching by its base address. */
248 	start = rman_get_start(sc->sc_mem_res);
249 	for (i = 0; i < nitems(bcm_bsc_pins); i++) {
250 		if (bcm_bsc_pins[i].start == (start & BCM_BSC_BASE_MASK))
251 			break;
252 	}
253 	if (i == nitems(bcm_bsc_pins)) {
254 		device_printf(dev, "only bsc0 and bsc1 are supported\n");
255 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
256 		return (ENXIO);
257 	}
258 
259 	/*
260 	 * Configure the GPIO pins to ALT0 function to enable BSC control
261 	 * over the pins.
262 	 */
263 	gpio = devclass_get_device(devclass_find("gpio"), 0);
264 	if (!gpio) {
265 		device_printf(dev, "cannot find gpio0\n");
266 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
267 		return (ENXIO);
268 	}
269 	bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0);
270 	bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0);
271 
272 	rid = 0;
273 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
274 	    RF_ACTIVE | RF_SHAREABLE);
275 	if (!sc->sc_irq_res) {
276 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
277 		device_printf(dev, "cannot allocate interrupt\n");
278 		return (ENXIO);
279 	}
280 
281 	/* Hook up our interrupt handler. */
282 	if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
283 	    NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) {
284 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
285 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
286 		device_printf(dev, "cannot setup the interrupt handler\n");
287 		return (ENXIO);
288 	}
289 
290 	mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF);
291 
292 	bcm_bsc_sysctl_init(sc);
293 
294 	/* Enable the BSC controller.  Flush the FIFO. */
295 	BCM_BSC_LOCK(sc);
296 	bcm_bsc_reset(sc);
297 	BCM_BSC_UNLOCK(sc);
298 
299 	sc->sc_iicbus = device_add_child(dev, "iicbus", -1);
300 	if (sc->sc_iicbus == NULL) {
301 		bcm_bsc_detach(dev);
302 		return (ENXIO);
303 	}
304 
305 	return (bus_generic_attach(dev));
306 }
307 
308 static int
309 bcm_bsc_detach(device_t dev)
310 {
311 	struct bcm_bsc_softc *sc;
312 
313 	bus_generic_detach(dev);
314 
315 	sc = device_get_softc(dev);
316 	mtx_destroy(&sc->sc_mtx);
317 	if (sc->sc_intrhand)
318 		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
319 	if (sc->sc_irq_res)
320 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
321 	if (sc->sc_mem_res)
322 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
323 
324 	return (0);
325 }
326 
327 static void
328 bcm_bsc_intr(void *arg)
329 {
330 	struct bcm_bsc_softc *sc;
331 	uint32_t status;
332 
333 	sc = (struct bcm_bsc_softc *)arg;
334 
335 	BCM_BSC_LOCK(sc);
336 
337 	/* The I2C interrupt is shared among all the BSC controllers. */
338 	if ((sc->sc_flags & BCM_I2C_BUSY) == 0) {
339 		BCM_BSC_UNLOCK(sc);
340 		return;
341 	}
342 
343 	status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
344 
345 	/* Check for errors. */
346 	if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) {
347 		/* Disable interrupts. */
348 		bcm_bsc_reset(sc);
349 		sc->sc_flags |= BCM_I2C_ERROR;
350 		wakeup(sc->sc_dev);
351 		BCM_BSC_UNLOCK(sc);
352 		return;
353 	}
354 
355 	if (sc->sc_flags & BCM_I2C_READ) {
356 		while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) {
357 			*sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA);
358 			sc->sc_resid--;
359 			status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
360 		}
361 	} else {
362 		while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) {
363 			BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++);
364 			sc->sc_resid--;
365 			status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
366 		}
367 	}
368 
369 	if (status & BCM_BSC_STATUS_DONE) {
370 		/* Disable interrupts. */
371 		bcm_bsc_reset(sc);
372 		wakeup(sc->sc_dev);
373 	}
374 
375 	BCM_BSC_UNLOCK(sc);
376 }
377 
378 static int
379 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
380 {
381 	struct bcm_bsc_softc *sc;
382 	uint32_t intr, read, status;
383 	int i, err;
384 
385 	sc = device_get_softc(dev);
386 	BCM_BSC_LOCK(sc);
387 
388 	/* If the controller is busy wait until it is available. */
389 	while (sc->sc_flags & BCM_I2C_BUSY)
390 		mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0);
391 
392 	/* Now we have control over the BSC controller. */
393 	sc->sc_flags = BCM_I2C_BUSY;
394 
395 	/* Clear the FIFO and the pending interrupts. */
396 	bcm_bsc_reset(sc);
397 
398 	err = 0;
399 	for (i = 0; i < nmsgs; i++) {
400 
401 		/* Write the slave address. */
402 		BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, msgs[i].slave >> 1);
403 
404 		/* Write the data length. */
405 		BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len);
406 
407 		sc->sc_data = msgs[i].buf;
408 		sc->sc_resid = msgs[i].len;
409 		if ((msgs[i].flags & IIC_M_RD) == 0) {
410 			/* Fill up the TX FIFO. */
411 			status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
412 			while (sc->sc_resid > 0 &&
413 			    (status & BCM_BSC_STATUS_TXD)) {
414 				BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data);
415 				sc->sc_data++;
416 				sc->sc_resid--;
417 				status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
418 			}
419 			read = 0;
420 			intr = BCM_BSC_CTRL_INTT;
421 			sc->sc_flags &= ~BCM_I2C_READ;
422 		} else {
423 			sc->sc_flags |= BCM_I2C_READ;
424 			read = BCM_BSC_CTRL_READ;
425 			intr = BCM_BSC_CTRL_INTR;
426 		}
427 		intr |= BCM_BSC_CTRL_INTD;
428 
429 		/* Start the transfer. */
430 		BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN |
431 		    BCM_BSC_CTRL_ST | read | intr);
432 
433 		/* Wait for the transaction to complete. */
434 		err = mtx_sleep(dev, &sc->sc_mtx, 0, "bsciow", hz);
435 
436 		/* Check for errors. */
437 		if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR))
438 			err = EIO;
439 		if (err != 0)
440 			break;
441 	}
442 
443 	/* Clean the controller flags. */
444 	sc->sc_flags = 0;
445 
446 	/* Wake up the threads waiting for bus. */
447 	wakeup(dev);
448 
449 	BCM_BSC_UNLOCK(sc);
450 
451 	return (err);
452 }
453 
454 static int
455 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
456 {
457 	struct bcm_bsc_softc *sc;
458 	uint32_t busfreq;
459 
460 	sc = device_get_softc(dev);
461 	BCM_BSC_LOCK(sc);
462 	bcm_bsc_reset(sc);
463 	if (sc->sc_iicbus == NULL)
464 		busfreq = 100000;
465 	else
466 		busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
467 	BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq);
468 	BCM_BSC_UNLOCK(sc);
469 
470 	return (IIC_ENOADDR);
471 }
472 
473 static phandle_t
474 bcm_bsc_get_node(device_t bus, device_t dev)
475 {
476 
477 	/* We only have one child, the I2C bus, which needs our own node. */
478 	return (ofw_bus_get_node(bus));
479 }
480 
481 static device_method_t bcm_bsc_methods[] = {
482 	/* Device interface */
483 	DEVMETHOD(device_probe,		bcm_bsc_probe),
484 	DEVMETHOD(device_attach,	bcm_bsc_attach),
485 	DEVMETHOD(device_detach,	bcm_bsc_detach),
486 
487 	/* iicbus interface */
488 	DEVMETHOD(iicbus_reset,		bcm_bsc_iicbus_reset),
489 	DEVMETHOD(iicbus_callback,	iicbus_null_callback),
490 	DEVMETHOD(iicbus_transfer,	bcm_bsc_transfer),
491 
492 	/* ofw_bus interface */
493 	DEVMETHOD(ofw_bus_get_node,	bcm_bsc_get_node),
494 
495 	DEVMETHOD_END
496 };
497 
498 static devclass_t bcm_bsc_devclass;
499 
500 static driver_t bcm_bsc_driver = {
501 	"iichb",
502 	bcm_bsc_methods,
503 	sizeof(struct bcm_bsc_softc),
504 };
505 
506 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0);
507 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0);
508