1 /*- 2 * Copyright (c) 2001 Tsubai Masanari. 3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 4 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/bus.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 44 #include <dev/iicbus/iicbus.h> 45 #include <dev/iicbus/iiconf.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 50 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h> 51 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h> 52 53 #include "iicbus_if.h" 54 55 static struct ofw_compat_data compat_data[] = { 56 {"broadcom,bcm2835-bsc", 1}, 57 {"brcm,bcm2708-i2c", 1}, 58 {NULL, 0} 59 }; 60 61 static void bcm_bsc_intr(void *); 62 static int bcm_bsc_detach(device_t); 63 64 static void 65 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, 66 uint32_t value) 67 { 68 uint32_t reg; 69 70 mtx_assert(&sc->sc_mtx, MA_OWNED); 71 reg = BCM_BSC_READ(sc, off); 72 reg &= ~mask; 73 reg |= value; 74 BCM_BSC_WRITE(sc, off, reg); 75 } 76 77 static int 78 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) 79 { 80 struct bcm_bsc_softc *sc; 81 uint32_t clk; 82 83 sc = (struct bcm_bsc_softc *)arg1; 84 BCM_BSC_LOCK(sc); 85 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 86 BCM_BSC_UNLOCK(sc); 87 clk &= 0xffff; 88 if (clk == 0) 89 clk = 32768; 90 clk = BCM_BSC_CORE_CLK / clk; 91 92 return (sysctl_handle_int(oidp, &clk, 0, req)); 93 } 94 95 static int 96 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) 97 { 98 struct bcm_bsc_softc *sc; 99 uint32_t clkt; 100 int error; 101 102 sc = (struct bcm_bsc_softc *)arg1; 103 104 BCM_BSC_LOCK(sc); 105 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); 106 BCM_BSC_UNLOCK(sc); 107 clkt &= 0xffff; 108 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); 109 if (error != 0 || req->newptr == NULL) 110 return (error); 111 112 BCM_BSC_LOCK(sc); 113 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); 114 BCM_BSC_UNLOCK(sc); 115 116 return (0); 117 } 118 119 static int 120 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) 121 { 122 struct bcm_bsc_softc *sc; 123 uint32_t clk, reg; 124 int error; 125 126 sc = (struct bcm_bsc_softc *)arg1; 127 128 BCM_BSC_LOCK(sc); 129 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 130 BCM_BSC_UNLOCK(sc); 131 reg >>= 16; 132 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 133 if (error != 0 || req->newptr == NULL) 134 return (error); 135 136 BCM_BSC_LOCK(sc); 137 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 138 clk = BCM_BSC_CORE_CLK / clk; 139 if (reg > clk / 2) 140 reg = clk / 2 - 1; 141 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); 142 BCM_BSC_UNLOCK(sc); 143 144 return (0); 145 } 146 147 static int 148 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) 149 { 150 struct bcm_bsc_softc *sc; 151 uint32_t clk, reg; 152 int error; 153 154 sc = (struct bcm_bsc_softc *)arg1; 155 156 BCM_BSC_LOCK(sc); 157 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 158 BCM_BSC_UNLOCK(sc); 159 reg &= 0xffff; 160 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 161 if (error != 0 || req->newptr == NULL) 162 return (error); 163 164 BCM_BSC_LOCK(sc); 165 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 166 clk = BCM_BSC_CORE_CLK / clk; 167 if (reg > clk / 2) 168 reg = clk / 2 - 1; 169 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); 170 BCM_BSC_UNLOCK(sc); 171 172 return (0); 173 } 174 175 static void 176 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) 177 { 178 struct sysctl_ctx_list *ctx; 179 struct sysctl_oid *tree_node; 180 struct sysctl_oid_list *tree; 181 182 /* 183 * Add system sysctl tree/handlers. 184 */ 185 ctx = device_get_sysctl_ctx(sc->sc_dev); 186 tree_node = device_get_sysctl_tree(sc->sc_dev); 187 tree = SYSCTL_CHILDREN(tree_node); 188 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency", 189 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 190 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); 191 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", 192 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 193 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); 194 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", 195 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 196 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); 197 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", 198 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 199 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); 200 } 201 202 static void 203 bcm_bsc_reset(struct bcm_bsc_softc *sc) 204 { 205 206 /* Enable the BSC Controller, disable interrupts. */ 207 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 208 /* Clear pending interrupts. */ 209 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | 210 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); 211 /* Clear the FIFO. */ 212 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, 213 BCM_BSC_CTRL_CLEAR0); 214 } 215 216 static int 217 bcm_bsc_probe(device_t dev) 218 { 219 220 if (!ofw_bus_status_okay(dev)) 221 return (ENXIO); 222 223 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 224 return (ENXIO); 225 226 device_set_desc(dev, "BCM2708/2835 BSC controller"); 227 228 return (BUS_PROBE_DEFAULT); 229 } 230 231 static int 232 bcm_bsc_attach(device_t dev) 233 { 234 struct bcm_bsc_softc *sc; 235 unsigned long start; 236 device_t gpio; 237 int i, rid; 238 239 sc = device_get_softc(dev); 240 sc->sc_dev = dev; 241 242 rid = 0; 243 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 244 RF_ACTIVE); 245 if (!sc->sc_mem_res) { 246 device_printf(dev, "cannot allocate memory window\n"); 247 return (ENXIO); 248 } 249 250 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 251 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 252 253 /* Check the unit we are attaching by its base address. */ 254 start = rman_get_start(sc->sc_mem_res); 255 for (i = 0; i < nitems(bcm_bsc_pins); i++) { 256 if (bcm_bsc_pins[i].start == (start & BCM_BSC_BASE_MASK)) 257 break; 258 } 259 if (i == nitems(bcm_bsc_pins)) { 260 device_printf(dev, "only bsc0 and bsc1 are supported\n"); 261 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 262 return (ENXIO); 263 } 264 265 /* 266 * Configure the GPIO pins to ALT0 function to enable BSC control 267 * over the pins. 268 */ 269 gpio = devclass_get_device(devclass_find("gpio"), 0); 270 if (!gpio) { 271 device_printf(dev, "cannot find gpio0\n"); 272 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 273 return (ENXIO); 274 } 275 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0); 276 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0); 277 278 rid = 0; 279 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 280 RF_ACTIVE | RF_SHAREABLE); 281 if (!sc->sc_irq_res) { 282 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 283 device_printf(dev, "cannot allocate interrupt\n"); 284 return (ENXIO); 285 } 286 287 /* Hook up our interrupt handler. */ 288 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 289 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { 290 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 291 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 292 device_printf(dev, "cannot setup the interrupt handler\n"); 293 return (ENXIO); 294 } 295 296 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); 297 298 bcm_bsc_sysctl_init(sc); 299 300 /* Enable the BSC controller. Flush the FIFO. */ 301 BCM_BSC_LOCK(sc); 302 bcm_bsc_reset(sc); 303 BCM_BSC_UNLOCK(sc); 304 305 sc->sc_iicbus = device_add_child(dev, "iicbus", -1); 306 if (sc->sc_iicbus == NULL) { 307 bcm_bsc_detach(dev); 308 return (ENXIO); 309 } 310 311 return (bus_generic_attach(dev)); 312 } 313 314 static int 315 bcm_bsc_detach(device_t dev) 316 { 317 struct bcm_bsc_softc *sc; 318 319 bus_generic_detach(dev); 320 321 sc = device_get_softc(dev); 322 mtx_destroy(&sc->sc_mtx); 323 if (sc->sc_intrhand) 324 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 325 if (sc->sc_irq_res) 326 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 327 if (sc->sc_mem_res) 328 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 329 330 return (0); 331 } 332 333 static void 334 bcm_bsc_intr(void *arg) 335 { 336 struct bcm_bsc_softc *sc; 337 uint32_t status; 338 339 sc = (struct bcm_bsc_softc *)arg; 340 341 BCM_BSC_LOCK(sc); 342 343 /* The I2C interrupt is shared among all the BSC controllers. */ 344 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { 345 BCM_BSC_UNLOCK(sc); 346 return; 347 } 348 349 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 350 351 /* Check for errors. */ 352 if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) { 353 /* Disable interrupts. */ 354 bcm_bsc_reset(sc); 355 sc->sc_flags |= BCM_I2C_ERROR; 356 wakeup(sc->sc_dev); 357 BCM_BSC_UNLOCK(sc); 358 return; 359 } 360 361 if (sc->sc_flags & BCM_I2C_READ) { 362 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) { 363 *sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA); 364 sc->sc_resid--; 365 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 366 } 367 } else { 368 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) { 369 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++); 370 sc->sc_resid--; 371 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 372 } 373 } 374 375 if (status & BCM_BSC_STATUS_DONE) { 376 /* Disable interrupts. */ 377 bcm_bsc_reset(sc); 378 wakeup(sc->sc_dev); 379 } 380 381 BCM_BSC_UNLOCK(sc); 382 } 383 384 static int 385 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 386 { 387 struct bcm_bsc_softc *sc; 388 uint32_t intr, read, status; 389 int i, err; 390 391 sc = device_get_softc(dev); 392 BCM_BSC_LOCK(sc); 393 394 /* If the controller is busy wait until it is available. */ 395 while (sc->sc_flags & BCM_I2C_BUSY) 396 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0); 397 398 /* Now we have control over the BSC controller. */ 399 sc->sc_flags = BCM_I2C_BUSY; 400 401 /* Clear the FIFO and the pending interrupts. */ 402 bcm_bsc_reset(sc); 403 404 err = 0; 405 for (i = 0; i < nmsgs; i++) { 406 407 /* Write the slave address. */ 408 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, msgs[i].slave >> 1); 409 410 /* Write the data length. */ 411 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len); 412 413 sc->sc_data = msgs[i].buf; 414 sc->sc_resid = msgs[i].len; 415 if ((msgs[i].flags & IIC_M_RD) == 0) { 416 /* Fill up the TX FIFO. */ 417 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 418 while (sc->sc_resid > 0 && 419 (status & BCM_BSC_STATUS_TXD)) { 420 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); 421 sc->sc_data++; 422 sc->sc_resid--; 423 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 424 } 425 read = 0; 426 intr = BCM_BSC_CTRL_INTT; 427 sc->sc_flags &= ~BCM_I2C_READ; 428 } else { 429 sc->sc_flags |= BCM_I2C_READ; 430 read = BCM_BSC_CTRL_READ; 431 intr = BCM_BSC_CTRL_INTR; 432 } 433 intr |= BCM_BSC_CTRL_INTD; 434 435 /* Start the transfer. */ 436 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | 437 BCM_BSC_CTRL_ST | read | intr); 438 439 /* Wait for the transaction to complete. */ 440 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bsciow", hz); 441 442 /* Check for errors. */ 443 if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR)) 444 err = EIO; 445 if (err != 0) 446 break; 447 } 448 449 /* Clean the controller flags. */ 450 sc->sc_flags = 0; 451 452 /* Wake up the threads waiting for bus. */ 453 wakeup(dev); 454 455 BCM_BSC_UNLOCK(sc); 456 457 return (err); 458 } 459 460 static int 461 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 462 { 463 struct bcm_bsc_softc *sc; 464 uint32_t busfreq; 465 466 sc = device_get_softc(dev); 467 BCM_BSC_LOCK(sc); 468 bcm_bsc_reset(sc); 469 if (sc->sc_iicbus == NULL) 470 busfreq = 100000; 471 else 472 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 473 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq); 474 BCM_BSC_UNLOCK(sc); 475 476 return (IIC_ENOADDR); 477 } 478 479 static phandle_t 480 bcm_bsc_get_node(device_t bus, device_t dev) 481 { 482 483 /* We only have one child, the I2C bus, which needs our own node. */ 484 return (ofw_bus_get_node(bus)); 485 } 486 487 static device_method_t bcm_bsc_methods[] = { 488 /* Device interface */ 489 DEVMETHOD(device_probe, bcm_bsc_probe), 490 DEVMETHOD(device_attach, bcm_bsc_attach), 491 DEVMETHOD(device_detach, bcm_bsc_detach), 492 493 /* iicbus interface */ 494 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset), 495 DEVMETHOD(iicbus_callback, iicbus_null_callback), 496 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), 497 498 /* ofw_bus interface */ 499 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), 500 501 DEVMETHOD_END 502 }; 503 504 static devclass_t bcm_bsc_devclass; 505 506 static driver_t bcm_bsc_driver = { 507 "iichb", 508 bcm_bsc_methods, 509 sizeof(struct bcm_bsc_softc), 510 }; 511 512 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0); 513 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); 514