1 /*- 2 * Copyright (c) 2001 Tsubai Masanari. 3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 4 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/bus.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 44 #include <dev/iicbus/iicbus.h> 45 #include <dev/iicbus/iiconf.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 50 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h> 51 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h> 52 53 #include "iicbus_if.h" 54 55 static struct ofw_compat_data compat_data[] = { 56 {"broadcom,bcm2835-bsc", 1}, 57 {"brcm,bcm2708-i2c", 1}, 58 {"brcm,bcm2835-i2c", 1}, 59 {NULL, 0} 60 }; 61 62 static void bcm_bsc_intr(void *); 63 static int bcm_bsc_detach(device_t); 64 65 static void 66 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, 67 uint32_t value) 68 { 69 uint32_t reg; 70 71 mtx_assert(&sc->sc_mtx, MA_OWNED); 72 reg = BCM_BSC_READ(sc, off); 73 reg &= ~mask; 74 reg |= value; 75 BCM_BSC_WRITE(sc, off, reg); 76 } 77 78 static int 79 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) 80 { 81 struct bcm_bsc_softc *sc; 82 uint32_t clk; 83 84 sc = (struct bcm_bsc_softc *)arg1; 85 BCM_BSC_LOCK(sc); 86 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 87 BCM_BSC_UNLOCK(sc); 88 clk &= 0xffff; 89 if (clk == 0) 90 clk = 32768; 91 clk = BCM_BSC_CORE_CLK / clk; 92 93 return (sysctl_handle_int(oidp, &clk, 0, req)); 94 } 95 96 static int 97 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) 98 { 99 struct bcm_bsc_softc *sc; 100 uint32_t clkt; 101 int error; 102 103 sc = (struct bcm_bsc_softc *)arg1; 104 105 BCM_BSC_LOCK(sc); 106 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); 107 BCM_BSC_UNLOCK(sc); 108 clkt &= 0xffff; 109 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); 110 if (error != 0 || req->newptr == NULL) 111 return (error); 112 113 BCM_BSC_LOCK(sc); 114 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); 115 BCM_BSC_UNLOCK(sc); 116 117 return (0); 118 } 119 120 static int 121 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) 122 { 123 struct bcm_bsc_softc *sc; 124 uint32_t clk, reg; 125 int error; 126 127 sc = (struct bcm_bsc_softc *)arg1; 128 129 BCM_BSC_LOCK(sc); 130 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 131 BCM_BSC_UNLOCK(sc); 132 reg >>= 16; 133 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 134 if (error != 0 || req->newptr == NULL) 135 return (error); 136 137 BCM_BSC_LOCK(sc); 138 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 139 clk = BCM_BSC_CORE_CLK / clk; 140 if (reg > clk / 2) 141 reg = clk / 2 - 1; 142 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); 143 BCM_BSC_UNLOCK(sc); 144 145 return (0); 146 } 147 148 static int 149 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) 150 { 151 struct bcm_bsc_softc *sc; 152 uint32_t clk, reg; 153 int error; 154 155 sc = (struct bcm_bsc_softc *)arg1; 156 157 BCM_BSC_LOCK(sc); 158 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 159 BCM_BSC_UNLOCK(sc); 160 reg &= 0xffff; 161 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 162 if (error != 0 || req->newptr == NULL) 163 return (error); 164 165 BCM_BSC_LOCK(sc); 166 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 167 clk = BCM_BSC_CORE_CLK / clk; 168 if (reg > clk / 2) 169 reg = clk / 2 - 1; 170 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); 171 BCM_BSC_UNLOCK(sc); 172 173 return (0); 174 } 175 176 static void 177 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) 178 { 179 struct sysctl_ctx_list *ctx; 180 struct sysctl_oid *tree_node; 181 struct sysctl_oid_list *tree; 182 183 /* 184 * Add system sysctl tree/handlers. 185 */ 186 ctx = device_get_sysctl_ctx(sc->sc_dev); 187 tree_node = device_get_sysctl_tree(sc->sc_dev); 188 tree = SYSCTL_CHILDREN(tree_node); 189 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency", 190 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 191 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); 192 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", 193 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 194 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); 195 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", 196 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 197 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); 198 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", 199 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 200 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); 201 } 202 203 static void 204 bcm_bsc_reset(struct bcm_bsc_softc *sc) 205 { 206 207 /* Enable the BSC Controller, disable interrupts. */ 208 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 209 /* Clear pending interrupts. */ 210 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | 211 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); 212 /* Clear the FIFO. */ 213 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, 214 BCM_BSC_CTRL_CLEAR0); 215 } 216 217 static int 218 bcm_bsc_probe(device_t dev) 219 { 220 221 if (!ofw_bus_status_okay(dev)) 222 return (ENXIO); 223 224 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 225 return (ENXIO); 226 227 device_set_desc(dev, "BCM2708/2835 BSC controller"); 228 229 return (BUS_PROBE_DEFAULT); 230 } 231 232 static int 233 bcm_bsc_attach(device_t dev) 234 { 235 struct bcm_bsc_softc *sc; 236 unsigned long start; 237 device_t gpio; 238 int i, rid; 239 240 sc = device_get_softc(dev); 241 sc->sc_dev = dev; 242 243 rid = 0; 244 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 245 RF_ACTIVE); 246 if (!sc->sc_mem_res) { 247 device_printf(dev, "cannot allocate memory window\n"); 248 return (ENXIO); 249 } 250 251 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 252 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 253 254 /* Check the unit we are attaching by its base address. */ 255 start = rman_get_start(sc->sc_mem_res); 256 for (i = 0; i < nitems(bcm_bsc_pins); i++) { 257 if (bcm_bsc_pins[i].start == (start & BCM_BSC_BASE_MASK)) 258 break; 259 } 260 if (i == nitems(bcm_bsc_pins)) { 261 device_printf(dev, "only bsc0 and bsc1 are supported\n"); 262 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 263 return (ENXIO); 264 } 265 266 /* 267 * Configure the GPIO pins to ALT0 function to enable BSC control 268 * over the pins. 269 */ 270 gpio = devclass_get_device(devclass_find("gpio"), 0); 271 if (!gpio) { 272 device_printf(dev, "cannot find gpio0\n"); 273 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 274 return (ENXIO); 275 } 276 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0); 277 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0); 278 279 rid = 0; 280 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 281 RF_ACTIVE | RF_SHAREABLE); 282 if (!sc->sc_irq_res) { 283 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 284 device_printf(dev, "cannot allocate interrupt\n"); 285 return (ENXIO); 286 } 287 288 /* Hook up our interrupt handler. */ 289 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 290 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { 291 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 292 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 293 device_printf(dev, "cannot setup the interrupt handler\n"); 294 return (ENXIO); 295 } 296 297 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); 298 299 bcm_bsc_sysctl_init(sc); 300 301 /* Enable the BSC controller. Flush the FIFO. */ 302 BCM_BSC_LOCK(sc); 303 bcm_bsc_reset(sc); 304 BCM_BSC_UNLOCK(sc); 305 306 sc->sc_iicbus = device_add_child(dev, "iicbus", -1); 307 if (sc->sc_iicbus == NULL) { 308 bcm_bsc_detach(dev); 309 return (ENXIO); 310 } 311 312 /* Probe and attach the iicbus when interrupts are available. */ 313 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); 314 315 return (0); 316 } 317 318 static int 319 bcm_bsc_detach(device_t dev) 320 { 321 struct bcm_bsc_softc *sc; 322 323 bus_generic_detach(dev); 324 325 sc = device_get_softc(dev); 326 mtx_destroy(&sc->sc_mtx); 327 if (sc->sc_intrhand) 328 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 329 if (sc->sc_irq_res) 330 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 331 if (sc->sc_mem_res) 332 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 333 334 return (0); 335 } 336 337 static void 338 bcm_bsc_intr(void *arg) 339 { 340 struct bcm_bsc_softc *sc; 341 uint32_t status; 342 343 sc = (struct bcm_bsc_softc *)arg; 344 345 BCM_BSC_LOCK(sc); 346 347 /* The I2C interrupt is shared among all the BSC controllers. */ 348 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { 349 BCM_BSC_UNLOCK(sc); 350 return; 351 } 352 353 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 354 355 /* Check for errors. */ 356 if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) { 357 /* Disable interrupts. */ 358 bcm_bsc_reset(sc); 359 sc->sc_flags |= BCM_I2C_ERROR; 360 wakeup(sc->sc_dev); 361 BCM_BSC_UNLOCK(sc); 362 return; 363 } 364 365 if (sc->sc_flags & BCM_I2C_READ) { 366 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) { 367 *sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA); 368 sc->sc_resid--; 369 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 370 } 371 } else { 372 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) { 373 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++); 374 sc->sc_resid--; 375 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 376 } 377 } 378 379 if (status & BCM_BSC_STATUS_DONE) { 380 /* Disable interrupts. */ 381 bcm_bsc_reset(sc); 382 wakeup(sc->sc_dev); 383 } 384 385 BCM_BSC_UNLOCK(sc); 386 } 387 388 static int 389 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 390 { 391 struct bcm_bsc_softc *sc; 392 uint32_t intr, read, status; 393 int i, err; 394 395 sc = device_get_softc(dev); 396 BCM_BSC_LOCK(sc); 397 398 /* If the controller is busy wait until it is available. */ 399 while (sc->sc_flags & BCM_I2C_BUSY) 400 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0); 401 402 /* Now we have control over the BSC controller. */ 403 sc->sc_flags = BCM_I2C_BUSY; 404 405 /* Clear the FIFO and the pending interrupts. */ 406 bcm_bsc_reset(sc); 407 408 err = 0; 409 for (i = 0; i < nmsgs; i++) { 410 411 /* Write the slave address. */ 412 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, msgs[i].slave >> 1); 413 414 /* Write the data length. */ 415 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len); 416 417 sc->sc_data = msgs[i].buf; 418 sc->sc_resid = msgs[i].len; 419 if ((msgs[i].flags & IIC_M_RD) == 0) { 420 /* Fill up the TX FIFO. */ 421 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 422 while (sc->sc_resid > 0 && 423 (status & BCM_BSC_STATUS_TXD)) { 424 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); 425 sc->sc_data++; 426 sc->sc_resid--; 427 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 428 } 429 read = 0; 430 intr = BCM_BSC_CTRL_INTT; 431 sc->sc_flags &= ~BCM_I2C_READ; 432 } else { 433 sc->sc_flags |= BCM_I2C_READ; 434 read = BCM_BSC_CTRL_READ; 435 intr = BCM_BSC_CTRL_INTR; 436 } 437 intr |= BCM_BSC_CTRL_INTD; 438 439 /* Start the transfer. */ 440 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | 441 BCM_BSC_CTRL_ST | read | intr); 442 443 /* Wait for the transaction to complete. */ 444 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bsciow", hz); 445 446 /* Check for errors. */ 447 if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR)) 448 err = EIO; 449 if (err != 0) 450 break; 451 } 452 453 /* Clean the controller flags. */ 454 sc->sc_flags = 0; 455 456 /* Wake up the threads waiting for bus. */ 457 wakeup(dev); 458 459 BCM_BSC_UNLOCK(sc); 460 461 return (err); 462 } 463 464 static int 465 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 466 { 467 struct bcm_bsc_softc *sc; 468 uint32_t busfreq; 469 470 sc = device_get_softc(dev); 471 BCM_BSC_LOCK(sc); 472 bcm_bsc_reset(sc); 473 if (sc->sc_iicbus == NULL) 474 busfreq = 100000; 475 else 476 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 477 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq); 478 BCM_BSC_UNLOCK(sc); 479 480 return (IIC_ENOADDR); 481 } 482 483 static phandle_t 484 bcm_bsc_get_node(device_t bus, device_t dev) 485 { 486 487 /* We only have one child, the I2C bus, which needs our own node. */ 488 return (ofw_bus_get_node(bus)); 489 } 490 491 static device_method_t bcm_bsc_methods[] = { 492 /* Device interface */ 493 DEVMETHOD(device_probe, bcm_bsc_probe), 494 DEVMETHOD(device_attach, bcm_bsc_attach), 495 DEVMETHOD(device_detach, bcm_bsc_detach), 496 497 /* iicbus interface */ 498 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset), 499 DEVMETHOD(iicbus_callback, iicbus_null_callback), 500 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), 501 502 /* ofw_bus interface */ 503 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), 504 505 DEVMETHOD_END 506 }; 507 508 static devclass_t bcm_bsc_devclass; 509 510 static driver_t bcm_bsc_driver = { 511 "iichb", 512 bcm_bsc_methods, 513 sizeof(struct bcm_bsc_softc), 514 }; 515 516 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0); 517 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); 518