1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2001 Tsubai Masanari. 5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 6 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 7 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Driver for bcm2835 i2c-compatible two-wire bus, named 'BSC' on this SoC. 37 * 38 * This controller can only perform complete transfers, it does not provide 39 * low-level control over sending start/repeat-start/stop sequences on the bus. 40 * In addition, bugs in the silicon make it somewhat difficult to perform a 41 * repeat-start, and limit the repeat-start to a read following a write on 42 * the same slave device. (The i2c protocol allows a repeat start to change 43 * direction or not, and change slave address or not at any time.) 44 * 45 * The repeat-start bug and workaround are described in a problem report at 46 * https://github.com/raspberrypi/linux/issues/254 with the crucial part being 47 * in a comment block from a fragment of a GPU i2c driver, containing this: 48 * 49 * ----------------------------------------------------------------------------- 50 * - See i2c.v: The I2C peripheral samples the values for rw_bit and xfer_count 51 * - in the IDLE state if start is set. 52 * - 53 * - We want to generate a ReSTART not a STOP at the end of the TX phase. In 54 * - order to do that we must ensure the state machine goes RACK1 -> RACK2 -> 55 * - SRSTRT1 (not RACK1 -> RACK2 -> SSTOP1). 56 * - 57 * - So, in the RACK2 state when (TX) xfer_count==0 we must therefore have 58 * - already set, ready to be sampled: 59 * - READ ; rw_bit <= I2CC bit 0 -- must be "read" 60 * - ST; start <= I2CC bit 7 -- must be "Go" in order to not issue STOP 61 * - DLEN; xfer_count <= I2CDLEN -- must be equal to our read amount 62 * - 63 * - The plan to do this is: 64 * - 1. Start the sub-address write, but don't let it finish 65 * - (keep xfer_count > 0) 66 * - 2. Populate READ, DLEN and ST in preparation for ReSTART read sequence 67 * - 3. Let TX finish (write the rest of the data) 68 * - 4. Read back data as it arrives 69 * ----------------------------------------------------------------------------- 70 * 71 * The transfer function below scans the list of messages passed to it, looking 72 * for a read following a write to the same slave. When it finds that, it 73 * starts the write without prefilling the tx fifo, which holds xfer_count>0, 74 * then presets the direction, length, and start command for the following read, 75 * as described above. Then the tx fifo is filled and the rest of the transfer 76 * proceeds as normal, with the controller automatically supplying a 77 * repeat-start on the bus when the write operation finishes. 78 * 79 * XXX I suspect the controller may be able to do a repeat-start on any 80 * write->read or write->write transition, even when the slave addresses differ. 81 * It's unclear whether the slave address can be prestaged along with the 82 * direction and length while the write xfer_count is being held at zero. In 83 * fact, if it can't do this, then it couldn't be used to read EDID data. 84 */ 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/kernel.h> 89 #include <sys/lock.h> 90 #include <sys/module.h> 91 #include <sys/mutex.h> 92 #include <sys/bus.h> 93 #include <machine/resource.h> 94 #include <machine/bus.h> 95 #include <sys/rman.h> 96 #include <sys/sysctl.h> 97 98 #include <dev/iicbus/iicbus.h> 99 #include <dev/iicbus/iiconf.h> 100 #include <dev/ofw/ofw_bus.h> 101 #include <dev/ofw/ofw_bus_subr.h> 102 103 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h> 104 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h> 105 106 #include "iicbus_if.h" 107 108 static struct ofw_compat_data compat_data[] = { 109 {"broadcom,bcm2835-bsc", 1}, 110 {"brcm,bcm2708-i2c", 1}, 111 {"brcm,bcm2835-i2c", 1}, 112 {NULL, 0} 113 }; 114 115 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 116 if ((lvl) <= (sc)->sc_debug) \ 117 device_printf((sc)->sc_dev, fmt, ##args) 118 119 #define DEBUGF(sc, lvl, fmt, args...) \ 120 if ((lvl) <= (sc)->sc_debug) \ 121 printf(fmt, ##args) 122 123 static void bcm_bsc_intr(void *); 124 static int bcm_bsc_detach(device_t); 125 126 static void 127 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, 128 uint32_t value) 129 { 130 uint32_t reg; 131 132 mtx_assert(&sc->sc_mtx, MA_OWNED); 133 reg = BCM_BSC_READ(sc, off); 134 reg &= ~mask; 135 reg |= value; 136 BCM_BSC_WRITE(sc, off, reg); 137 } 138 139 static int 140 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) 141 { 142 struct bcm_bsc_softc *sc; 143 uint32_t clk; 144 145 sc = (struct bcm_bsc_softc *)arg1; 146 BCM_BSC_LOCK(sc); 147 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 148 BCM_BSC_UNLOCK(sc); 149 clk &= 0xffff; 150 if (clk == 0) 151 clk = 32768; 152 clk = BCM_BSC_CORE_CLK / clk; 153 154 return (sysctl_handle_int(oidp, &clk, 0, req)); 155 } 156 157 static int 158 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) 159 { 160 struct bcm_bsc_softc *sc; 161 uint32_t clkt; 162 int error; 163 164 sc = (struct bcm_bsc_softc *)arg1; 165 166 BCM_BSC_LOCK(sc); 167 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); 168 BCM_BSC_UNLOCK(sc); 169 clkt &= 0xffff; 170 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); 171 if (error != 0 || req->newptr == NULL) 172 return (error); 173 174 BCM_BSC_LOCK(sc); 175 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); 176 BCM_BSC_UNLOCK(sc); 177 178 return (0); 179 } 180 181 static int 182 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) 183 { 184 struct bcm_bsc_softc *sc; 185 uint32_t clk, reg; 186 int error; 187 188 sc = (struct bcm_bsc_softc *)arg1; 189 190 BCM_BSC_LOCK(sc); 191 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 192 BCM_BSC_UNLOCK(sc); 193 reg >>= 16; 194 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 195 if (error != 0 || req->newptr == NULL) 196 return (error); 197 198 BCM_BSC_LOCK(sc); 199 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 200 clk = BCM_BSC_CORE_CLK / clk; 201 if (reg > clk / 2) 202 reg = clk / 2 - 1; 203 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); 204 BCM_BSC_UNLOCK(sc); 205 206 return (0); 207 } 208 209 static int 210 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) 211 { 212 struct bcm_bsc_softc *sc; 213 uint32_t clk, reg; 214 int error; 215 216 sc = (struct bcm_bsc_softc *)arg1; 217 218 BCM_BSC_LOCK(sc); 219 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 220 BCM_BSC_UNLOCK(sc); 221 reg &= 0xffff; 222 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 223 if (error != 0 || req->newptr == NULL) 224 return (error); 225 226 BCM_BSC_LOCK(sc); 227 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 228 clk = BCM_BSC_CORE_CLK / clk; 229 if (reg > clk / 2) 230 reg = clk / 2 - 1; 231 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); 232 BCM_BSC_UNLOCK(sc); 233 234 return (0); 235 } 236 237 static void 238 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) 239 { 240 struct sysctl_ctx_list *ctx; 241 struct sysctl_oid *tree_node; 242 struct sysctl_oid_list *tree; 243 244 /* 245 * Add system sysctl tree/handlers. 246 */ 247 ctx = device_get_sysctl_ctx(sc->sc_dev); 248 tree_node = device_get_sysctl_tree(sc->sc_dev); 249 tree = SYSCTL_CHILDREN(tree_node); 250 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency", 251 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 252 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); 253 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", 254 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 255 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); 256 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", 257 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 258 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); 259 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", 260 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 261 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); 262 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "debug", 263 CTLFLAG_RWTUN, &sc->sc_debug, 0, 264 "Enable debug; 1=reads/writes, 2=add starts/stops"); 265 } 266 267 static void 268 bcm_bsc_reset(struct bcm_bsc_softc *sc) 269 { 270 271 /* Enable the BSC Controller, disable interrupts. */ 272 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 273 /* Clear pending interrupts. */ 274 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | 275 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); 276 /* Clear the FIFO. */ 277 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, 278 BCM_BSC_CTRL_CLEAR0); 279 } 280 281 static int 282 bcm_bsc_probe(device_t dev) 283 { 284 285 if (!ofw_bus_status_okay(dev)) 286 return (ENXIO); 287 288 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 289 return (ENXIO); 290 291 device_set_desc(dev, "BCM2708/2835 BSC controller"); 292 293 return (BUS_PROBE_DEFAULT); 294 } 295 296 static int 297 bcm_bsc_attach(device_t dev) 298 { 299 struct bcm_bsc_softc *sc; 300 int rid; 301 302 sc = device_get_softc(dev); 303 sc->sc_dev = dev; 304 305 rid = 0; 306 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 307 RF_ACTIVE); 308 if (!sc->sc_mem_res) { 309 device_printf(dev, "cannot allocate memory window\n"); 310 return (ENXIO); 311 } 312 313 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 314 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 315 316 rid = 0; 317 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 318 RF_ACTIVE | RF_SHAREABLE); 319 if (!sc->sc_irq_res) { 320 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 321 device_printf(dev, "cannot allocate interrupt\n"); 322 return (ENXIO); 323 } 324 325 /* Hook up our interrupt handler. */ 326 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 327 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { 328 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 329 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 330 device_printf(dev, "cannot setup the interrupt handler\n"); 331 return (ENXIO); 332 } 333 334 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); 335 336 bcm_bsc_sysctl_init(sc); 337 338 /* Enable the BSC controller. Flush the FIFO. */ 339 BCM_BSC_LOCK(sc); 340 bcm_bsc_reset(sc); 341 BCM_BSC_UNLOCK(sc); 342 343 sc->sc_iicbus = device_add_child(dev, "iicbus", -1); 344 if (sc->sc_iicbus == NULL) { 345 bcm_bsc_detach(dev); 346 return (ENXIO); 347 } 348 349 /* Probe and attach the iicbus when interrupts are available. */ 350 return (bus_delayed_attach_children(dev)); 351 } 352 353 static int 354 bcm_bsc_detach(device_t dev) 355 { 356 struct bcm_bsc_softc *sc; 357 358 bus_generic_detach(dev); 359 360 sc = device_get_softc(dev); 361 if (sc->sc_iicbus != NULL) 362 device_delete_child(dev, sc->sc_iicbus); 363 mtx_destroy(&sc->sc_mtx); 364 if (sc->sc_intrhand) 365 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 366 if (sc->sc_irq_res) 367 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 368 if (sc->sc_mem_res) 369 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 370 371 return (0); 372 } 373 374 static void 375 bcm_bsc_empty_rx_fifo(struct bcm_bsc_softc *sc) 376 { 377 uint32_t status; 378 379 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_RXD is asserted on entry. */ 380 do { 381 if (sc->sc_resid == 0) { 382 sc->sc_data = sc->sc_curmsg->buf; 383 sc->sc_dlen = sc->sc_curmsg->len; 384 sc->sc_resid = sc->sc_dlen; 385 ++sc->sc_curmsg; 386 } 387 do { 388 *sc->sc_data = BCM_BSC_READ(sc, BCM_BSC_DATA); 389 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); 390 ++sc->sc_data; 391 --sc->sc_resid; 392 --sc->sc_totlen; 393 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 394 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)); 395 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_RXD)); 396 } 397 398 static void 399 bcm_bsc_fill_tx_fifo(struct bcm_bsc_softc *sc) 400 { 401 uint32_t status; 402 403 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_TXD is asserted on entry. */ 404 do { 405 if (sc->sc_resid == 0) { 406 sc->sc_data = sc->sc_curmsg->buf; 407 sc->sc_dlen = sc->sc_curmsg->len; 408 sc->sc_resid = sc->sc_dlen; 409 ++sc->sc_curmsg; 410 } 411 do { 412 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); 413 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); 414 ++sc->sc_data; 415 --sc->sc_resid; 416 --sc->sc_totlen; 417 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 418 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)); 419 /* 420 * If a repeat-start was pending and we just hit the end of a tx 421 * buffer, see if it's also the end of the writes that preceeded 422 * the repeat-start. If so, log the repeat-start and the start 423 * of the following read, and return because we're not writing 424 * anymore (and TXD will be true because there's room to write 425 * in the fifo). 426 */ 427 if (sc->sc_replen > 0 && sc->sc_resid == 0) { 428 sc->sc_replen -= sc->sc_dlen; 429 if (sc->sc_replen == 0) { 430 DEBUGF(sc, 1, " err=0\n"); 431 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", 432 sc->sc_curmsg->slave | 0x01); 433 DEVICE_DEBUGF(sc, 1, 434 "read 0x%02x len %d: ", 435 sc->sc_curmsg->slave | 0x01, 436 sc->sc_totlen); 437 sc->sc_flags |= BCM_I2C_READ; 438 return; 439 } 440 } 441 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_TXD)); 442 } 443 444 static void 445 bcm_bsc_intr(void *arg) 446 { 447 struct bcm_bsc_softc *sc; 448 uint32_t status; 449 450 sc = (struct bcm_bsc_softc *)arg; 451 452 BCM_BSC_LOCK(sc); 453 454 /* The I2C interrupt is shared among all the BSC controllers. */ 455 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { 456 BCM_BSC_UNLOCK(sc); 457 return; 458 } 459 460 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 461 DEBUGF(sc, 4, " <intrstatus=0x%08x> ", status); 462 463 /* RXD and DONE can assert together, empty fifo before checking done. */ 464 if ((sc->sc_flags & BCM_I2C_READ) && (status & BCM_BSC_STATUS_RXD)) 465 bcm_bsc_empty_rx_fifo(sc); 466 467 /* Check for completion. */ 468 if (status & (BCM_BSC_STATUS_ERRBITS | BCM_BSC_STATUS_DONE)) { 469 sc->sc_flags |= BCM_I2C_DONE; 470 if (status & BCM_BSC_STATUS_ERRBITS) 471 sc->sc_flags |= BCM_I2C_ERROR; 472 /* Disable interrupts. */ 473 bcm_bsc_reset(sc); 474 wakeup(sc); 475 } else if (!(sc->sc_flags & BCM_I2C_READ)) { 476 /* 477 * Don't check for TXD until after determining whether the 478 * transfer is complete; TXD will be asserted along with ERR or 479 * DONE if there is room in the fifo. 480 */ 481 if ((status & BCM_BSC_STATUS_TXD) && sc->sc_totlen > 0) 482 bcm_bsc_fill_tx_fifo(sc); 483 } 484 485 BCM_BSC_UNLOCK(sc); 486 } 487 488 static int 489 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 490 { 491 struct bcm_bsc_softc *sc; 492 struct iic_msg *endmsgs, *nxtmsg; 493 uint32_t readctl, status; 494 int err; 495 uint16_t curlen; 496 uint8_t curisread, curslave, nxtisread, nxtslave; 497 498 sc = device_get_softc(dev); 499 BCM_BSC_LOCK(sc); 500 501 /* If the controller is busy wait until it is available. */ 502 while (sc->sc_flags & BCM_I2C_BUSY) 503 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0); 504 505 /* Now we have control over the BSC controller. */ 506 sc->sc_flags = BCM_I2C_BUSY; 507 508 DEVICE_DEBUGF(sc, 3, "Transfer %d msgs\n", nmsgs); 509 510 /* Clear the FIFO and the pending interrupts. */ 511 bcm_bsc_reset(sc); 512 513 /* 514 * Perform all the transfers requested in the array of msgs. Note that 515 * it is bcm_bsc_empty_rx_fifo() and bcm_bsc_fill_tx_fifo() that advance 516 * sc->sc_curmsg through the array of messages, as the data from each 517 * message is fully consumed, but it is this loop that notices when we 518 * have no more messages to process. 519 */ 520 err = 0; 521 sc->sc_resid = 0; 522 sc->sc_curmsg = msgs; 523 endmsgs = &msgs[nmsgs]; 524 while (sc->sc_curmsg < endmsgs) { 525 readctl = 0; 526 curslave = sc->sc_curmsg->slave >> 1; 527 curisread = sc->sc_curmsg->flags & IIC_M_RD; 528 sc->sc_replen = 0; 529 sc->sc_totlen = sc->sc_curmsg->len; 530 /* 531 * Scan for scatter/gather IO (same slave and direction) or 532 * repeat-start (read following write for the same slave). 533 */ 534 for (nxtmsg = sc->sc_curmsg + 1; nxtmsg < endmsgs; ++nxtmsg) { 535 nxtslave = nxtmsg->slave >> 1; 536 if (curslave == nxtslave) { 537 nxtisread = nxtmsg->flags & IIC_M_RD; 538 if (curisread == nxtisread) { 539 /* 540 * Same slave and direction, this 541 * message will be part of the same 542 * transfer as the previous one. 543 */ 544 sc->sc_totlen += nxtmsg->len; 545 continue; 546 } else if (curisread == IIC_M_WR) { 547 /* 548 * Read after write to same slave means 549 * repeat-start, remember how many bytes 550 * come before the repeat-start, switch 551 * the direction to IIC_M_RD, and gather 552 * up following reads to the same slave. 553 */ 554 curisread = IIC_M_RD; 555 sc->sc_replen = sc->sc_totlen; 556 sc->sc_totlen += nxtmsg->len; 557 continue; 558 } 559 } 560 break; 561 } 562 563 /* 564 * curslave and curisread temporaries from above may refer to 565 * the after-repstart msg, reset them to reflect sc_curmsg. 566 */ 567 curisread = (sc->sc_curmsg->flags & IIC_M_RD) ? 1 : 0; 568 curslave = sc->sc_curmsg->slave | curisread; 569 570 /* Write the slave address. */ 571 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, curslave >> 1); 572 573 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", curslave); 574 575 /* 576 * Either set up read length and direction variables for a 577 * simple transfer or get the hardware started on the first 578 * piece of a transfer that involves a repeat-start and set up 579 * the read length and direction vars for the second piece. 580 */ 581 if (sc->sc_replen == 0) { 582 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", 583 (curisread) ? "read" : "write", curslave, 584 sc->sc_totlen); 585 curlen = sc->sc_totlen; 586 if (curisread) { 587 readctl = BCM_BSC_CTRL_READ; 588 sc->sc_flags |= BCM_I2C_READ; 589 } else { 590 readctl = 0; 591 sc->sc_flags &= ~BCM_I2C_READ; 592 } 593 } else { 594 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", 595 (curisread) ? "read" : "write", curslave, 596 sc->sc_replen); 597 598 /* 599 * Start the write transfer with an empty fifo and wait 600 * for the 'transfer active' status bit to light up; 601 * that indicates that the hardware has latched the 602 * direction and length for the write, and we can safely 603 * reload those registers and issue the start for the 604 * following read; interrupts are not enabled here. 605 */ 606 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, sc->sc_replen); 607 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | 608 BCM_BSC_CTRL_ST); 609 do { 610 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 611 if (status & BCM_BSC_STATUS_ERR) { 612 /* no ACK on slave addr */ 613 err = EIO; 614 goto xfer_done; 615 } 616 } while ((status & BCM_BSC_STATUS_TA) == 0); 617 /* 618 * Set curlen and readctl for the repeat-start read that 619 * we need to set up below, but set sc_flags to write, 620 * because that is the operation in progress right now. 621 */ 622 curlen = sc->sc_totlen - sc->sc_replen; 623 readctl = BCM_BSC_CTRL_READ; 624 sc->sc_flags &= ~BCM_I2C_READ; 625 } 626 627 /* 628 * Start the transfer with interrupts enabled, then if doing a 629 * write, fill the tx fifo. Not prefilling the fifo until after 630 * this start command is the key workaround for making 631 * repeat-start work, and it's harmless to do it in this order 632 * for a regular write too. 633 */ 634 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, curlen); 635 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, readctl | BCM_BSC_CTRL_I2CEN | 636 BCM_BSC_CTRL_ST | BCM_BSC_CTRL_INT_ALL); 637 638 if (!(sc->sc_curmsg->flags & IIC_M_RD)) { 639 bcm_bsc_fill_tx_fifo(sc); 640 } 641 642 /* Wait for the transaction to complete. */ 643 while (err == 0 && !(sc->sc_flags & BCM_I2C_DONE)) { 644 err = mtx_sleep(sc, &sc->sc_mtx, 0, "bsciow", hz); 645 } 646 /* Check for errors. */ 647 if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR)) 648 err = EIO; 649 xfer_done: 650 DEBUGF(sc, 1, " err=%d\n", err); 651 DEVICE_DEBUGF(sc, 2, "stop\n"); 652 if (err != 0) 653 break; 654 } 655 656 /* Disable interrupts, clean fifo, etc. */ 657 bcm_bsc_reset(sc); 658 659 /* Clean the controller flags. */ 660 sc->sc_flags = 0; 661 662 /* Wake up the threads waiting for bus. */ 663 wakeup(dev); 664 665 BCM_BSC_UNLOCK(sc); 666 667 return (err); 668 } 669 670 static int 671 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 672 { 673 struct bcm_bsc_softc *sc; 674 uint32_t busfreq; 675 676 sc = device_get_softc(dev); 677 BCM_BSC_LOCK(sc); 678 bcm_bsc_reset(sc); 679 if (sc->sc_iicbus == NULL) 680 busfreq = 100000; 681 else 682 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 683 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq); 684 BCM_BSC_UNLOCK(sc); 685 686 return (IIC_ENOADDR); 687 } 688 689 static phandle_t 690 bcm_bsc_get_node(device_t bus, device_t dev) 691 { 692 693 /* We only have one child, the I2C bus, which needs our own node. */ 694 return (ofw_bus_get_node(bus)); 695 } 696 697 static device_method_t bcm_bsc_methods[] = { 698 /* Device interface */ 699 DEVMETHOD(device_probe, bcm_bsc_probe), 700 DEVMETHOD(device_attach, bcm_bsc_attach), 701 DEVMETHOD(device_detach, bcm_bsc_detach), 702 703 /* iicbus interface */ 704 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset), 705 DEVMETHOD(iicbus_callback, iicbus_null_callback), 706 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), 707 708 /* ofw_bus interface */ 709 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), 710 711 DEVMETHOD_END 712 }; 713 714 static devclass_t bcm_bsc_devclass; 715 716 static driver_t bcm_bsc_driver = { 717 "iichb", 718 bcm_bsc_methods, 719 sizeof(struct bcm_bsc_softc), 720 }; 721 722 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0); 723 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); 724