1 /*- 2 * Copyright (c) 2001 Tsubai Masanari. 3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 4 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/bus.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 44 #include <dev/iicbus/iicbus.h> 45 #include <dev/iicbus/iiconf.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 50 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h> 51 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h> 52 53 #include "iicbus_if.h" 54 55 static void bcm_bsc_intr(void *); 56 57 static void 58 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, 59 uint32_t value) 60 { 61 uint32_t reg; 62 63 mtx_assert(&sc->sc_mtx, MA_OWNED); 64 reg = BCM_BSC_READ(sc, off); 65 reg &= ~mask; 66 reg |= value; 67 BCM_BSC_WRITE(sc, off, reg); 68 } 69 70 static int 71 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) 72 { 73 struct bcm_bsc_softc *sc; 74 uint32_t clk; 75 int error; 76 77 sc = (struct bcm_bsc_softc *)arg1; 78 79 BCM_BSC_LOCK(sc); 80 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 81 BCM_BSC_UNLOCK(sc); 82 clk &= 0xffff; 83 if (clk == 0) 84 clk = 32768; 85 clk = BCM_BSC_CORE_CLK / clk; 86 error = sysctl_handle_int(oidp, &clk, sizeof(clk), req); 87 if (error != 0 || req->newptr == NULL) 88 return (error); 89 90 clk = BCM_BSC_CORE_CLK / clk; 91 if (clk % 2) 92 clk--; 93 if (clk > 0xffff) 94 clk = 0xffff; 95 BCM_BSC_LOCK(sc); 96 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, clk); 97 BCM_BSC_UNLOCK(sc); 98 99 return (0); 100 } 101 102 static int 103 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) 104 { 105 struct bcm_bsc_softc *sc; 106 uint32_t clkt; 107 int error; 108 109 sc = (struct bcm_bsc_softc *)arg1; 110 111 BCM_BSC_LOCK(sc); 112 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); 113 BCM_BSC_UNLOCK(sc); 114 clkt &= 0xffff; 115 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); 116 if (error != 0 || req->newptr == NULL) 117 return (error); 118 119 BCM_BSC_LOCK(sc); 120 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); 121 BCM_BSC_UNLOCK(sc); 122 123 return (0); 124 } 125 126 static int 127 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) 128 { 129 struct bcm_bsc_softc *sc; 130 uint32_t clk, reg; 131 int error; 132 133 sc = (struct bcm_bsc_softc *)arg1; 134 135 BCM_BSC_LOCK(sc); 136 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 137 BCM_BSC_UNLOCK(sc); 138 reg >>= 16; 139 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 140 if (error != 0 || req->newptr == NULL) 141 return (error); 142 143 BCM_BSC_LOCK(sc); 144 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 145 clk = BCM_BSC_CORE_CLK / clk; 146 if (reg > clk / 2) 147 reg = clk / 2 - 1; 148 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); 149 BCM_BSC_UNLOCK(sc); 150 151 return (0); 152 } 153 154 static int 155 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) 156 { 157 struct bcm_bsc_softc *sc; 158 uint32_t clk, reg; 159 int error; 160 161 sc = (struct bcm_bsc_softc *)arg1; 162 163 BCM_BSC_LOCK(sc); 164 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 165 BCM_BSC_UNLOCK(sc); 166 reg &= 0xffff; 167 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 168 if (error != 0 || req->newptr == NULL) 169 return (error); 170 171 BCM_BSC_LOCK(sc); 172 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 173 clk = BCM_BSC_CORE_CLK / clk; 174 if (reg > clk / 2) 175 reg = clk / 2 - 1; 176 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); 177 BCM_BSC_UNLOCK(sc); 178 179 return (0); 180 } 181 182 static void 183 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) 184 { 185 struct sysctl_ctx_list *ctx; 186 struct sysctl_oid *tree_node; 187 struct sysctl_oid_list *tree; 188 189 /* 190 * Add system sysctl tree/handlers. 191 */ 192 ctx = device_get_sysctl_ctx(sc->sc_dev); 193 tree_node = device_get_sysctl_tree(sc->sc_dev); 194 tree = SYSCTL_CHILDREN(tree_node); 195 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock", 196 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 197 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); 198 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", 199 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 200 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); 201 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", 202 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 203 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); 204 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", 205 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 206 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); 207 } 208 209 static void 210 bcm_bsc_reset(struct bcm_bsc_softc *sc) 211 { 212 213 /* Enable the BSC Controller, disable interrupts. */ 214 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 215 /* Clear pending interrupts. */ 216 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | 217 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); 218 /* Clear the FIFO. */ 219 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, 220 BCM_BSC_CTRL_CLEAR0); 221 } 222 223 static int 224 bcm_bsc_probe(device_t dev) 225 { 226 227 if (!ofw_bus_status_okay(dev)) 228 return (ENXIO); 229 230 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-bsc")) 231 return (ENXIO); 232 233 device_set_desc(dev, "BCM2708/2835 BSC controller"); 234 235 return (BUS_PROBE_DEFAULT); 236 } 237 238 static int 239 bcm_bsc_attach(device_t dev) 240 { 241 struct bcm_bsc_softc *sc; 242 unsigned long start; 243 device_t gpio; 244 int i, rid; 245 246 sc = device_get_softc(dev); 247 sc->sc_dev = dev; 248 249 rid = 0; 250 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 251 RF_ACTIVE); 252 if (!sc->sc_mem_res) { 253 device_printf(dev, "cannot allocate memory window\n"); 254 return (ENXIO); 255 } 256 257 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 258 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 259 260 /* Check the unit we are attaching by its base address. */ 261 start = rman_get_start(sc->sc_mem_res); 262 for (i = 0; i < nitems(bcm_bsc_pins); i++) { 263 if (bcm_bsc_pins[i].start == start) 264 break; 265 } 266 if (i == nitems(bcm_bsc_pins)) { 267 device_printf(dev, "only bsc0 and bsc1 are supported\n"); 268 return (ENXIO); 269 } 270 271 /* 272 * Configure the GPIO pins to ALT0 function to enable BSC control 273 * over the pins. 274 */ 275 gpio = devclass_get_device(devclass_find("gpio"), 0); 276 if (!gpio) { 277 device_printf(dev, "cannot find gpio0\n"); 278 return (ENXIO); 279 } 280 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0); 281 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0); 282 283 rid = 0; 284 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 285 RF_ACTIVE | RF_SHAREABLE); 286 if (!sc->sc_irq_res) { 287 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 288 device_printf(dev, "cannot allocate interrupt\n"); 289 return (ENXIO); 290 } 291 292 /* Hook up our interrupt handler. */ 293 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 294 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { 295 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 296 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 297 device_printf(dev, "cannot setup the interrupt handler\n"); 298 return (ENXIO); 299 } 300 301 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); 302 303 bcm_bsc_sysctl_init(sc); 304 305 /* Enable the BSC controller. Flush the FIFO. */ 306 BCM_BSC_LOCK(sc); 307 bcm_bsc_reset(sc); 308 BCM_BSC_UNLOCK(sc); 309 310 device_add_child(dev, "iicbus", -1); 311 312 return (bus_generic_attach(dev)); 313 } 314 315 static int 316 bcm_bsc_detach(device_t dev) 317 { 318 struct bcm_bsc_softc *sc; 319 320 bus_generic_detach(dev); 321 322 sc = device_get_softc(dev); 323 mtx_destroy(&sc->sc_mtx); 324 if (sc->sc_intrhand) 325 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 326 if (sc->sc_irq_res) 327 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 328 if (sc->sc_mem_res) 329 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 330 331 return (0); 332 } 333 334 static void 335 bcm_bsc_intr(void *arg) 336 { 337 struct bcm_bsc_softc *sc; 338 uint32_t status; 339 340 sc = (struct bcm_bsc_softc *)arg; 341 342 BCM_BSC_LOCK(sc); 343 344 /* The I2C interrupt is shared among all the BSC controllers. */ 345 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { 346 BCM_BSC_UNLOCK(sc); 347 return; 348 } 349 350 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 351 352 /* Check for errors. */ 353 if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) { 354 /* Disable interrupts. */ 355 bcm_bsc_reset(sc); 356 sc->sc_flags |= BCM_I2C_ERROR; 357 wakeup(sc->sc_dev); 358 BCM_BSC_UNLOCK(sc); 359 return; 360 } 361 362 if (sc->sc_flags & BCM_I2C_READ) { 363 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) { 364 *sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA); 365 sc->sc_resid--; 366 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 367 } 368 } else { 369 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) { 370 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++); 371 sc->sc_resid--; 372 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 373 } 374 } 375 376 if (status & BCM_BSC_STATUS_DONE) { 377 /* Disable interrupts. */ 378 bcm_bsc_reset(sc); 379 wakeup(sc->sc_dev); 380 } 381 382 BCM_BSC_UNLOCK(sc); 383 } 384 385 static int 386 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 387 { 388 struct bcm_bsc_softc *sc; 389 uint32_t intr, read, status; 390 int i, err; 391 392 sc = device_get_softc(dev); 393 BCM_BSC_LOCK(sc); 394 395 /* If the controller is busy wait until it is available. */ 396 while (sc->sc_flags & BCM_I2C_BUSY) 397 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0); 398 399 /* Now we have control over the BSC controller. */ 400 sc->sc_flags = BCM_I2C_BUSY; 401 402 /* Clear the FIFO and the pending interrupts. */ 403 bcm_bsc_reset(sc); 404 405 err = 0; 406 for (i = 0; i < nmsgs; i++) { 407 408 /* Write the slave address. */ 409 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, msgs[i].slave >> 1); 410 411 /* Write the data length. */ 412 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len); 413 414 sc->sc_data = msgs[i].buf; 415 sc->sc_resid = msgs[i].len; 416 if ((msgs[i].flags & IIC_M_RD) == 0) { 417 /* Fill up the TX FIFO. */ 418 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 419 while (sc->sc_resid > 0 && 420 (status & BCM_BSC_STATUS_TXD)) { 421 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); 422 sc->sc_data++; 423 sc->sc_resid--; 424 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 425 } 426 read = 0; 427 intr = BCM_BSC_CTRL_INTT; 428 sc->sc_flags &= ~BCM_I2C_READ; 429 } else { 430 sc->sc_flags |= BCM_I2C_READ; 431 read = BCM_BSC_CTRL_READ; 432 intr = BCM_BSC_CTRL_INTR; 433 } 434 intr |= BCM_BSC_CTRL_INTD; 435 436 /* Start the transfer. */ 437 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | 438 BCM_BSC_CTRL_ST | read | intr); 439 440 /* Wait for the transaction to complete. */ 441 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bsciow", hz); 442 443 /* Check for errors. */ 444 if (err != 0 && (sc->sc_flags & BCM_I2C_ERROR)) 445 err = EIO; 446 if (err != 0) 447 break; 448 } 449 450 /* Clean the controller flags. */ 451 sc->sc_flags = 0; 452 453 /* Wake up the threads waiting for bus. */ 454 wakeup(dev); 455 456 BCM_BSC_UNLOCK(sc); 457 458 return (err); 459 } 460 461 static int 462 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 463 { 464 struct bcm_bsc_softc *sc; 465 uint32_t freq; 466 467 sc = device_get_softc(dev); 468 BCM_BSC_LOCK(sc); 469 bcm_bsc_reset(sc); 470 freq = 0; 471 switch (speed) { 472 case IIC_SLOW: 473 freq = BCM_BSC_SLOW; 474 break; 475 case IIC_FAST: 476 freq = BCM_BSC_FAST; 477 break; 478 case IIC_FASTEST: 479 freq = BCM_BSC_FASTEST; 480 break; 481 case IIC_UNKNOWN: 482 default: 483 /* Reuse last frequency. */ 484 break; 485 } 486 if (freq != 0) 487 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / freq); 488 BCM_BSC_UNLOCK(sc); 489 490 return (IIC_ENOADDR); 491 } 492 493 static phandle_t 494 bcm_bsc_get_node(device_t bus, device_t dev) 495 { 496 497 /* We only have one child, the I2C bus, which needs our own node. */ 498 return (ofw_bus_get_node(bus)); 499 } 500 501 static device_method_t bcm_bsc_methods[] = { 502 /* Device interface */ 503 DEVMETHOD(device_probe, bcm_bsc_probe), 504 DEVMETHOD(device_attach, bcm_bsc_attach), 505 DEVMETHOD(device_detach, bcm_bsc_detach), 506 507 /* iicbus interface */ 508 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset), 509 DEVMETHOD(iicbus_callback, iicbus_null_callback), 510 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), 511 512 /* ofw_bus interface */ 513 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), 514 515 DEVMETHOD_END 516 }; 517 518 static devclass_t bcm_bsc_devclass; 519 520 static driver_t bcm_bsc_driver = { 521 "iichb", 522 bcm_bsc_methods, 523 sizeof(struct bcm_bsc_softc), 524 }; 525 526 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0); 527 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); 528