xref: /freebsd/sys/arm/arm/sys_machdep.c (revision 7d536dc855c85c15bf45f033d108a61b1f3cecc3)
1 /*-
2  * Copyright (c) 1990 The Regents of the University of California.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the University nor the names of its contributors
14  *    may be used to endorse or promote products derived from this software
15  *    without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  *	from: @(#)sys_machdep.c	5.5 (Berkeley) 1/19/91
30  */
31 
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34 
35 #include "opt_capsicum.h"
36 
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/capsicum.h>
40 #include <sys/proc.h>
41 #include <sys/sysproto.h>
42 #include <sys/syscall.h>
43 #include <sys/sysent.h>
44 #include <vm/vm.h>
45 #include <vm/vm_extern.h>
46 
47 #include <machine/acle-compat.h>
48 #include <machine/cpu.h>
49 #include <machine/sysarch.h>
50 #include <machine/vmparam.h>
51 
52 #ifndef _SYS_SYSPROTO_H_
53 struct sysarch_args {
54 	int op;
55 	char *parms;
56 };
57 #endif
58 
59 /* Prototypes */
60 static int arm32_sync_icache (struct thread *, void *);
61 static int arm32_drain_writebuf(struct thread *, void *);
62 
63 #if __ARM_ARCH >= 6
64 static int
65 sync_icache(uintptr_t addr, size_t len)
66 {
67 	size_t size;
68 	vm_offset_t rv;
69 
70 	/*
71 	 * Align starting address to even number because value of "1"
72 	 * is used as return value for success.
73 	 */
74 	len += addr & 1;
75 	addr &= ~1;
76 
77 	/* Break whole range to pages. */
78 	do {
79 		size = PAGE_SIZE - (addr & PAGE_MASK);
80 		size = min(size, len);
81 		rv = dcache_wb_pou_checked(addr, size);
82 		if (rv == 1) /* see dcache_wb_pou_checked() */
83 			rv = icache_inv_pou_checked(addr, size);
84 		if (rv != 1) {
85 			if (!useracc((void *)addr, size, VM_PROT_READ)) {
86 				/* Invalid access */
87 				return (rv);
88 			}
89 			/* Valid but unmapped page - skip it. */
90 		}
91 		len -= size;
92 		addr += size;
93 	} while (len > 0);
94 
95 	/* Invalidate branch predictor buffer. */
96 	bpb_inv_all();
97 	return (1);
98 }
99 #endif
100 
101 static int
102 arm32_sync_icache(struct thread *td, void *args)
103 {
104 	struct arm_sync_icache_args ua;
105 	int error;
106 	ksiginfo_t ksi;
107 #if __ARM_ARCH >= 6
108 	vm_offset_t rv;
109 #endif
110 
111 	if ((error = copyin(args, &ua, sizeof(ua))) != 0)
112 		return (error);
113 
114 	if  (ua.len == 0) {
115 		td->td_retval[0] = 0;
116 		return (0);
117 	}
118 
119 	/*
120 	 * Validate arguments. Address and length are unsigned,
121 	 * so we can use wrapped overflow check.
122 	 */
123 	if (((ua.addr + ua.len) < ua.addr) ||
124 	    ((ua.addr + ua.len) > VM_MAXUSER_ADDRESS)) {
125 		ksiginfo_init_trap(&ksi);
126 		ksi.ksi_signo = SIGSEGV;
127 		ksi.ksi_code = SEGV_ACCERR;
128 		ksi.ksi_addr = (void *)max(ua.addr, VM_MAXUSER_ADDRESS);
129 		trapsignal(td, &ksi);
130 		return (EINVAL);
131 	}
132 
133 #if __ARM_ARCH >= 6
134 	rv = sync_icache(ua.addr, ua.len);
135 	if (rv != 1) {
136 		ksiginfo_init_trap(&ksi);
137 		ksi.ksi_signo = SIGSEGV;
138 		ksi.ksi_code = SEGV_MAPERR;
139 		ksi.ksi_addr = (void *)rv;
140 		trapsignal(td, &ksi);
141 		return (EINVAL);
142 	}
143 #else
144 	cpu_icache_sync_range(ua.addr, ua.len);
145 #endif
146 
147 	td->td_retval[0] = 0;
148 	return (0);
149 }
150 
151 static int
152 arm32_drain_writebuf(struct thread *td, void *args)
153 {
154 	/* No args. */
155 
156 #if __ARM_ARCH < 6
157 	cpu_drain_writebuf();
158 #else
159 	dsb();
160 	cpu_l2cache_drain_writebuf();
161 #endif
162 	td->td_retval[0] = 0;
163 	return (0);
164 }
165 
166 static int
167 arm32_set_tp(struct thread *td, void *args)
168 {
169 
170 	td->td_md.md_tp = (register_t)args;
171 #if __ARM_ARCH >= 6
172 	set_tls(args);
173 #else
174 	*(register_t *)ARM_TP_ADDRESS = (register_t)args;
175 #endif
176 	return (0);
177 }
178 
179 static int
180 arm32_get_tp(struct thread *td, void *args)
181 {
182 
183 #if __ARM_ARCH >= 6
184 	td->td_retval[0] = td->td_md.md_tp;
185 #else
186 	td->td_retval[0] = *(register_t *)ARM_TP_ADDRESS;
187 #endif
188 	return (0);
189 }
190 
191 int
192 sysarch(td, uap)
193 	struct thread *td;
194 	register struct sysarch_args *uap;
195 {
196 	int error;
197 
198 #ifdef CAPABILITY_MODE
199 	/*
200 	 * When adding new operations, add a new case statement here to
201 	 * explicitly indicate whether or not the operation is safe to
202 	 * perform in capability mode.
203 	 */
204 	if (IN_CAPABILITY_MODE(td)) {
205 		switch (uap->op) {
206 		case ARM_SYNC_ICACHE:
207 		case ARM_DRAIN_WRITEBUF:
208 		case ARM_SET_TP:
209 		case ARM_GET_TP:
210 			break;
211 
212 		default:
213 #ifdef KTRACE
214 			if (KTRPOINT(td, KTR_CAPFAIL))
215 				ktrcapfail(CAPFAIL_SYSCALL, NULL, NULL);
216 #endif
217 			return (ECAPMODE);
218 		}
219 	}
220 #endif
221 
222 	switch (uap->op) {
223 	case ARM_SYNC_ICACHE:
224 		error = arm32_sync_icache(td, uap->parms);
225 		break;
226 	case ARM_DRAIN_WRITEBUF:
227 		error = arm32_drain_writebuf(td, uap->parms);
228 		break;
229 	case ARM_SET_TP:
230 		error = arm32_set_tp(td, uap->parms);
231 		break;
232 	case ARM_GET_TP:
233 		error = arm32_get_tp(td, uap->parms);
234 		break;
235 	default:
236 		error = EINVAL;
237 		break;
238 	}
239 	return (error);
240 }
241