xref: /freebsd/sys/arm/arm/sys_machdep.c (revision 7899f917b1c0ea178f1d2be0cfb452086d079d23)
1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
3  *
4  * Copyright (c) 1990 The Regents of the University of California.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. Neither the name of the University nor the names of its contributors
16  *    may be used to endorse or promote products derived from this software
17  *    without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>
33 #include "opt_capsicum.h"
34 #include "opt_ktrace.h"
35 
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/capsicum.h>
39 #include <sys/ktrace.h>
40 #include <sys/proc.h>
41 #include <sys/sysproto.h>
42 #include <sys/syscall.h>
43 #include <sys/sysent.h>
44 #include <vm/vm.h>
45 #include <vm/vm_extern.h>
46 
47 #include <machine/cpu.h>
48 #include <machine/sysarch.h>
49 #include <machine/machdep.h>
50 #include <machine/vmparam.h>
51 
52 #ifndef _SYS_SYSPROTO_H_
53 struct sysarch_args {
54 	int op;
55 	char *parms;
56 };
57 #endif
58 
59 /* Prototypes */
60 static int arm32_sync_icache (struct thread *, void *);
61 static int arm32_drain_writebuf(struct thread *, void *);
62 
63 static int
64 sync_icache(uintptr_t addr, size_t len)
65 {
66 	size_t size;
67 	vm_offset_t rv;
68 
69 	 /* Align starting address to cacheline size */
70 	len += addr & cpuinfo.dcache_line_mask;
71 	addr &= ~cpuinfo.dcache_line_mask;
72 
73 	/* Break whole range to pages. */
74 	do {
75 		size = PAGE_SIZE - (addr & PAGE_MASK);
76 		size = min(size, len);
77 		rv = dcache_wb_pou_checked(addr, size);
78 		if (rv == 1) /* see dcache_wb_pou_checked() */
79 			rv = icache_inv_pou_checked(addr, size);
80 		if (rv != 1) {
81 			if (!useracc((void *)addr, size, VM_PROT_READ)) {
82 				/* Invalid access */
83 				return (rv);
84 			}
85 			/* Valid but unmapped page - skip it. */
86 		}
87 		len -= size;
88 		addr += size;
89 	} while (len > 0);
90 
91 	/* Invalidate branch predictor buffer. */
92 	bpb_inv_all();
93 	return (1);
94 }
95 
96 static int
97 arm32_sync_icache(struct thread *td, void *args)
98 {
99 	struct arm_sync_icache_args ua;
100 	int error;
101 	ksiginfo_t ksi;
102 	vm_offset_t rv;
103 
104 	if ((error = copyin(args, &ua, sizeof(ua))) != 0)
105 		return (error);
106 
107 	if  (ua.len == 0) {
108 		td->td_retval[0] = 0;
109 		return (0);
110 	}
111 
112 	/*
113 	 * Validate arguments. Address and length are unsigned,
114 	 * so we can use wrapped overflow check.
115 	 */
116 	if (((ua.addr + ua.len) < ua.addr) ||
117 	    ((ua.addr + ua.len) > VM_MAXUSER_ADDRESS)) {
118 		ksiginfo_init_trap(&ksi);
119 		ksi.ksi_signo = SIGSEGV;
120 		ksi.ksi_code = SEGV_ACCERR;
121 		ksi.ksi_addr = (void *)max(ua.addr, VM_MAXUSER_ADDRESS);
122 		trapsignal(td, &ksi);
123 		return (EINVAL);
124 	}
125 
126 	rv = sync_icache(ua.addr, ua.len);
127 	if (rv != 1) {
128 		ksiginfo_init_trap(&ksi);
129 		ksi.ksi_signo = SIGSEGV;
130 		ksi.ksi_code = SEGV_MAPERR;
131 		ksi.ksi_addr = (void *)rv;
132 		trapsignal(td, &ksi);
133 		return (EINVAL);
134 	}
135 
136 	td->td_retval[0] = 0;
137 	return (0);
138 }
139 
140 static int
141 arm32_drain_writebuf(struct thread *td, void *args)
142 {
143 	/* No args. */
144 
145 	dsb();
146 	cpu_l2cache_drain_writebuf();
147 	td->td_retval[0] = 0;
148 	return (0);
149 }
150 
151 static int
152 arm32_set_tp(struct thread *td, void *args)
153 {
154 
155 	set_tls(args);
156 	return (0);
157 }
158 
159 static int
160 arm32_get_tp(struct thread *td, void *args)
161 {
162 
163 	td->td_retval[0] = (register_t)get_tls();
164 	return (0);
165 }
166 
167 int
168 sysarch(struct thread *td, struct sysarch_args *uap)
169 {
170 	int error;
171 
172 #ifdef CAPABILITY_MODE
173 	/*
174 	 * When adding new operations, add a new case statement here to
175 	 * explicitly indicate whether or not the operation is safe to
176 	 * perform in capability mode.
177 	 */
178 	switch (uap->op) {
179 	case ARM_SYNC_ICACHE:
180 	case ARM_DRAIN_WRITEBUF:
181 	case ARM_SET_TP:
182 	case ARM_GET_TP:
183 	case ARM_GET_VFPSTATE:
184 		break;
185 
186 	default:
187 		if (CAP_TRACING(td))
188 			ktrcapfail(CAPFAIL_SYSCALL, &uap->op);
189 		if (IN_CAPABILITY_MODE(td))
190 			return (ECAPMODE);
191 	}
192 #endif
193 
194 	switch (uap->op) {
195 	case ARM_SYNC_ICACHE:
196 		error = arm32_sync_icache(td, uap->parms);
197 		break;
198 	case ARM_DRAIN_WRITEBUF:
199 		error = arm32_drain_writebuf(td, uap->parms);
200 		break;
201 	case ARM_SET_TP:
202 		error = arm32_set_tp(td, uap->parms);
203 		break;
204 	case ARM_GET_TP:
205 		error = arm32_get_tp(td, uap->parms);
206 		break;
207 	case ARM_GET_VFPSTATE:
208 		error = arm_get_vfpstate(td, uap->parms);
209 		break;
210 	default:
211 		error = EINVAL;
212 		break;
213 	}
214 	return (error);
215 }
216