1/* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */ 2 3/* 4 * Copyright (C) 1994-1997 Mark Brinicombe 5 * Copyright (C) 1994 Brini 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of Brini may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35#include "assym.s" 36#include <sys/syscall.h> 37#include <machine/asm.h> 38#include <machine/armreg.h> 39#include <machine/pte.h> 40__FBSDID("$FreeBSD$"); 41 42/* What size should this really be ? It is only used by init_arm() */ 43#define INIT_ARM_STACK_SIZE 2048 44 45/* 46 * This is for kvm_mkdb, and should be the address of the beginning 47 * of the kernel text segment (not necessarily the same as kernbase). 48 */ 49 50 51#define CPWAIT_BRANCH \ 52 sub pc, pc, #4 53 54#define CPWAIT(tmp) \ 55 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 56 mov tmp, tmp /* wait for it to complete */ ;\ 57 CPWAIT_BRANCH /* branch to next insn */ 58 59 .text 60 .align 0 61.globl kernbase 62.set kernbase,KERNBASE 63 64ENTRY_NP(btext) 65 66ASENTRY_NP(_start) 67 68 /* Check if we are running on RAM, if not move ourself to RAM */ 69#if 0 70 cmp pc, #PHYSADDR 71 bhi start_inram /* XXX: This is wrong */ 72#endif 73 b start_inram /* 74 * XXX: this is even more wrong, but RedBoot 75 * use 0x00000000-0x100000000 as virtual 76 * addresses for the RAM. 77 */ 78 79 /* move me to RAM 80 * XXX: we can use memcpy if it is PIC 81 */ 82 ldr r1, Lcopy_size 83 adr r0, _C_LABEL(_start) 84 add r1, r1, #3 85 mov r1, r1, LSR #2 86 mov r2, #PHYSADDR 87 add r2, r2, #0x00200000 88 mov r4, r2 89 905: ldr r3,[r0],#4 91 str r3,[r2],#4 92 subs r1,r1,#1 93 bhi 5b 94 95 /* Jump to RAM */ 96 ldr r0, Lstart_off 97 add pc, r4, r0 98 99Lcopy_size: .word _edata-_C_LABEL(_start) 100Lstart_off: .word start_inram-_C_LABEL(_start) 101start_inram: 102 adr r7, Lunmapped 103 bic r7, r7, #0xff000000 104 orr r7, r7, #PHYSADDR 105 106 /* Disable MMU for a while */ 107 mrc p15, 0, r2, c1, c0, 0 108 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 109 mcr p15, 0, r2, c1, c0, 0 110 111 nop 112 nop 113 nop 114 mov pc, r7 115Lunmapped: 116 117#ifdef STARTUP_PAGETABLE_ADDR 118 /* build page table from scratch */ 119 ldr r0, Lstartup_pagetable 120 adr r4, mmu_init_table 121 b 3f 122 1232: 124 str r3, [r0, r2] 125 add r2, r2, #4 126 add r3, r3, #(L1_S_SIZE) 127 adds r1, r1, #-1 128 bhi 2b 1293: 130 ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ 131 cmp r1, #0 132 bne 2b 133 134 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 135 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 136 137 /* Set the Domain Access register. Very important! */ 138 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 139 mcr p15, 0, r0, c3, c0, 0 140 141 /* Enable MMU */ 142 mrc p15, 0, r0, c1, c0, 0 143 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 144 mcr p15, 0, r0, c1, c0, 0 145 CPWAIT(r0) 146 147 bl mmu_done 148mmu_done: 149#endif 150 adr r1, .Lstart 151 ldmia r1, {r1, r2, sp} /* Set initial stack and */ 152 sub r2, r2, r1 /* get zero init data */ 153 mov r3, #0 154 155.L1: 156 str r3, [r1], #0x0004 /* Zero the bss */ 157 subs r2, r2, #4 158 bgt .L1 159 160 ldr fp, =KERNVIRTADDR /* trace back starts here */ 161 bl _C_LABEL(initarm) /* Off we go */ 162 163 /* init arm will return the new stack pointer. */ 164 mov sp, r0 165 166 bl _C_LABEL(mi_startup) /* call mi_startup()! */ 167 168 adr r0, .Lmainreturned 169 b _C_LABEL(panic) 170 /* NOTEACHED */ 171#ifdef STARTUP_PAGETABLE_ADDR 172#define MMU_INIT(va,pa,n_sec,attr) \ 173 .word n_sec ; \ 174 .word 4*((va)>>L1_S_SHIFT) ; \ 175 .word (pa)|(attr) ; 176 177Lstartup_pagetable: 178 .word STARTUP_PAGETABLE_ADDR 179mmu_init_table: 180 /* fill all table VA==PA */ 181 MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) 182 /* map SDRAM VA==PA, WT cacheable */ 183 MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 184 /* map VA 0xc0000000..0xc3ffffff to PA */ 185 MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 186 MMU_INIT(0xfe800000, 0xfe800000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) 187 188 .word 0 /* end of table */ 189#endif 190.Lstart: 191 .word _edata 192 .word _end 193 .word svcstk + INIT_ARM_STACK_SIZE 194 195.Lmainreturned: 196 .asciz "main() returned" 197 .align 0 198 199 .bss 200svcstk: 201 .space INIT_ARM_STACK_SIZE 202 203 .text 204 .align 0 205 206#ifndef OFW 207 /* OFW based systems will used OF_boot() */ 208 209.Lcpufuncs: 210 .word _C_LABEL(cpufuncs) 211 212ENTRY_NP(cpu_halt) 213 mrs r2, cpsr 214 bic r2, r2, #(PSR_MODE) 215 orr r2, r2, #(PSR_SVC32_MODE) 216 orr r2, r2, #(I32_bit | F32_bit) 217 msr cpsr_all, r2 218 219 ldr r4, .Lcpu_reset_address 220 ldr r4, [r4] 221 222 ldr r0, .Lcpufuncs 223 mov lr, pc 224 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] 225 226 /* 227 * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's 228 * necessary. 229 */ 230 231 ldr r1, .Lcpu_reset_needs_v4_MMU_disable 232 ldr r1, [r1] 233 cmp r1, #0 234 mov r2, #0 235 236 /* 237 * MMU & IDC off, 32 bit program & data space 238 * Hurl ourselves into the ROM 239 */ 240 mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) 241 mcr 15, 0, r0, c1, c0, 0 242 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */ 243 mov pc, r4 244 245 /* 246 * _cpu_reset_address contains the address to branch to, to complete 247 * the cpu reset after turning the MMU off 248 * This variable is provided by the hardware specific code 249 */ 250.Lcpu_reset_address: 251 .word _C_LABEL(cpu_reset_address) 252 253 /* 254 * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the 255 * v4 MMU disable instruction needs executing... it is an illegal instruction 256 * on f.e. ARM6/7 that locks up the computer in an endless illegal 257 * instruction / data-abort / reset loop. 258 */ 259.Lcpu_reset_needs_v4_MMU_disable: 260 .word _C_LABEL(cpu_reset_needs_v4_MMU_disable) 261 262#endif /* OFW */ 263 264#ifdef IPKDB 265/* 266 * Execute(inst, psr, args, sp) 267 * 268 * Execute INSTruction with PSR and ARGS[0] - ARGS[3] making 269 * available stack at SP for next undefined instruction trap. 270 * 271 * Move the instruction onto the stack and jump to it. 272 */ 273ENTRY_NP(Execute) 274 mov ip, sp 275 stmfd sp!, {r2, r4-r7, fp, ip, lr, pc} 276 sub fp, ip, #4 277 mov ip, r3 278 ldr r7, .Lreturn 279 stmfd sp!, {r0, r7} 280 adr r7, #.LExec 281 mov r5, r1 282 mrs r4, cpsr 283 ldmia r2, {r0-r3} 284 mov r6, sp 285 mov sp, ip 286 msr cpsr_all, r5 287 mov pc, r6 288.LExec: 289 mrs r5, cpsr 290/* XXX Cannot switch thus easily back from user mode */ 291 msr cpsr_all, r4 292 add sp, r6, #8 293 ldmfd sp!, {r6} 294 stmia r6, {r0-r3} 295 mov r0, r5 296 ldmdb fp, {r4-r7, fp, sp, pc} 297.Lreturn: 298 mov pc, r7 299#endif 300 301/* 302 * setjump + longjmp 303 */ 304ENTRY(setjmp) 305 stmia r0, {r4-r14} 306 mov r0, #0x00000000 307 mov pc, lr 308 309ENTRY(longjmp) 310 ldmia r0, {r4-r14} 311 mov r0, #0x00000001 312 mov pc, lr 313 314 .data 315 .global _C_LABEL(esym) 316_C_LABEL(esym): .word _C_LABEL(end) 317 318ENTRY_NP(abort) 319 b _C_LABEL(abort) 320 321ENTRY_NP(sigcode) 322 mov r0, sp 323 swi SYS_sigreturn 324 325 /* Well if that failed we better exit quick ! */ 326 327 swi SYS_exit 328 b . - 8 329 330 .align 0 331 .global _C_LABEL(esigcode) 332 _C_LABEL(esigcode): 333 334 .data 335 .global szsigcode 336szsigcode: 337 .long esigcode-sigcode 338/* End of locore.S */ 339