1/* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */ 2 3/*- 4 * Copyright (C) 1994-1997 Mark Brinicombe 5 * Copyright (C) 1994 Brini 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of Brini may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35#include "assym.s" 36#include <sys/syscall.h> 37#include <machine/asm.h> 38#include <machine/armreg.h> 39#include <machine/pte.h> 40__FBSDID("$FreeBSD$"); 41 42/* What size should this really be ? It is only used by init_arm() */ 43#define INIT_ARM_STACK_SIZE 2048 44 45/* 46 * This is for kvm_mkdb, and should be the address of the beginning 47 * of the kernel text segment (not necessarily the same as kernbase). 48 */ 49 50 51#define CPWAIT_BRANCH \ 52 sub pc, pc, #4 53 54#define CPWAIT(tmp) \ 55 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 56 mov tmp, tmp /* wait for it to complete */ ;\ 57 CPWAIT_BRANCH /* branch to next insn */ 58 59 .text 60 .align 0 61.globl kernbase 62.set kernbase,KERNBASE 63 64ENTRY_NP(btext) 65 66ASENTRY_NP(_start) 67 68 /* Check if we are running on RAM, if not move ourself to RAM */ 69#if 0 70 cmp pc, #PHYSADDR 71 bhi start_inram /* XXX: This is wrong */ 72#endif 73 b start_inram /* 74 * XXX: this is even more wrong, but RedBoot 75 * use 0x00000000-0x100000000 as virtual 76 * addresses for the RAM. 77 */ 78 79 /* move me to RAM 80 * XXX: we can use memcpy if it is PIC 81 */ 82 ldr r1, Lcopy_size 83 adr r0, _C_LABEL(_start) 84 add r1, r1, #3 85 mov r1, r1, LSR #2 86 mov r2, #PHYSADDR 87 add r2, r2, #0x00200000 88 mov r4, r2 89 905: ldr r3,[r0],#4 91 str r3,[r2],#4 92 subs r1,r1,#1 93 bhi 5b 94 95 /* Jump to RAM */ 96 ldr r0, Lstart_off 97 add pc, r4, r0 98 99Lcopy_size: .word _edata-_C_LABEL(_start) 100Lstart_off: .word start_inram-_C_LABEL(_start) 101start_inram: 102 adr r7, Lunmapped 103 bic r7, r7, #0xff000000 104 orr r7, r7, #PHYSADDR 105 106 /* Disable MMU for a while */ 107 mrc p15, 0, r2, c1, c0, 0 108 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 109 mcr p15, 0, r2, c1, c0, 0 110 111 nop 112 nop 113 nop 114 mov pc, r7 115Lunmapped: 116 117#ifdef STARTUP_PAGETABLE_ADDR 118 /* build page table from scratch */ 119 ldr r0, Lstartup_pagetable 120 adr r4, mmu_init_table 121 b 3f 122 1232: 124 str r3, [r0, r2] 125 add r2, r2, #4 126 add r3, r3, #(L1_S_SIZE) 127 adds r1, r1, #-1 128 bhi 2b 1293: 130 ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ 131 cmp r1, #0 132 bne 2b 133 134 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 135 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 136 137 /* Set the Domain Access register. Very important! */ 138 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 139 mcr p15, 0, r0, c3, c0, 0 140 141 /* Enable MMU */ 142 mrc p15, 0, r0, c1, c0, 0 143 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 144 mcr p15, 0, r0, c1, c0, 0 145 CPWAIT(r0) 146 147 bl mmu_done 148mmu_done: 149#endif 150 adr r1, .Lstart 151 ldmia r1, {r1, r2, sp} /* Set initial stack and */ 152 sub r2, r2, r1 /* get zero init data */ 153 mov r3, #0 154 155.L1: 156 str r3, [r1], #0x0004 /* Zero the bss */ 157 subs r2, r2, #4 158 bgt .L1 159 160 ldr r4, =KERNVIRTADDR 161 cmp pc, r4 162#if KERNVIRTADDR > KERNPHYSADDR 163 ldrlt r4, =KERNVIRTADDR 164 ldrlt r5, =KERNPHYSADDR 165 sublt r4, r4, r5 166 addlt pc, pc, r4 167#else 168 ldrgt r4, =KERNPHYSADDR 169 ldrgt r5, =KERNVIRTADDR 170 subgt r4, r4, r5 171 sublt pc, pc, r4 172#endif 173 ldr fp, =KERNVIRTADDR /* trace back starts here */ 174 bl _C_LABEL(initarm) /* Off we go */ 175 176 /* init arm will return the new stack pointer. */ 177 mov sp, r0 178 179 bl _C_LABEL(mi_startup) /* call mi_startup()! */ 180 181 adr r0, .Lmainreturned 182 b _C_LABEL(panic) 183 /* NOTEACHED */ 184#ifdef STARTUP_PAGETABLE_ADDR 185#define MMU_INIT(va,pa,n_sec,attr) \ 186 .word n_sec ; \ 187 .word 4*((va)>>L1_S_SHIFT) ; \ 188 .word (pa)|(attr) ; 189 190Lstartup_pagetable: 191 .word STARTUP_PAGETABLE_ADDR 192mmu_init_table: 193 /* fill all table VA==PA */ 194 MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) 195 /* map SDRAM VA==PA, WT cacheable */ 196 MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 197 /* map VA 0xc0000000..0xc3ffffff to PA */ 198 MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 199 MMU_INIT(0xfe800000, 0xfe800000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) 200 201 .word 0 /* end of table */ 202#endif 203.Lstart: 204 .word _edata 205 .word _end 206 .word svcstk + INIT_ARM_STACK_SIZE 207 208.Lmainreturned: 209 .asciz "main() returned" 210 .align 0 211 212 .bss 213svcstk: 214 .space INIT_ARM_STACK_SIZE 215 216 .text 217 .align 0 218 219#ifndef OFW 220 /* OFW based systems will used OF_boot() */ 221 222.Lcpufuncs: 223 .word _C_LABEL(cpufuncs) 224 225ENTRY_NP(cpu_halt) 226 mrs r2, cpsr 227 bic r2, r2, #(PSR_MODE) 228 orr r2, r2, #(PSR_SVC32_MODE) 229 orr r2, r2, #(I32_bit | F32_bit) 230 msr cpsr_all, r2 231 232 ldr r4, .Lcpu_reset_address 233 ldr r4, [r4] 234 235 ldr r0, .Lcpufuncs 236 mov lr, pc 237 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] 238 239 /* 240 * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's 241 * necessary. 242 */ 243 244 ldr r1, .Lcpu_reset_needs_v4_MMU_disable 245 ldr r1, [r1] 246 cmp r1, #0 247 mov r2, #0 248 249 /* 250 * MMU & IDC off, 32 bit program & data space 251 * Hurl ourselves into the ROM 252 */ 253 mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) 254 mcr 15, 0, r0, c1, c0, 0 255 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */ 256 mov pc, r4 257 258 /* 259 * _cpu_reset_address contains the address to branch to, to complete 260 * the cpu reset after turning the MMU off 261 * This variable is provided by the hardware specific code 262 */ 263.Lcpu_reset_address: 264 .word _C_LABEL(cpu_reset_address) 265 266 /* 267 * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the 268 * v4 MMU disable instruction needs executing... it is an illegal instruction 269 * on f.e. ARM6/7 that locks up the computer in an endless illegal 270 * instruction / data-abort / reset loop. 271 */ 272.Lcpu_reset_needs_v4_MMU_disable: 273 .word _C_LABEL(cpu_reset_needs_v4_MMU_disable) 274 275#endif /* OFW */ 276 277#ifdef IPKDB 278/* 279 * Execute(inst, psr, args, sp) 280 * 281 * Execute INSTruction with PSR and ARGS[0] - ARGS[3] making 282 * available stack at SP for next undefined instruction trap. 283 * 284 * Move the instruction onto the stack and jump to it. 285 */ 286ENTRY_NP(Execute) 287 mov ip, sp 288 stmfd sp!, {r2, r4-r7, fp, ip, lr, pc} 289 sub fp, ip, #4 290 mov ip, r3 291 ldr r7, .Lreturn 292 stmfd sp!, {r0, r7} 293 adr r7, #.LExec 294 mov r5, r1 295 mrs r4, cpsr 296 ldmia r2, {r0-r3} 297 mov r6, sp 298 mov sp, ip 299 msr cpsr_all, r5 300 mov pc, r6 301.LExec: 302 mrs r5, cpsr 303/* XXX Cannot switch thus easily back from user mode */ 304 msr cpsr_all, r4 305 add sp, r6, #8 306 ldmfd sp!, {r6} 307 stmia r6, {r0-r3} 308 mov r0, r5 309 ldmdb fp, {r4-r7, fp, sp, pc} 310.Lreturn: 311 mov pc, r7 312#endif 313 314/* 315 * setjump + longjmp 316 */ 317ENTRY(setjmp) 318 stmia r0, {r4-r14} 319 mov r0, #0x00000000 320 RET 321 322ENTRY(longjmp) 323 ldmia r0, {r4-r14} 324 mov r0, #0x00000001 325 RET 326 327 .data 328 .global _C_LABEL(esym) 329_C_LABEL(esym): .word _C_LABEL(end) 330 331ENTRY_NP(abort) 332 b _C_LABEL(abort) 333 334ENTRY_NP(sigcode) 335 mov r0, sp 336 swi SYS_sigreturn 337 338 /* Well if that failed we better exit quick ! */ 339 340 swi SYS_exit 341 b . - 8 342 343 .align 0 344 .global _C_LABEL(esigcode) 345 _C_LABEL(esigcode): 346 347 .data 348 .global szsigcode 349szsigcode: 350 .long esigcode-sigcode 351/* End of locore.S */ 352