1 /*- 2 * Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Alpine PCI/PCI-Express controller driver. 31 */ 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/rman.h> 40 #include <sys/intr.h> 41 42 #include <dev/ofw/openfirm.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #include <dev/pci/pci_host_generic.h> 46 #include <dev/pci/pci_host_generic_fdt.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include "pcib_if.h" 51 52 #include "contrib/alpine-hal/al_hal_unit_adapter_regs.h" 53 #include "contrib/alpine-hal/al_hal_pcie.h" 54 #include "contrib/alpine-hal/al_hal_pcie_axi_reg.h" 55 56 #define ANNAPURNA_VENDOR_ID 0x1c36 57 58 /* Forward prototypes */ 59 static int al_pcib_probe(device_t); 60 static int al_pcib_attach(device_t); 61 static void al_pcib_fixup(device_t); 62 63 static struct ofw_compat_data compat_data[] = { 64 {"annapurna-labs,al-internal-pcie", true}, 65 {"annapurna-labs,alpine-internal-pcie", true}, 66 {NULL, false} 67 }; 68 69 /* 70 * Bus interface definitions. 71 */ 72 static device_method_t al_pcib_methods[] = { 73 /* Device interface */ 74 DEVMETHOD(device_probe, al_pcib_probe), 75 DEVMETHOD(device_attach, al_pcib_attach), 76 77 DEVMETHOD_END 78 }; 79 80 DEFINE_CLASS_1(pcib, al_pcib_driver, al_pcib_methods, 81 sizeof(struct generic_pcie_fdt_softc), generic_pcie_fdt_driver); 82 83 DRIVER_MODULE(alpine_pcib, simplebus, al_pcib_driver, 0, 0); 84 DRIVER_MODULE(alpine_pcib, ofwbus, al_pcib_driver, 0, 0); 85 86 static int 87 al_pcib_probe(device_t dev) 88 { 89 90 if (!ofw_bus_status_okay(dev)) 91 return (ENXIO); 92 93 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 94 return (ENXIO); 95 96 device_set_desc(dev, 97 "Annapurna-Labs Integrated Internal PCI-E Controller"); 98 return (BUS_PROBE_DEFAULT); 99 } 100 101 static int 102 al_pcib_attach(device_t dev) 103 { 104 int rv; 105 106 rv = pci_host_generic_fdt_attach(dev); 107 108 /* Annapurna quirk: configure vendor-specific registers */ 109 if (rv == 0) 110 al_pcib_fixup(dev); 111 112 return (rv); 113 } 114 115 static void 116 al_pcib_fixup(device_t dev) 117 { 118 uint32_t val; 119 uint16_t vid; 120 uint8_t hdrtype; 121 int bus, slot, func, maxfunc; 122 123 /* Fixup is only needed on bus 0 */ 124 bus = 0; 125 for (slot = 0; slot <= PCI_SLOTMAX; slot++) { 126 maxfunc = 0; 127 for (func = 0; func <= maxfunc; func++) { 128 hdrtype = PCIB_READ_CONFIG(dev, bus, slot, func, 129 PCIR_HDRTYPE, 1); 130 131 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 132 continue; 133 134 if (func == 0 && (hdrtype & PCIM_MFDEV) != 0) 135 maxfunc = PCI_FUNCMAX; 136 137 vid = PCIB_READ_CONFIG(dev, bus, slot, func, 138 PCIR_VENDOR, 2); 139 if (vid == ANNAPURNA_VENDOR_ID) { 140 val = PCIB_READ_CONFIG(dev, bus, slot, func, 141 AL_PCI_AXI_CFG_AND_CTR_0, 4); 142 val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK; 143 PCIB_WRITE_CONFIG(dev, bus, slot, func, 144 AL_PCI_AXI_CFG_AND_CTR_0, val, 4); 145 146 val = PCIB_READ_CONFIG(dev, bus, slot, func, 147 AL_PCI_APP_CONTROL, 4); 148 val &= ~0xffff; 149 val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK; 150 PCIB_WRITE_CONFIG(dev, bus, slot, func, 151 AL_PCI_APP_CONTROL, val, 4); 152 } 153 } 154 } 155 } 156