1 /*- 2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2015 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/smp.h> 37 #include <sys/cpuset.h> 38 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 42 #include <machine/smp.h> 43 #include <machine/fdt.h> 44 #include <machine/intr.h> 45 #include <machine/cpu-v6.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_cpu.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #define AL_CPU_RESUME_WATERMARK_REG 0x00 53 #define AL_CPU_RESUME_FLAGS_REG 0x04 54 #define AL_CPU_RESUME_PCPU_RADDR_REG(cpu) (0x08 + 0x04 + 8*(cpu)) 55 #define AL_CPU_RESUME_PCPU_FLAGS(cpu) (0x08 + 8*(cpu)) 56 57 /* Per-CPU flags */ 58 #define AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME (1 << 2) 59 60 /* The expected magic number for validating the resume addresses */ 61 #define AL_CPU_RESUME_MAGIC_NUM 0xf0e1d200 62 #define AL_CPU_RESUME_MAGIC_NUM_MASK 0xffffff00 63 64 /* The expected minimal version number for validating the capabilities */ 65 #define AL_CPU_RESUME_MIN_VER 0x000000c3 66 #define AL_CPU_RESUME_MIN_VER_MASK 0x000000ff 67 68 /* Field controlling the boot-up of companion cores */ 69 #define AL_NB_INIT_CONTROL (0x8) 70 #define AL_NB_CONFIG_STATUS_PWR_CTRL(cpu) (0x2020 + (cpu)*0x100) 71 72 extern bus_addr_t al_devmap_pa; 73 extern bus_addr_t al_devmap_size; 74 75 extern void mpentry(void); 76 77 static int platform_mp_get_core_cnt(void); 78 static int alpine_get_cpu_resume_base(u_long *pbase, u_long *psize); 79 static int alpine_get_nb_base(u_long *pbase, u_long *psize); 80 static boolean_t alpine_validate_cpu(u_int, phandle_t, u_int, pcell_t *); 81 82 static boolean_t 83 alpine_validate_cpu(u_int id, phandle_t child, u_int addr_cell, pcell_t *reg) 84 { 85 return ofw_bus_node_is_compatible(child, "arm,cortex-a15"); 86 } 87 88 static int 89 platform_mp_get_core_cnt(void) 90 { 91 static int ncores = 0; 92 int nchilds; 93 uint32_t reg; 94 95 /* Calculate ncores value only once */ 96 if (ncores) 97 return (ncores); 98 99 reg = cp15_l2ctlr_get(); 100 ncores = CPUV7_L2CTLR_NPROC(reg); 101 102 nchilds = ofw_cpu_early_foreach(alpine_validate_cpu, false); 103 104 /* Limit CPUs if DTS has configured less than available */ 105 if ((nchilds > 0) && (nchilds < ncores)) { 106 printf("SMP: limiting number of active CPUs to %d out of %d\n", 107 nchilds, ncores); 108 ncores = nchilds; 109 } 110 111 return (ncores); 112 } 113 114 void 115 platform_mp_setmaxid(void) 116 { 117 118 mp_ncpus = platform_mp_get_core_cnt(); 119 mp_maxid = mp_ncpus - 1; 120 } 121 122 static int 123 alpine_get_cpu_resume_base(u_long *pbase, u_long *psize) 124 { 125 phandle_t node; 126 u_long base = 0; 127 u_long size = 0; 128 129 if (pbase == NULL || psize == NULL) 130 return (EINVAL); 131 132 if ((node = OF_finddevice("/")) == -1) 133 return (EFAULT); 134 135 if ((node = 136 ofw_bus_find_compatible(node, "annapurna-labs,al-cpu-resume")) == 0) 137 return (EFAULT); 138 139 if (fdt_regsize(node, &base, &size)) 140 return (EFAULT); 141 142 *pbase = base; 143 *psize = size; 144 145 return (0); 146 } 147 148 static int 149 alpine_get_nb_base(u_long *pbase, u_long *psize) 150 { 151 phandle_t node; 152 u_long base = 0; 153 u_long size = 0; 154 155 if (pbase == NULL || psize == NULL) 156 return (EINVAL); 157 158 if ((node = OF_finddevice("/")) == -1) 159 return (EFAULT); 160 161 if ((node = 162 ofw_bus_find_compatible(node, "annapurna-labs,al-nb-service")) == 0) 163 return (EFAULT); 164 165 if (fdt_regsize(node, &base, &size)) 166 return (EFAULT); 167 168 *pbase = base; 169 *psize = size; 170 171 return (0); 172 } 173 174 void 175 platform_mp_start_ap(void) 176 { 177 uint32_t physaddr; 178 vm_offset_t vaddr; 179 uint32_t val; 180 uint32_t start_mask; 181 u_long cpu_resume_base; 182 u_long nb_base; 183 u_long cpu_resume_size; 184 u_long nb_size; 185 bus_addr_t cpu_resume_baddr; 186 bus_addr_t nb_baddr; 187 int a; 188 189 if (alpine_get_cpu_resume_base(&cpu_resume_base, &cpu_resume_size)) 190 panic("Couldn't resolve cpu_resume_base address\n"); 191 192 if (alpine_get_nb_base(&nb_base, &nb_size)) 193 panic("Couldn't resolve_nb_base address\n"); 194 195 /* Proceed with start addresses for additional CPUs */ 196 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + cpu_resume_base, 197 cpu_resume_size, 0, &cpu_resume_baddr)) 198 panic("Couldn't map CPU-resume area"); 199 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base, 200 nb_size, 0, &nb_baddr)) 201 panic("Couldn't map NB-service area"); 202 203 /* Proceed with start addresses for additional CPUs */ 204 val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr, 205 AL_CPU_RESUME_WATERMARK_REG); 206 if (((val & AL_CPU_RESUME_MAGIC_NUM_MASK) != AL_CPU_RESUME_MAGIC_NUM) || 207 ((val & AL_CPU_RESUME_MIN_VER_MASK) < AL_CPU_RESUME_MIN_VER)) { 208 panic("CPU-resume device is not compatible"); 209 } 210 211 vaddr = (vm_offset_t)mpentry; 212 physaddr = pmap_kextract(vaddr); 213 214 for (a = 1; a < platform_mp_get_core_cnt(); a++) { 215 /* Power up the core */ 216 bus_space_write_4(fdtbus_bs_tag, nb_baddr, 217 AL_NB_CONFIG_STATUS_PWR_CTRL(a), 0); 218 mb(); 219 220 /* Enable resume */ 221 val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr, 222 AL_CPU_RESUME_PCPU_FLAGS(a)); 223 val &= ~AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME; 224 bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr, 225 AL_CPU_RESUME_PCPU_FLAGS(a), val); 226 mb(); 227 228 /* Set resume physical address */ 229 bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr, 230 AL_CPU_RESUME_PCPU_RADDR_REG(a), physaddr); 231 mb(); 232 } 233 234 /* Release cores from reset */ 235 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base, 236 nb_size, 0, &nb_baddr)) 237 panic("Couldn't map NB-service area"); 238 239 start_mask = (1 << platform_mp_get_core_cnt()) - 1; 240 241 /* Release cores from reset */ 242 val = bus_space_read_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL); 243 val |= start_mask; 244 bus_space_write_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL, val); 245 dsb(); 246 247 bus_space_unmap(fdtbus_bs_tag, nb_baddr, nb_size); 248 bus_space_unmap(fdtbus_bs_tag, cpu_resume_baddr, cpu_resume_size); 249 } 250