1 /*- 2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2015 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/smp.h> 36 #include <sys/cpuset.h> 37 38 #include <vm/vm.h> 39 #include <vm/pmap.h> 40 41 #include <machine/smp.h> 42 #include <machine/fdt.h> 43 #include <machine/intr.h> 44 #include <machine/cpu.h> 45 #include <machine/platformvar.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_cpu.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <arm/annapurna/alpine/alpine_mp.h> 53 54 #define AL_CPU_RESUME_WATERMARK_REG 0x00 55 #define AL_CPU_RESUME_FLAGS_REG 0x04 56 #define AL_CPU_RESUME_PCPU_RADDR_REG(cpu) (0x08 + 0x04 + 8*(cpu)) 57 #define AL_CPU_RESUME_PCPU_FLAGS(cpu) (0x08 + 8*(cpu)) 58 59 /* Per-CPU flags */ 60 #define AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME (1 << 2) 61 62 /* The expected magic number for validating the resume addresses */ 63 #define AL_CPU_RESUME_MAGIC_NUM 0xf0e1d200 64 #define AL_CPU_RESUME_MAGIC_NUM_MASK 0xffffff00 65 66 /* The expected minimal version number for validating the capabilities */ 67 #define AL_CPU_RESUME_MIN_VER 0x000000c3 68 #define AL_CPU_RESUME_MIN_VER_MASK 0x000000ff 69 70 /* Field controlling the boot-up of companion cores */ 71 #define AL_NB_INIT_CONTROL (0x8) 72 #define AL_NB_CONFIG_STATUS_PWR_CTRL(cpu) (0x2020 + (cpu)*0x100) 73 74 extern bus_addr_t al_devmap_pa; 75 extern bus_addr_t al_devmap_size; 76 77 extern void mpentry(void); 78 79 static int platform_mp_get_core_cnt(void); 80 static int alpine_get_cpu_resume_base(u_long *pbase, u_long *psize); 81 static int alpine_get_nb_base(u_long *pbase, u_long *psize); 82 static bool alpine_validate_cpu(u_int, phandle_t, u_int, pcell_t *); 83 84 static bool 85 alpine_validate_cpu(u_int id, phandle_t child, u_int addr_cell, pcell_t *reg) 86 { 87 return ofw_bus_node_is_compatible(child, "arm,cortex-a15"); 88 } 89 90 static int 91 platform_mp_get_core_cnt(void) 92 { 93 static int ncores = 0; 94 int nchilds; 95 uint32_t reg; 96 97 /* Calculate ncores value only once */ 98 if (ncores) 99 return (ncores); 100 101 reg = cp15_l2ctlr_get(); 102 ncores = CPUV7_L2CTLR_NPROC(reg); 103 104 nchilds = ofw_cpu_early_foreach(alpine_validate_cpu, false); 105 106 /* Limit CPUs if DTS has configured less than available */ 107 if ((nchilds > 0) && (nchilds < ncores)) { 108 printf("SMP: limiting number of active CPUs to %d out of %d\n", 109 nchilds, ncores); 110 ncores = nchilds; 111 } 112 113 return (ncores); 114 } 115 116 void 117 alpine_mp_setmaxid(platform_t plat) 118 { 119 120 mp_ncpus = platform_mp_get_core_cnt(); 121 mp_maxid = mp_ncpus - 1; 122 } 123 124 static int 125 alpine_get_cpu_resume_base(u_long *pbase, u_long *psize) 126 { 127 phandle_t node; 128 u_long base = 0; 129 u_long size = 0; 130 131 if (pbase == NULL || psize == NULL) 132 return (EINVAL); 133 134 if ((node = OF_finddevice("/")) == -1) 135 return (EFAULT); 136 137 if ((node = 138 ofw_bus_find_compatible(node, "annapurna-labs,al-cpu-resume")) == 0) 139 return (EFAULT); 140 141 if (fdt_regsize(node, &base, &size)) 142 return (EFAULT); 143 144 *pbase = base; 145 *psize = size; 146 147 return (0); 148 } 149 150 static int 151 alpine_get_nb_base(u_long *pbase, u_long *psize) 152 { 153 phandle_t node; 154 u_long base = 0; 155 u_long size = 0; 156 157 if (pbase == NULL || psize == NULL) 158 return (EINVAL); 159 160 if ((node = OF_finddevice("/")) == -1) 161 return (EFAULT); 162 163 if ((node = 164 ofw_bus_find_compatible(node, "annapurna-labs,al-nb-service")) == 0) 165 return (EFAULT); 166 167 if (fdt_regsize(node, &base, &size)) 168 return (EFAULT); 169 170 *pbase = base; 171 *psize = size; 172 173 return (0); 174 } 175 176 void 177 alpine_mp_start_ap(platform_t plat) 178 { 179 uint32_t physaddr; 180 vm_offset_t vaddr; 181 uint32_t val; 182 uint32_t start_mask; 183 u_long cpu_resume_base; 184 u_long nb_base; 185 u_long cpu_resume_size; 186 u_long nb_size; 187 bus_addr_t cpu_resume_baddr; 188 bus_addr_t nb_baddr; 189 int a; 190 191 if (alpine_get_cpu_resume_base(&cpu_resume_base, &cpu_resume_size)) 192 panic("Couldn't resolve cpu_resume_base address\n"); 193 194 if (alpine_get_nb_base(&nb_base, &nb_size)) 195 panic("Couldn't resolve_nb_base address\n"); 196 197 /* Proceed with start addresses for additional CPUs */ 198 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + cpu_resume_base, 199 cpu_resume_size, 0, &cpu_resume_baddr)) 200 panic("Couldn't map CPU-resume area"); 201 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base, 202 nb_size, 0, &nb_baddr)) 203 panic("Couldn't map NB-service area"); 204 205 /* Proceed with start addresses for additional CPUs */ 206 val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr, 207 AL_CPU_RESUME_WATERMARK_REG); 208 if (((val & AL_CPU_RESUME_MAGIC_NUM_MASK) != AL_CPU_RESUME_MAGIC_NUM) || 209 ((val & AL_CPU_RESUME_MIN_VER_MASK) < AL_CPU_RESUME_MIN_VER)) { 210 panic("CPU-resume device is not compatible"); 211 } 212 213 vaddr = (vm_offset_t)mpentry; 214 physaddr = pmap_kextract(vaddr); 215 216 for (a = 1; a < platform_mp_get_core_cnt(); a++) { 217 /* Power up the core */ 218 bus_space_write_4(fdtbus_bs_tag, nb_baddr, 219 AL_NB_CONFIG_STATUS_PWR_CTRL(a), 0); 220 mb(); 221 222 /* Enable resume */ 223 val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr, 224 AL_CPU_RESUME_PCPU_FLAGS(a)); 225 val &= ~AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME; 226 bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr, 227 AL_CPU_RESUME_PCPU_FLAGS(a), val); 228 mb(); 229 230 /* Set resume physical address */ 231 bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr, 232 AL_CPU_RESUME_PCPU_RADDR_REG(a), physaddr); 233 mb(); 234 } 235 236 /* Release cores from reset */ 237 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base, 238 nb_size, 0, &nb_baddr)) 239 panic("Couldn't map NB-service area"); 240 241 start_mask = (1 << platform_mp_get_core_cnt()) - 1; 242 243 /* Release cores from reset */ 244 val = bus_space_read_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL); 245 val |= start_mask; 246 bus_space_write_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL, val); 247 dsb(); 248 249 bus_space_unmap(fdtbus_bs_tag, nb_baddr, nb_size); 250 bus_space_unmap(fdtbus_bs_tag, cpu_resume_baddr, cpu_resume_size); 251 } 252