1 /*- 2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2015 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/smp.h> 37 #include <sys/cpuset.h> 38 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 42 #include <machine/smp.h> 43 #include <machine/fdt.h> 44 #include <machine/intr.h> 45 #include <machine/cpu-v6.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/ofw_cpu.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #define AL_CPU_RESUME_WATERMARK_REG 0x00 52 #define AL_CPU_RESUME_FLAGS_REG 0x04 53 #define AL_CPU_RESUME_PCPU_RADDR_REG(cpu) (0x08 + 0x04 + 8*(cpu)) 54 #define AL_CPU_RESUME_PCPU_FLAGS(cpu) (0x08 + 8*(cpu)) 55 56 /* Per-CPU flags */ 57 #define AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME (1 << 2) 58 59 /* The expected magic number for validating the resume addresses */ 60 #define AL_CPU_RESUME_MAGIC_NUM 0xf0e1d200 61 #define AL_CPU_RESUME_MAGIC_NUM_MASK 0xffffff00 62 63 /* The expected minimal version number for validating the capabilities */ 64 #define AL_CPU_RESUME_MIN_VER 0x000000c3 65 #define AL_CPU_RESUME_MIN_VER_MASK 0x000000ff 66 67 /* Field controlling the boot-up of companion cores */ 68 #define AL_NB_INIT_CONTROL (0x8) 69 #define AL_NB_CONFIG_STATUS_PWR_CTRL(cpu) (0x2020 + (cpu)*0x100) 70 71 extern bus_addr_t al_devmap_pa; 72 extern bus_addr_t al_devmap_size; 73 74 extern void mpentry(void); 75 76 static int platform_mp_get_core_cnt(void); 77 static int alpine_get_cpu_resume_base(u_long *pbase, u_long *psize); 78 static int alpine_get_nb_base(u_long *pbase, u_long *psize); 79 static boolean_t alpine_validate_cpu(u_int, phandle_t, u_int, pcell_t *); 80 81 static boolean_t 82 alpine_validate_cpu(u_int id, phandle_t child, u_int addr_cell, pcell_t *reg) 83 { 84 return fdt_is_compatible(child, "arm,cortex-a15"); 85 } 86 87 static int 88 platform_mp_get_core_cnt(void) 89 { 90 static int ncores = 0; 91 int nchilds; 92 uint32_t reg; 93 94 /* Calculate ncores value only once */ 95 if (ncores) 96 return (ncores); 97 98 reg = cp15_l2ctlr_get(); 99 ncores = CPUV7_L2CTLR_NPROC(reg); 100 101 nchilds = ofw_cpu_early_foreach(alpine_validate_cpu, false); 102 103 /* Limit CPUs if DTS has configured less than available */ 104 if ((nchilds > 0) && (nchilds < ncores)) { 105 printf("SMP: limiting number of active CPUs to %d out of %d\n", 106 nchilds, ncores); 107 ncores = nchilds; 108 } 109 110 return (ncores); 111 } 112 113 void 114 platform_mp_setmaxid(void) 115 { 116 117 mp_ncpus = platform_mp_get_core_cnt(); 118 mp_maxid = mp_ncpus - 1; 119 } 120 121 static int 122 alpine_get_cpu_resume_base(u_long *pbase, u_long *psize) 123 { 124 phandle_t node; 125 u_long base = 0; 126 u_long size = 0; 127 128 if (pbase == NULL || psize == NULL) 129 return (EINVAL); 130 131 if ((node = OF_finddevice("/")) == -1) 132 return (EFAULT); 133 134 if ((node = 135 ofw_bus_find_compatible(node, "annapurna-labs,al-cpu-resume")) == 0) 136 return (EFAULT); 137 138 if (fdt_regsize(node, &base, &size)) 139 return (EFAULT); 140 141 *pbase = base; 142 *psize = size; 143 144 return (0); 145 } 146 147 static int 148 alpine_get_nb_base(u_long *pbase, u_long *psize) 149 { 150 phandle_t node; 151 u_long base = 0; 152 u_long size = 0; 153 154 if (pbase == NULL || psize == NULL) 155 return (EINVAL); 156 157 if ((node = OF_finddevice("/")) == -1) 158 return (EFAULT); 159 160 if ((node = 161 ofw_bus_find_compatible(node, "annapurna-labs,al-nb-service")) == 0) 162 return (EFAULT); 163 164 if (fdt_regsize(node, &base, &size)) 165 return (EFAULT); 166 167 *pbase = base; 168 *psize = size; 169 170 return (0); 171 } 172 173 void 174 platform_mp_start_ap(void) 175 { 176 uint32_t physaddr; 177 vm_offset_t vaddr; 178 uint32_t val; 179 uint32_t start_mask; 180 u_long cpu_resume_base; 181 u_long nb_base; 182 u_long cpu_resume_size; 183 u_long nb_size; 184 bus_addr_t cpu_resume_baddr; 185 bus_addr_t nb_baddr; 186 int a; 187 188 if (alpine_get_cpu_resume_base(&cpu_resume_base, &cpu_resume_size)) 189 panic("Couldn't resolve cpu_resume_base address\n"); 190 191 if (alpine_get_nb_base(&nb_base, &nb_size)) 192 panic("Couldn't resolve_nb_base address\n"); 193 194 /* Proceed with start addresses for additional CPUs */ 195 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + cpu_resume_base, 196 cpu_resume_size, 0, &cpu_resume_baddr)) 197 panic("Couldn't map CPU-resume area"); 198 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base, 199 nb_size, 0, &nb_baddr)) 200 panic("Couldn't map NB-service area"); 201 202 /* Proceed with start addresses for additional CPUs */ 203 val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr, 204 AL_CPU_RESUME_WATERMARK_REG); 205 if (((val & AL_CPU_RESUME_MAGIC_NUM_MASK) != AL_CPU_RESUME_MAGIC_NUM) || 206 ((val & AL_CPU_RESUME_MIN_VER_MASK) < AL_CPU_RESUME_MIN_VER)) { 207 panic("CPU-resume device is not compatible"); 208 } 209 210 vaddr = (vm_offset_t)mpentry; 211 physaddr = pmap_kextract(vaddr); 212 213 for (a = 1; a < platform_mp_get_core_cnt(); a++) { 214 /* Power up the core */ 215 bus_space_write_4(fdtbus_bs_tag, nb_baddr, 216 AL_NB_CONFIG_STATUS_PWR_CTRL(a), 0); 217 mb(); 218 219 /* Enable resume */ 220 val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr, 221 AL_CPU_RESUME_PCPU_FLAGS(a)); 222 val &= ~AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME; 223 bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr, 224 AL_CPU_RESUME_PCPU_FLAGS(a), val); 225 mb(); 226 227 /* Set resume physical address */ 228 bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr, 229 AL_CPU_RESUME_PCPU_RADDR_REG(a), physaddr); 230 mb(); 231 } 232 233 /* Release cores from reset */ 234 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base, 235 nb_size, 0, &nb_baddr)) 236 panic("Couldn't map NB-service area"); 237 238 start_mask = (1 << platform_mp_get_core_cnt()) - 1; 239 240 /* Release cores from reset */ 241 val = bus_space_read_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL); 242 val |= start_mask; 243 bus_space_write_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL, val); 244 dsb(); 245 246 bus_space_unmap(fdtbus_bs_tag, nb_baddr, nb_size); 247 bus_space_unmap(fdtbus_bs_tag, cpu_resume_baddr, cpu_resume_size); 248 } 249