1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #define RSTMGR_STAT 0x0 /* Status */ 32 #define RSTMGR_CTRL 0x4 /* Control */ 33 #define CTRL_SWWARMRSTREQ (1 << 1) /* Trigger warm reset */ 34 #define RSTMGR_COUNTS 0x8 /* Reset Cycles Count */ 35 #define RSTMGR_MPUMODRST 0x10 /* MPU Module Reset */ 36 #define MPUMODRST_CPU1 (1 << 1) 37 #define RSTMGR_PERMODRST 0x14 /* Peripheral Module Reset */ 38 #define RSTMGR_PER2MODRST 0x18 /* Peripheral 2 Module Reset */ 39 #define RSTMGR_BRGMODRST 0x1C /* Bridge Module Reset */ 40 #define BRGMODRST_FPGA2HPS (1 << 2) 41 #define BRGMODRST_LWHPS2FPGA (1 << 1) 42 #define BRGMODRST_HPS2FPGA (1 << 0) 43 #define RSTMGR_MISCMODRST 0x20 /* Miscellaneous Module Reset */ 44 45 #define RSTMGR_A10_CTRL 0xC /* Control */ 46 #define RSTMGR_A10_MPUMODRST 0x20 /* MPU Module Reset */ 47 48 int rstmgr_warmreset(uint32_t reg); 49