1 /*- 2 * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * SOCFPGA Reset Manager. 33 * Chapter 3, Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 */ 35 36 #include <sys/cdefs.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/rman.h> 44 #include <sys/timeet.h> 45 #include <sys/timetc.h> 46 #include <sys/sysctl.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <machine/bus.h> 53 #include <machine/fdt.h> 54 #include <machine/cpu.h> 55 #include <machine/intr.h> 56 57 #include <arm/altera/socfpga/socfpga_common.h> 58 #include <arm/altera/socfpga/socfpga_rstmgr.h> 59 #include <arm/altera/socfpga/socfpga_l3regs.h> 60 61 struct rstmgr_softc { 62 struct resource *res[1]; 63 bus_space_tag_t bst; 64 bus_space_handle_t bsh; 65 device_t dev; 66 }; 67 68 struct rstmgr_softc *rstmgr_sc; 69 70 static struct resource_spec rstmgr_spec[] = { 71 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 72 { -1, 0 } 73 }; 74 75 enum { 76 RSTMGR_SYSCTL_FPGA2HPS, 77 RSTMGR_SYSCTL_LWHPS2FPGA, 78 RSTMGR_SYSCTL_HPS2FPGA 79 }; 80 81 static int 82 l3remap(struct rstmgr_softc *sc, int remap, int enable) 83 { 84 uint32_t paddr; 85 bus_addr_t vaddr; 86 phandle_t node; 87 int reg; 88 89 /* 90 * Control whether bridge is visible to L3 masters or not. 91 * Register is write-only. 92 */ 93 94 reg = REMAP_MPUZERO; 95 if (enable) 96 reg |= (remap); 97 else 98 reg &= ~(remap); 99 100 node = OF_finddevice("l3regs"); 101 if (node == -1) { 102 device_printf(sc->dev, "Can't find l3regs node\n"); 103 return (1); 104 } 105 106 if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { 107 if (bus_space_map(fdtbus_bs_tag, paddr, 0x4, 0, &vaddr) == 0) { 108 bus_space_write_4(fdtbus_bs_tag, vaddr, 109 L3REGS_REMAP, reg); 110 return (0); 111 } 112 } 113 114 return (1); 115 } 116 117 static int 118 rstmgr_sysctl(SYSCTL_HANDLER_ARGS) 119 { 120 struct rstmgr_softc *sc; 121 int enable; 122 int remap; 123 int err; 124 int reg; 125 int bit; 126 127 sc = arg1; 128 129 switch (arg2) { 130 case RSTMGR_SYSCTL_FPGA2HPS: 131 bit = BRGMODRST_FPGA2HPS; 132 remap = 0; 133 break; 134 case RSTMGR_SYSCTL_LWHPS2FPGA: 135 bit = BRGMODRST_LWHPS2FPGA; 136 remap = REMAP_LWHPS2FPGA; 137 break; 138 case RSTMGR_SYSCTL_HPS2FPGA: 139 bit = BRGMODRST_HPS2FPGA; 140 remap = REMAP_HPS2FPGA; 141 break; 142 default: 143 return (1); 144 } 145 146 reg = READ4(sc, RSTMGR_BRGMODRST); 147 enable = reg & bit ? 0 : 1; 148 149 err = sysctl_handle_int(oidp, &enable, 0, req); 150 if (err || !req->newptr) 151 return (err); 152 153 if (enable == 1) 154 reg &= ~(bit); 155 else if (enable == 0) 156 reg |= (bit); 157 else 158 return (EINVAL); 159 160 WRITE4(sc, RSTMGR_BRGMODRST, reg); 161 l3remap(sc, remap, enable); 162 163 return (0); 164 } 165 166 int 167 rstmgr_warmreset(uint32_t reg) 168 { 169 struct rstmgr_softc *sc; 170 171 sc = rstmgr_sc; 172 if (sc == NULL) 173 return (1); 174 175 /* Request warm reset */ 176 WRITE4(sc, reg, CTRL_SWWARMRSTREQ); 177 178 return (0); 179 } 180 181 static int 182 rstmgr_add_sysctl(struct rstmgr_softc *sc) 183 { 184 struct sysctl_oid_list *children; 185 struct sysctl_ctx_list *ctx; 186 187 ctx = device_get_sysctl_ctx(sc->dev); 188 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 189 190 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps", 191 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 192 sc, RSTMGR_SYSCTL_FPGA2HPS, 193 rstmgr_sysctl, "I", "Enable fpga2hps bridge"); 194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga", 195 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 196 sc, RSTMGR_SYSCTL_LWHPS2FPGA, 197 rstmgr_sysctl, "I", "Enable lwhps2fpga bridge"); 198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga", 199 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 200 sc, RSTMGR_SYSCTL_HPS2FPGA, 201 rstmgr_sysctl, "I", "Enable hps2fpga bridge"); 202 203 return (0); 204 } 205 206 static int 207 rstmgr_probe(device_t dev) 208 { 209 210 if (!ofw_bus_status_okay(dev)) 211 return (ENXIO); 212 213 if (!ofw_bus_is_compatible(dev, "altr,rst-mgr")) 214 return (ENXIO); 215 216 device_set_desc(dev, "Reset Manager"); 217 218 return (BUS_PROBE_DEFAULT); 219 } 220 221 static int 222 rstmgr_attach(device_t dev) 223 { 224 struct rstmgr_softc *sc; 225 226 sc = device_get_softc(dev); 227 sc->dev = dev; 228 229 if (bus_alloc_resources(dev, rstmgr_spec, sc->res)) { 230 device_printf(dev, "could not allocate resources\n"); 231 return (ENXIO); 232 } 233 234 /* Memory interface */ 235 sc->bst = rman_get_bustag(sc->res[0]); 236 sc->bsh = rman_get_bushandle(sc->res[0]); 237 238 rstmgr_sc = sc; 239 rstmgr_add_sysctl(sc); 240 241 return (0); 242 } 243 244 static device_method_t rstmgr_methods[] = { 245 DEVMETHOD(device_probe, rstmgr_probe), 246 DEVMETHOD(device_attach, rstmgr_attach), 247 { 0, 0 } 248 }; 249 250 static driver_t rstmgr_driver = { 251 "rstmgr", 252 rstmgr_methods, 253 sizeof(struct rstmgr_softc), 254 }; 255 256 DRIVER_MODULE(rstmgr, simplebus, rstmgr_driver, 0, 0); 257