1 /*- 2 * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "opt_platform.h" 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/smp.h> 41 42 #include <vm/vm.h> 43 #include <vm/pmap.h> 44 45 #include <machine/cpu.h> 46 #include <machine/smp.h> 47 #include <machine/fdt.h> 48 #include <machine/intr.h> 49 #include <machine/platformvar.h> 50 51 #include <arm/altera/socfpga/socfpga_mp.h> 52 #include <arm/altera/socfpga/socfpga_rstmgr.h> 53 54 #define SCU_PHYSBASE 0xFFFEC000 55 #define SCU_PHYSBASE_A10 0xFFFFC000 56 #define SCU_SIZE 0x100 57 58 #define SCU_CONTROL_REG 0x00 59 #define SCU_CONTROL_ENABLE (1 << 0) 60 #define SCU_CONFIG_REG 0x04 61 #define SCU_CONFIG_REG_NCPU_MASK 0x03 62 #define SCU_CPUPOWER_REG 0x08 63 #define SCU_INV_TAGS_REG 0x0c 64 #define SCU_DIAG_CONTROL 0x30 65 #define SCU_DIAG_DISABLE_MIGBIT (1 << 0) 66 #define SCU_FILTER_START_REG 0x40 67 #define SCU_FILTER_END_REG 0x44 68 #define SCU_SECURE_ACCESS_REG 0x50 69 #define SCU_NONSECURE_ACCESS_REG 0x54 70 71 #define RSTMGR_PHYSBASE 0xFFD05000 72 #define RSTMGR_SIZE 0x100 73 74 #define RAM_PHYSBASE 0x0 75 #define RAM_SIZE 0x1000 76 77 #define SOCFPGA_ARRIA10 1 78 #define SOCFPGA_CYCLONE5 2 79 80 extern char *mpentry_addr; 81 static void socfpga_trampoline(void); 82 83 static void 84 socfpga_trampoline(void) 85 { 86 87 __asm __volatile( 88 "ldr pc, 1f\n" 89 ".globl mpentry_addr\n" 90 "mpentry_addr:\n" 91 "1: .space 4\n"); 92 } 93 94 void 95 socfpga_mp_setmaxid(platform_t plat) 96 { 97 int hwcpu, ncpu; 98 99 /* If we've already set this don't bother to do it again. */ 100 if (mp_ncpus != 0) 101 return; 102 103 hwcpu = 2; 104 105 ncpu = hwcpu; 106 TUNABLE_INT_FETCH("hw.ncpu", &ncpu); 107 if (ncpu < 1 || ncpu > hwcpu) 108 ncpu = hwcpu; 109 110 mp_ncpus = ncpu; 111 mp_maxid = ncpu - 1; 112 } 113 114 static void 115 _socfpga_mp_start_ap(uint32_t platid) 116 { 117 bus_space_handle_t scu, rst, ram; 118 int reg; 119 120 switch (platid) { 121 #if defined(SOC_ALTERA_ARRIA10) 122 case SOCFPGA_ARRIA10: 123 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10, 124 SCU_SIZE, 0, &scu) != 0) 125 panic("Couldn't map the SCU\n"); 126 break; 127 #endif 128 #if defined(SOC_ALTERA_CYCLONE5) 129 case SOCFPGA_CYCLONE5: 130 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, 131 SCU_SIZE, 0, &scu) != 0) 132 panic("Couldn't map the SCU\n"); 133 break; 134 #endif 135 default: 136 panic("Unknown platform id %d\n", platid); 137 } 138 139 if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE, 140 RSTMGR_SIZE, 0, &rst) != 0) 141 panic("Couldn't map the reset manager (RSTMGR)\n"); 142 if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE, 143 RAM_SIZE, 0, &ram) != 0) 144 panic("Couldn't map the first physram page\n"); 145 146 /* Invalidate SCU cache tags */ 147 bus_space_write_4(fdtbus_bs_tag, scu, 148 SCU_INV_TAGS_REG, 0x0000ffff); 149 150 /* 151 * Erratum ARM/MP: 764369 (problems with cache maintenance). 152 * Setting the "disable-migratory bit" in the undocumented SCU 153 * Diagnostic Control Register helps work around the problem. 154 */ 155 reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); 156 reg |= (SCU_DIAG_DISABLE_MIGBIT); 157 bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg); 158 159 /* Put CPU1 to reset state */ 160 switch (platid) { 161 #if defined(SOC_ALTERA_ARRIA10) 162 case SOCFPGA_ARRIA10: 163 bus_space_write_4(fdtbus_bs_tag, rst, 164 RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1); 165 break; 166 #endif 167 #if defined(SOC_ALTERA_CYCLONE5) 168 case SOCFPGA_CYCLONE5: 169 bus_space_write_4(fdtbus_bs_tag, rst, 170 RSTMGR_MPUMODRST, MPUMODRST_CPU1); 171 break; 172 #endif 173 default: 174 panic("Unknown platform id %d\n", platid); 175 } 176 177 /* Enable the SCU, then clean the cache on this core */ 178 reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); 179 reg |= (SCU_CONTROL_ENABLE); 180 bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg); 181 182 /* Set up trampoline code */ 183 mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry); 184 bus_space_write_region_4(fdtbus_bs_tag, ram, 0, 185 (uint32_t *)&socfpga_trampoline, 8); 186 187 dcache_wbinv_poc_all(); 188 189 /* Put CPU1 out from reset */ 190 switch (platid) { 191 #if defined(SOC_ALTERA_ARRIA10) 192 case SOCFPGA_ARRIA10: 193 bus_space_write_4(fdtbus_bs_tag, rst, 194 RSTMGR_A10_MPUMODRST, 0); 195 break; 196 #endif 197 #if defined(SOC_ALTERA_CYCLONE5) 198 case SOCFPGA_CYCLONE5: 199 bus_space_write_4(fdtbus_bs_tag, rst, 200 RSTMGR_MPUMODRST, 0); 201 break; 202 #endif 203 default: 204 panic("Unknown platform id %d\n", platid); 205 } 206 207 dsb(); 208 sev(); 209 210 bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); 211 bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE); 212 bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE); 213 } 214 215 #if defined(SOC_ALTERA_ARRIA10) 216 void 217 socfpga_a10_mp_start_ap(platform_t plat) 218 { 219 220 _socfpga_mp_start_ap(SOCFPGA_ARRIA10); 221 } 222 #endif 223 224 #if defined(SOC_ALTERA_CYCLONE5) 225 void 226 socfpga_mp_start_ap(platform_t plat) 227 { 228 229 _socfpga_mp_start_ap(SOCFPGA_CYCLONE5); 230 } 231 #endif 232