1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __IF_EMACREG_H__ 32 #define __IF_EMACREG_H__ 33 34 /* 35 * EMAC register definitions 36 */ 37 #define EMAC_CTL 0x00 38 #define EMAC_CTL_RST (1 << 0) 39 #define EMAC_CTL_TX_EN (1 << 1) 40 #define EMAC_CTL_RX_EN (1 << 2) 41 42 #define EMAC_TX_MODE 0x04 43 #define EMAC_TX_FLOW 0x08 44 #define EMAC_TX_CTL0 0x0C 45 #define EMAC_TX_CTL1 0x10 46 #define EMAC_TX_INS 0x14 47 #define EMAC_TX_PL0 0x18 48 #define EMAC_TX_PL1 0x1C 49 #define EMAC_TX_STA 0x20 50 #define EMAC_TX_IO_DATA 0x24 51 #define EMAC_TX_IO_DATA1 0x28 52 #define EMAC_TX_TSVL0 0x2C 53 #define EMAC_TX_TSVH0 0x30 54 #define EMAC_TX_TSVL1 0x34 55 #define EMAC_TX_TSVH1 0x38 56 #define EMAC_TX_FIFO0 (1 << 0) 57 #define EMAC_TX_FIFO1 (1 << 1) 58 59 #define EMAC_RX_CTL 0x3C 60 #define EMAC_RX_HASH0 0x40 61 #define EMAC_RX_HASH1 0x44 62 #define EMAC_RX_STA 0x48 63 #define EMAC_RX_IO_DATA 0x4C 64 #define EMAC_RX_FBC 0x50 65 66 #define EMAC_INT_CTL 0x54 67 #define EMAC_INT_STA 0x58 68 #define EMAC_INT_STA_TX (EMAC_TX_FIFO0 | EMAC_TX_FIFO1) 69 #define EMAC_INT_STA_RX 0x100 70 #define EMAC_INT_EN (0xf << 0) | (1 << 8) 71 72 #define EMAC_MAC_CTL0 0x5C 73 #define EMAC_MAC_CTL1 0x60 74 #define EMAC_MAC_IPGT 0x64 75 #define EMAC_MAC_IPGR 0x68 76 #define EMAC_MAC_CLRT 0x6C 77 #define EMAC_MAC_MAXF 0x70 78 #define EMAC_MAC_SUPP 0x74 79 #define EMAC_MAC_TEST 0x78 80 #define EMAC_MAC_MCFG 0x7C 81 #define EMAC_MAC_MCMD 0x80 82 #define EMAC_MAC_MADR 0x84 83 #define EMAC_MAC_MWTD 0x88 84 #define EMAC_MAC_MRDD 0x8C 85 #define EMAC_MAC_MIND 0x90 86 #define EMAC_MAC_SSRR 0x94 87 #define EMAC_MAC_A0 0x98 88 #define EMAC_MAC_A1 0x9C 89 #define EMAC_MAC_A2 0xA0 90 91 #define EMAC_SAFX_L0 0xA4 92 #define EMAC_SAFX_H0 0xA8 93 #define EMAC_SAFX_L1 0xAC 94 #define EMAC_SAFX_H1 0xB0 95 #define EMAC_SAFX_L2 0xB4 96 #define EMAC_SAFX_H2 0xB8 97 #define EMAC_SAFX_L3 0xBC 98 #define EMAC_SAFX_H3 0xC0 99 100 #define EMAC_PHY_DUPLEX (1 << 8) 101 102 /* 103 * Each received packet has 8 bytes header: 104 * Byte 0: Packet valid flag: 0x01 valid, 0x00 not valid 105 * Byte 1: 0x43 -> Ascii code 'C' 106 * Byte 2: 0x41 -> Ascii code 'A' 107 * Byte 3: 0x4d -> Ascii code 'M' 108 * Byte 4: High byte of received packet's status 109 * Byte 5: Low byte of received packet's status 110 * Byte 6: High byte of packet size 111 * Byte 7: Low byte of packet size 112 */ 113 #define EMAC_PACKET_HEADER (0x0143414d) 114 115 /* Aborted frame enable */ 116 #define EMAC_TX_AB_M (1 << 0) 117 118 /* 0: Enable CPU mode for TX, 1: DMA */ 119 #define EMAC_TX_TM ~(1 << 1) 120 121 /* 0: DRQ asserted, 1: DRQ automatically */ 122 #define EMAC_RX_DRQ_MODE (1 << 1) 123 124 /* 0: Enable CPU mode for RX, 1: DMA */ 125 #define EMAC_RX_TM ~(1 << 2) 126 127 /* Pass all Frames */ 128 #define EMAC_RX_PA (1 << 4) 129 130 /* Pass Control Frames */ 131 #define EMAC_RX_PCF (1 << 5) 132 133 /* Pass Frames with CRC Error */ 134 #define EMAC_RX_PCRCE (1 << 6) 135 136 /* Pass Frames with Length Error */ 137 #define EMAC_RX_PLE (1 << 7) 138 139 /* Pass Frames length out of range */ 140 #define EMAC_RX_POR (1 << 8) 141 142 /* Accept unicast Packets */ 143 #define EMAC_RX_UCAD (1 << 16) 144 145 /* Enable DA Filtering */ 146 #define EMAC_RX_DAF (1 << 17) 147 148 /* Accept multicast Packets */ 149 #define EMAC_RX_MCO (1 << 20) 150 151 /* Enable Hash filter */ 152 #define EMAC_RX_MHF (1 << 21) 153 154 /* Accept Broadcast Packets */ 155 #define EMAC_RX_BCO (1 << 22) 156 157 /* Enable SA Filtering */ 158 #define EMAC_RX_SAF (1 << 24) 159 160 /* Inverse Filtering */ 161 #define EMAC_RX_SAIF (1 << 25) 162 163 #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | \ 164 EMAC_RX_DAF | EMAC_RX_MCO | EMAC_RX_BCO) 165 166 /* Enable Receive Flow Control */ 167 #define EMAC_MAC_CTL0_RFC (1 << 2) 168 169 /* Enable Transmit Flow Control */ 170 #define EMAC_MAC_CTL0_TFC (1 << 3) 171 172 /* Enable soft reset */ 173 #define EMAC_MAC_CTL0_SOFT_RST (1 << 15) 174 175 #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) 176 177 /* Enable duplex */ 178 #define EMAC_MAC_CTL1_DUP (1 << 0) 179 180 /* Enable MAC Frame Length Checking */ 181 #define EMAC_MAC_CTL1_FLC (1 << 1) 182 183 /* Enable Huge Frame */ 184 #define EMAC_MAC_CTL1_HF (1 << 2) 185 186 /* Enable MAC Delayed CRC */ 187 #define EMAC_MAC_CTL1_DCRC (1 << 3) 188 189 /* Enable MAC CRC */ 190 #define EMAC_MAC_CTL1_CRC (1 << 4) 191 192 /* Enable MAC PAD Short frames */ 193 #define EMAC_MAC_CTL1_PC (1 << 5) 194 195 /* Enable MAC PAD Short frames and append CRC */ 196 #define EMAC_MAC_CTL1_VC (1 << 6) 197 198 /* Enable MAC auto detect Short frames */ 199 #define EMAC_MAC_CTL1_ADP (1 << 7) 200 201 #define EMAC_MAC_CTL1_PRE (1 << 8) 202 #define EMAC_MAC_CTL1_LPE (1 << 9) 203 204 /* Enable no back off */ 205 #define EMAC_MAC_CTL1_NB (1 << 12) 206 207 #define EMAC_MAC_CTL1_BNB (1 << 13) 208 #define EMAC_MAC_CTL1_ED (1 << 14) 209 210 #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ 211 EMAC_MAC_CTL1_PC) 212 213 /* half duplex */ 214 #define EMAC_MAC_IPGT_HD 0x12 215 216 /* full duplex */ 217 #define EMAC_MAC_IPGT_FD 0x15 218 219 #define EMAC_MAC_NBTB_IPG1 0xC 220 #define EMAC_MAC_NBTB_IPG2 0x12 221 222 #define EMAC_MAC_CW 0x37 223 #define EMAC_MAC_RM 0xF 224 225 #define EMAC_MAC_MFL 0x0600 226 227 /* Receive status */ 228 #define EMAC_CRCERR (1 << 4) 229 #define EMAC_LENERR (3 << 5) 230 #define EMAC_PKT_OK (1 << 7) 231 232 #define EMAC_RX_FLUSH_FIFO (1 << 3) 233 #define EMAC_PHY_RESET (1 << 15) 234 #define EMAC_PHY_PWRDOWN (1 << 11) 235 236 #define EMAC_PROC_MIN 16 237 #define EMAC_PROC_MAX 255 238 #define EMAC_PROC_DEFAULT 64 239 240 #define EMAC_LOCK(cs) mtx_lock(&(sc)->emac_mtx) 241 #define EMAC_UNLOCK(cs) mtx_unlock(&(sc)->emac_mtx) 242 #define EMAC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->emac_mtx, MA_OWNED); 243 244 #endif /* __IF_EMACREG_H__ */ 245