1 /* 2 * Copyright (C) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef __IF_EMACREG_H__ 30 #define __IF_EMACREG_H__ 31 32 /* 33 * EMAC register definitions 34 */ 35 #define EMAC_CTL 0x00 36 #define EMAC_CTL_RST (1 << 0) 37 #define EMAC_CTL_TX_EN (1 << 1) 38 #define EMAC_CTL_RX_EN (1 << 2) 39 40 #define EMAC_TX_MODE 0x04 41 #define EMAC_TX_FLOW 0x08 42 #define EMAC_TX_CTL0 0x0C 43 #define EMAC_TX_CTL1 0x10 44 #define EMAC_TX_INS 0x14 45 #define EMAC_TX_PL0 0x18 46 #define EMAC_TX_PL1 0x1C 47 #define EMAC_TX_STA 0x20 48 #define EMAC_TX_IO_DATA 0x24 49 #define EMAC_TX_IO_DATA1 0x28 50 #define EMAC_TX_TSVL0 0x2C 51 #define EMAC_TX_TSVH0 0x30 52 #define EMAC_TX_TSVL1 0x34 53 #define EMAC_TX_TSVH1 0x38 54 #define EMAC_TX_FIFO0 (1 << 0) 55 #define EMAC_TX_FIFO1 (1 << 1) 56 57 #define EMAC_RX_CTL 0x3C 58 #define EMAC_RX_HASH0 0x40 59 #define EMAC_RX_HASH1 0x44 60 #define EMAC_RX_STA 0x48 61 #define EMAC_RX_IO_DATA 0x4C 62 #define EMAC_RX_FBC 0x50 63 64 #define EMAC_INT_CTL 0x54 65 #define EMAC_INT_STA 0x58 66 #define EMAC_INT_STA_TX (EMAC_TX_FIFO0 | EMAC_TX_FIFO1) 67 #define EMAC_INT_STA_RX 0x100 68 #define EMAC_INT_EN (0xf << 0) | (1 << 8) 69 70 #define EMAC_MAC_CTL0 0x5C 71 #define EMAC_MAC_CTL1 0x60 72 #define EMAC_MAC_IPGT 0x64 73 #define EMAC_MAC_IPGR 0x68 74 #define EMAC_MAC_CLRT 0x6C 75 #define EMAC_MAC_MAXF 0x70 76 #define EMAC_MAC_SUPP 0x74 77 #define EMAC_MAC_TEST 0x78 78 #define EMAC_MAC_MCFG 0x7C 79 #define EMAC_MAC_MCMD 0x80 80 #define EMAC_MAC_MADR 0x84 81 #define EMAC_MAC_MWTD 0x88 82 #define EMAC_MAC_MRDD 0x8C 83 #define EMAC_MAC_MIND 0x90 84 #define EMAC_MAC_SSRR 0x94 85 #define EMAC_MAC_A0 0x98 86 #define EMAC_MAC_A1 0x9C 87 #define EMAC_MAC_A2 0xA0 88 89 #define EMAC_SAFX_L0 0xA4 90 #define EMAC_SAFX_H0 0xA8 91 #define EMAC_SAFX_L1 0xAC 92 #define EMAC_SAFX_H1 0xB0 93 #define EMAC_SAFX_L2 0xB4 94 #define EMAC_SAFX_H2 0xB8 95 #define EMAC_SAFX_L3 0xBC 96 #define EMAC_SAFX_H3 0xC0 97 98 #define EMAC_PHY_DUPLEX (1 << 8) 99 100 /* 101 * Each received packet has 8 bytes header: 102 * Byte 0: Packet valid flag: 0x01 valid, 0x00 not valid 103 * Byte 1: 0x43 -> Ascii code 'C' 104 * Byte 2: 0x41 -> Ascii code 'A' 105 * Byte 3: 0x4d -> Ascii code 'M' 106 * Byte 4: High byte of received packet's status 107 * Byte 5: Low byte of received packet's status 108 * Byte 6: High byte of packet size 109 * Byte 7: Low byte of packet size 110 */ 111 #define EMAC_PACKET_HEADER (0x0143414d) 112 113 /* Aborted frame enable */ 114 #define EMAC_TX_AB_M (1 << 0) 115 116 /* 0: Enable CPU mode for TX, 1: DMA */ 117 #define EMAC_TX_TM ~(1 << 1) 118 119 /* 0: DRQ asserted, 1: DRQ automatically */ 120 #define EMAC_RX_DRQ_MODE (1 << 1) 121 122 /* 0: Enable CPU mode for RX, 1: DMA */ 123 #define EMAC_RX_TM ~(1 << 2) 124 125 /* Pass all Frames */ 126 #define EMAC_RX_PA (1 << 4) 127 128 /* Pass Control Frames */ 129 #define EMAC_RX_PCF (1 << 5) 130 131 /* Pass Frames with CRC Error */ 132 #define EMAC_RX_PCRCE (1 << 6) 133 134 /* Pass Frames with Length Error */ 135 #define EMAC_RX_PLE (1 << 7) 136 137 /* Pass Frames length out of range */ 138 #define EMAC_RX_POR (1 << 8) 139 140 /* Accept unicast Packets */ 141 #define EMAC_RX_UCAD (1 << 16) 142 143 /* Enable DA Filtering */ 144 #define EMAC_RX_DAF (1 << 17) 145 146 /* Accept multicast Packets */ 147 #define EMAC_RX_MCO (1 << 20) 148 149 /* Enable Hash filter */ 150 #define EMAC_RX_MHF (1 << 21) 151 152 /* Accept Broadcast Packets */ 153 #define EMAC_RX_BCO (1 << 22) 154 155 /* Enable SA Filtering */ 156 #define EMAC_RX_SAF (1 << 24) 157 158 /* Inverse Filtering */ 159 #define EMAC_RX_SAIF (1 << 25) 160 161 #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | \ 162 EMAC_RX_DAF | EMAC_RX_MCO | EMAC_RX_BCO) 163 164 /* Enable Receive Flow Control */ 165 #define EMAC_MAC_CTL0_RFC (1 << 2) 166 167 /* Enable Transmit Flow Control */ 168 #define EMAC_MAC_CTL0_TFC (1 << 3) 169 170 /* Enable soft reset */ 171 #define EMAC_MAC_CTL0_SOFT_RST (1 << 15) 172 173 #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) 174 175 /* Enable duplex */ 176 #define EMAC_MAC_CTL1_DUP (1 << 0) 177 178 /* Enable MAC Frame Length Checking */ 179 #define EMAC_MAC_CTL1_FLC (1 << 1) 180 181 /* Enable Huge Frame */ 182 #define EMAC_MAC_CTL1_HF (1 << 2) 183 184 /* Enable MAC Delayed CRC */ 185 #define EMAC_MAC_CTL1_DCRC (1 << 3) 186 187 /* Enable MAC CRC */ 188 #define EMAC_MAC_CTL1_CRC (1 << 4) 189 190 /* Enable MAC PAD Short frames */ 191 #define EMAC_MAC_CTL1_PC (1 << 5) 192 193 /* Enable MAC PAD Short frames and append CRC */ 194 #define EMAC_MAC_CTL1_VC (1 << 6) 195 196 /* Enable MAC auto detect Short frames */ 197 #define EMAC_MAC_CTL1_ADP (1 << 7) 198 199 #define EMAC_MAC_CTL1_PRE (1 << 8) 200 #define EMAC_MAC_CTL1_LPE (1 << 9) 201 202 /* Enable no back off */ 203 #define EMAC_MAC_CTL1_NB (1 << 12) 204 205 #define EMAC_MAC_CTL1_BNB (1 << 13) 206 #define EMAC_MAC_CTL1_ED (1 << 14) 207 208 #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ 209 EMAC_MAC_CTL1_PC) 210 211 /* half duplex */ 212 #define EMAC_MAC_IPGT_HD 0x12 213 214 /* full duplex */ 215 #define EMAC_MAC_IPGT_FD 0x15 216 217 #define EMAC_MAC_NBTB_IPG1 0xC 218 #define EMAC_MAC_NBTB_IPG2 0x12 219 220 #define EMAC_MAC_CW 0x37 221 #define EMAC_MAC_RM 0xF 222 223 #define EMAC_MAC_MFL 0x0600 224 225 /* Receive status */ 226 #define EMAC_CRCERR (1 << 4) 227 #define EMAC_LENERR (3 << 5) 228 #define EMAC_PKT_OK (1 << 7) 229 230 #define EMAC_RX_FLUSH_FIFO (1 << 3) 231 #define EMAC_PHY_RESET (1 << 15) 232 #define EMAC_PHY_PWRDOWN (1 << 11) 233 234 #define EMAC_PROC_MIN 16 235 #define EMAC_PROC_MAX 255 236 #define EMAC_PROC_DEFAULT 64 237 238 #define EMAC_LOCK(cs) mtx_lock(&(sc)->emac_mtx) 239 #define EMAC_UNLOCK(cs) mtx_unlock(&(sc)->emac_mtx) 240 #define EMAC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->emac_mtx, MA_OWNED); 241 242 #endif /* __IF_EMACREG_H__ */ 243