1 /*- 2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* A10/A20 EMAC driver */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/lock.h> 40 #include <sys/mbuf.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/gpio.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/intr.h> 51 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_arp.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_mib.h> 59 #include <net/ethernet.h> 60 #include <net/if_vlan_var.h> 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #endif 68 69 #include <net/bpf.h> 70 #include <net/bpfdesc.h> 71 72 #include <dev/ofw/ofw_bus.h> 73 #include <dev/ofw/ofw_bus_subr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <arm/allwinner/if_emacreg.h> 79 #include <arm/allwinner/aw_sid.h> 80 81 #include <dev/extres/clk/clk.h> 82 83 #include "miibus_if.h" 84 85 #include "gpio_if.h" 86 87 #include "a10_sramc.h" 88 89 struct emac_softc { 90 struct ifnet *emac_ifp; 91 device_t emac_dev; 92 device_t emac_miibus; 93 bus_space_handle_t emac_handle; 94 bus_space_tag_t emac_tag; 95 struct resource *emac_res; 96 struct resource *emac_irq; 97 void *emac_intrhand; 98 clk_t emac_clk; 99 int emac_if_flags; 100 struct mtx emac_mtx; 101 struct callout emac_tick_ch; 102 int emac_watchdog_timer; 103 int emac_rx_process_limit; 104 int emac_link; 105 uint32_t emac_fifo_mask; 106 }; 107 108 static int emac_probe(device_t); 109 static int emac_attach(device_t); 110 static int emac_detach(device_t); 111 static int emac_shutdown(device_t); 112 static int emac_suspend(device_t); 113 static int emac_resume(device_t); 114 115 static int emac_sys_setup(struct emac_softc *); 116 static void emac_reset(struct emac_softc *); 117 118 static void emac_init_locked(struct emac_softc *); 119 static void emac_start_locked(struct ifnet *); 120 static void emac_init(void *); 121 static void emac_stop_locked(struct emac_softc *); 122 static void emac_intr(void *); 123 static int emac_ioctl(struct ifnet *, u_long, caddr_t); 124 125 static void emac_rxeof(struct emac_softc *, int); 126 static void emac_txeof(struct emac_softc *, uint32_t); 127 128 static int emac_miibus_readreg(device_t, int, int); 129 static int emac_miibus_writereg(device_t, int, int, int); 130 static void emac_miibus_statchg(device_t); 131 132 static int emac_ifmedia_upd(struct ifnet *); 133 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *); 134 135 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 136 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS); 137 138 #define EMAC_READ_REG(sc, reg) \ 139 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg) 140 #define EMAC_WRITE_REG(sc, reg, val) \ 141 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val) 142 143 static int 144 emac_sys_setup(struct emac_softc *sc) 145 { 146 int error; 147 148 /* Activate EMAC clock. */ 149 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk); 150 if (error != 0) { 151 device_printf(sc->emac_dev, "cannot get clock\n"); 152 return (error); 153 } 154 error = clk_enable(sc->emac_clk); 155 if (error != 0) { 156 device_printf(sc->emac_dev, "cannot enable clock\n"); 157 return (error); 158 } 159 160 /* Map sram. */ 161 a10_map_to_emac(); 162 163 return (0); 164 } 165 166 static void 167 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr) 168 { 169 uint32_t val0, val1, rnd; 170 u_char rootkey[16]; 171 172 /* 173 * Try to get MAC address from running hardware. 174 * If there is something non-zero there just use it. 175 * 176 * Otherwise set the address to a convenient locally assigned address, 177 * using the SID rootkey. 178 * This is was uboot does so we end up with the same mac as if uboot 179 * did set it. 180 * If we can't get the root key, generate a random one, 181 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 182 * assigned bit set, and the broadcast/multicast bit clear. 183 */ 184 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0); 185 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1); 186 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) { 187 hwaddr[0] = (val1 >> 16) & 0xff; 188 hwaddr[1] = (val1 >> 8) & 0xff; 189 hwaddr[2] = (val1 >> 0) & 0xff; 190 hwaddr[3] = (val0 >> 16) & 0xff; 191 hwaddr[4] = (val0 >> 8) & 0xff; 192 hwaddr[5] = (val0 >> 0) & 0xff; 193 } else { 194 if (aw_sid_get_rootkey(rootkey) == 0) { 195 hwaddr[0] = 0x2; 196 hwaddr[1] = rootkey[3]; 197 hwaddr[2] = rootkey[12]; 198 hwaddr[3] = rootkey[13]; 199 hwaddr[4] = rootkey[14]; 200 hwaddr[5] = rootkey[15]; 201 } 202 else { 203 rnd = arc4random() & 0x00ffffff; 204 hwaddr[0] = 'b'; 205 hwaddr[1] = 's'; 206 hwaddr[2] = 'd'; 207 hwaddr[3] = (rnd >> 16) & 0xff; 208 hwaddr[4] = (rnd >> 8) & 0xff; 209 hwaddr[5] = (rnd >> 0) & 0xff; 210 } 211 } 212 if (bootverbose) 213 printf("MAC address: %s\n", ether_sprintf(hwaddr)); 214 } 215 216 static void 217 emac_set_rx_mode(struct emac_softc *sc) 218 { 219 struct ifnet *ifp; 220 struct ifmultiaddr *ifma; 221 uint32_t h, hashes[2]; 222 uint32_t rcr = 0; 223 224 EMAC_ASSERT_LOCKED(sc); 225 226 ifp = sc->emac_ifp; 227 228 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); 229 230 /* Unicast packet and DA filtering */ 231 rcr |= EMAC_RX_UCAD; 232 rcr |= EMAC_RX_DAF; 233 234 hashes[0] = 0; 235 hashes[1] = 0; 236 if (ifp->if_flags & IFF_ALLMULTI) { 237 hashes[0] = 0xffffffff; 238 hashes[1] = 0xffffffff; 239 } else { 240 if_maddr_rlock(ifp); 241 TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) { 242 if (ifma->ifma_addr->sa_family != AF_LINK) 243 continue; 244 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 245 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 246 hashes[h >> 5] |= 1 << (h & 0x1f); 247 } 248 if_maddr_runlock(ifp); 249 } 250 rcr |= EMAC_RX_MCO; 251 rcr |= EMAC_RX_MHF; 252 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]); 253 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]); 254 255 if (ifp->if_flags & IFF_BROADCAST) { 256 rcr |= EMAC_RX_BCO; 257 rcr |= EMAC_RX_MCO; 258 } 259 260 if (ifp->if_flags & IFF_PROMISC) 261 rcr |= EMAC_RX_PA; 262 else 263 rcr |= EMAC_RX_UCAD; 264 265 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr); 266 } 267 268 static void 269 emac_reset(struct emac_softc *sc) 270 { 271 272 EMAC_WRITE_REG(sc, EMAC_CTL, 0); 273 DELAY(200); 274 EMAC_WRITE_REG(sc, EMAC_CTL, 1); 275 DELAY(200); 276 } 277 278 static void 279 emac_drain_rxfifo(struct emac_softc *sc) 280 { 281 uint32_t data; 282 283 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0) 284 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 285 } 286 287 static void 288 emac_txeof(struct emac_softc *sc, uint32_t status) 289 { 290 struct ifnet *ifp; 291 292 EMAC_ASSERT_LOCKED(sc); 293 294 ifp = sc->emac_ifp; 295 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1); 296 sc->emac_fifo_mask &= ~status; 297 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 298 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2); 299 else 300 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 301 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 302 303 /* Unarm watchdog timer if no TX */ 304 sc->emac_watchdog_timer = 0; 305 } 306 307 static void 308 emac_rxeof(struct emac_softc *sc, int count) 309 { 310 struct ifnet *ifp; 311 struct mbuf *m, *m0; 312 uint32_t reg_val, rxcount; 313 int16_t len; 314 uint16_t status; 315 int i; 316 317 ifp = sc->emac_ifp; 318 for (; count > 0 && 319 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) { 320 /* 321 * Race warning: The first packet might arrive with 322 * the interrupts disabled, but the second will fix 323 */ 324 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 325 if (!rxcount) { 326 /* Had one stuck? */ 327 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 328 if (!rxcount) 329 return; 330 } 331 /* Check packet header */ 332 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 333 if (reg_val != EMAC_PACKET_HEADER) { 334 /* Packet header is wrong */ 335 if (bootverbose) 336 if_printf(ifp, "wrong packet header\n"); 337 /* Disable RX */ 338 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 339 reg_val &= ~EMAC_CTL_RX_EN; 340 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 341 342 /* Flush RX FIFO */ 343 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 344 reg_val |= EMAC_RX_FLUSH_FIFO; 345 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 346 for (i = 100; i > 0; i--) { 347 DELAY(100); 348 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) & 349 EMAC_RX_FLUSH_FIFO) == 0) 350 break; 351 } 352 if (i == 0) { 353 device_printf(sc->emac_dev, 354 "flush FIFO timeout\n"); 355 /* Reinitialize controller */ 356 emac_init_locked(sc); 357 return; 358 } 359 /* Enable RX */ 360 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 361 reg_val |= EMAC_CTL_RX_EN; 362 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 363 364 return; 365 } 366 367 /* Get packet size and status */ 368 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 369 len = reg_val & 0xffff; 370 status = (reg_val >> 16) & 0xffff; 371 372 if (len < 64 || (status & EMAC_PKT_OK) == 0) { 373 if (bootverbose) 374 if_printf(ifp, 375 "bad packet: len = %i status = %i\n", 376 len, status); 377 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 378 emac_drain_rxfifo(sc); 379 continue; 380 } 381 #if 0 382 if (status & (EMAC_CRCERR | EMAC_LENERR)) { 383 good_packet = 0; 384 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 385 if (status & EMAC_CRCERR) 386 if_printf(ifp, "crc error\n"); 387 if (status & EMAC_LENERR) 388 if_printf(ifp, "length error\n"); 389 } 390 #endif 391 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 392 if (m == NULL) { 393 emac_drain_rxfifo(sc); 394 return; 395 } 396 m->m_len = m->m_pkthdr.len = MCLBYTES; 397 398 /* Copy entire frame to mbuf first. */ 399 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle, 400 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4); 401 402 m->m_pkthdr.rcvif = ifp; 403 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN; 404 405 /* 406 * Emac controller needs strict aligment, so to avoid 407 * copying over an entire frame to align, we allocate 408 * a new mbuf and copy ethernet header + IP header to 409 * the new mbuf. The new mbuf is prepended into the 410 * existing mbuf chain. 411 */ 412 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) { 413 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 414 m->m_data += ETHER_HDR_LEN; 415 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) && 416 m->m_len > (MHLEN - ETHER_HDR_LEN)) { 417 MGETHDR(m0, M_NOWAIT, MT_DATA); 418 if (m0 != NULL) { 419 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen; 420 bcopy(m->m_data, m0->m_data, len); 421 m->m_data += len; 422 m->m_len -= len; 423 m0->m_len = len; 424 M_MOVE_PKTHDR(m0, m); 425 m0->m_next = m; 426 m = m0; 427 } else { 428 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 429 m_freem(m); 430 m = NULL; 431 continue; 432 } 433 } else if (m->m_len > EMAC_MAC_MAXF) { 434 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 435 m_freem(m); 436 m = NULL; 437 continue; 438 } 439 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 440 EMAC_UNLOCK(sc); 441 (*ifp->if_input)(ifp, m); 442 EMAC_LOCK(sc); 443 } 444 } 445 446 static void 447 emac_watchdog(struct emac_softc *sc) 448 { 449 struct ifnet *ifp; 450 451 EMAC_ASSERT_LOCKED(sc); 452 453 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer) 454 return; 455 456 ifp = sc->emac_ifp; 457 458 if (sc->emac_link == 0) { 459 if (bootverbose) 460 if_printf(sc->emac_ifp, "watchdog timeout " 461 "(missed link)\n"); 462 } else 463 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n"); 464 465 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 466 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 467 emac_init_locked(sc); 468 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 469 emac_start_locked(ifp); 470 } 471 472 static void 473 emac_tick(void *arg) 474 { 475 struct emac_softc *sc; 476 struct mii_data *mii; 477 478 sc = (struct emac_softc *)arg; 479 mii = device_get_softc(sc->emac_miibus); 480 mii_tick(mii); 481 482 emac_watchdog(sc); 483 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 484 } 485 486 static void 487 emac_init(void *xcs) 488 { 489 struct emac_softc *sc; 490 491 sc = (struct emac_softc *)xcs; 492 EMAC_LOCK(sc); 493 emac_init_locked(sc); 494 EMAC_UNLOCK(sc); 495 } 496 497 static void 498 emac_init_locked(struct emac_softc *sc) 499 { 500 struct ifnet *ifp; 501 struct mii_data *mii; 502 uint32_t reg_val; 503 uint8_t *eaddr; 504 505 EMAC_ASSERT_LOCKED(sc); 506 507 ifp = sc->emac_ifp; 508 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 509 return; 510 511 /* Flush RX FIFO */ 512 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 513 reg_val |= EMAC_RX_FLUSH_FIFO; 514 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 515 DELAY(1); 516 517 /* Soft reset MAC */ 518 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 519 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); 520 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 521 522 /* Set MII clock */ 523 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); 524 reg_val &= (~(0xf << 2)); 525 reg_val |= (0xd << 2); 526 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); 527 528 /* Clear RX counter */ 529 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); 530 531 /* Disable all interrupt and clear interrupt status */ 532 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 533 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 534 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 535 DELAY(1); 536 537 /* Set up TX */ 538 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); 539 reg_val |= EMAC_TX_AB_M; 540 reg_val &= EMAC_TX_TM; 541 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); 542 543 /* Set up RX */ 544 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 545 reg_val |= EMAC_RX_SETUP; 546 reg_val &= EMAC_RX_TM; 547 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 548 549 /* Set up MAC CTL0. */ 550 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 551 reg_val |= EMAC_MAC_CTL0_SETUP; 552 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 553 554 /* Set up MAC CTL1. */ 555 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1); 556 reg_val |= EMAC_MAC_CTL1_SETUP; 557 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val); 558 559 /* Set up IPGT */ 560 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD); 561 562 /* Set up IPGR */ 563 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 | 564 (EMAC_MAC_NBTB_IPG1 << 8)); 565 566 /* Set up Collison window */ 567 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8)); 568 569 /* Set up Max Frame Length */ 570 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL); 571 572 /* Setup ethernet address */ 573 eaddr = IF_LLADDR(ifp); 574 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 | 575 eaddr[1] << 8 | eaddr[2]); 576 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 | 577 eaddr[4] << 8 | eaddr[5]); 578 579 /* Setup rx filter */ 580 emac_set_rx_mode(sc); 581 582 /* Enable RX/TX0/RX Hlevel interrupt */ 583 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 584 reg_val |= EMAC_INT_EN; 585 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 586 587 ifp->if_drv_flags |= IFF_DRV_RUNNING; 588 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 589 590 sc->emac_link = 0; 591 592 /* Switch to the current media. */ 593 mii = device_get_softc(sc->emac_miibus); 594 mii_mediachg(mii); 595 596 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 597 } 598 599 600 static void 601 emac_start(struct ifnet *ifp) 602 { 603 struct emac_softc *sc; 604 605 sc = ifp->if_softc; 606 EMAC_LOCK(sc); 607 emac_start_locked(ifp); 608 EMAC_UNLOCK(sc); 609 } 610 611 static void 612 emac_start_locked(struct ifnet *ifp) 613 { 614 struct emac_softc *sc; 615 struct mbuf *m, *m0; 616 uint32_t fifo, reg; 617 618 sc = ifp->if_softc; 619 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 620 return; 621 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 622 return; 623 if (sc->emac_link == 0) 624 return; 625 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 626 if (m == NULL) 627 return; 628 629 /* Select channel */ 630 if (sc->emac_fifo_mask & EMAC_TX_FIFO0) 631 fifo = 1; 632 else 633 fifo = 0; 634 sc->emac_fifo_mask |= (1 << fifo); 635 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 636 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 637 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo); 638 639 /* 640 * Emac controller wants 4 byte aligned TX buffers. 641 * We have to copy pretty much all the time. 642 */ 643 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) { 644 m0 = m_defrag(m, M_NOWAIT); 645 if (m0 == NULL) { 646 m_freem(m); 647 m = NULL; 648 return; 649 } 650 m = m0; 651 } 652 /* Write data */ 653 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle, 654 EMAC_TX_IO_DATA, mtod(m, uint32_t *), 655 roundup2(m->m_len, 4) / 4); 656 657 /* Send the data lengh. */ 658 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1; 659 EMAC_WRITE_REG(sc, reg, m->m_len); 660 661 /* Start translate from fifo to phy. */ 662 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1; 663 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1); 664 665 /* Set timeout */ 666 sc->emac_watchdog_timer = 5; 667 668 /* Data have been sent to hardware, it is okay to free the mbuf now. */ 669 BPF_MTAP(ifp, m); 670 m_freem(m); 671 } 672 673 static void 674 emac_stop_locked(struct emac_softc *sc) 675 { 676 struct ifnet *ifp; 677 uint32_t reg_val; 678 679 EMAC_ASSERT_LOCKED(sc); 680 681 ifp = sc->emac_ifp; 682 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 683 sc->emac_link = 0; 684 685 /* Disable all interrupt and clear interrupt status */ 686 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 687 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 688 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 689 690 /* Disable RX/TX */ 691 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 692 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 693 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 694 695 callout_stop(&sc->emac_tick_ch); 696 } 697 698 static void 699 emac_intr(void *arg) 700 { 701 struct emac_softc *sc; 702 struct ifnet *ifp; 703 uint32_t reg_val; 704 705 sc = (struct emac_softc *)arg; 706 EMAC_LOCK(sc); 707 708 /* Disable all interrupts */ 709 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 710 /* Get EMAC interrupt status */ 711 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 712 /* Clear ISR status */ 713 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 714 715 /* Received incoming packet */ 716 if (reg_val & EMAC_INT_STA_RX) 717 emac_rxeof(sc, sc->emac_rx_process_limit); 718 719 /* Transmit Interrupt check */ 720 if (reg_val & EMAC_INT_STA_TX) { 721 emac_txeof(sc, reg_val); 722 ifp = sc->emac_ifp; 723 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 724 emac_start_locked(ifp); 725 } 726 727 /* Re-enable interrupt mask */ 728 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 729 reg_val |= EMAC_INT_EN; 730 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 731 EMAC_UNLOCK(sc); 732 } 733 734 static int 735 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 736 { 737 struct emac_softc *sc; 738 struct mii_data *mii; 739 struct ifreq *ifr; 740 int error = 0; 741 742 sc = ifp->if_softc; 743 ifr = (struct ifreq *)data; 744 745 switch (command) { 746 case SIOCSIFFLAGS: 747 EMAC_LOCK(sc); 748 if (ifp->if_flags & IFF_UP) { 749 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 750 if ((ifp->if_flags ^ sc->emac_if_flags) & 751 (IFF_PROMISC | IFF_ALLMULTI)) 752 emac_set_rx_mode(sc); 753 } else 754 emac_init_locked(sc); 755 } else { 756 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 757 emac_stop_locked(sc); 758 } 759 sc->emac_if_flags = ifp->if_flags; 760 EMAC_UNLOCK(sc); 761 break; 762 case SIOCADDMULTI: 763 case SIOCDELMULTI: 764 EMAC_LOCK(sc); 765 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 766 emac_set_rx_mode(sc); 767 } 768 EMAC_UNLOCK(sc); 769 break; 770 case SIOCGIFMEDIA: 771 case SIOCSIFMEDIA: 772 mii = device_get_softc(sc->emac_miibus); 773 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 774 break; 775 default: 776 error = ether_ioctl(ifp, command, data); 777 break; 778 } 779 return (error); 780 } 781 782 static int 783 emac_probe(device_t dev) 784 { 785 786 if (!ofw_bus_status_okay(dev)) 787 return (ENXIO); 788 789 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac")) 790 return (ENXIO); 791 792 device_set_desc(dev, "A10/A20 EMAC ethernet controller"); 793 return (BUS_PROBE_DEFAULT); 794 } 795 796 static int 797 emac_detach(device_t dev) 798 { 799 struct emac_softc *sc; 800 801 sc = device_get_softc(dev); 802 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 803 if (device_is_attached(dev)) { 804 ether_ifdetach(sc->emac_ifp); 805 EMAC_LOCK(sc); 806 emac_stop_locked(sc); 807 EMAC_UNLOCK(sc); 808 callout_drain(&sc->emac_tick_ch); 809 } 810 811 if (sc->emac_intrhand != NULL) 812 bus_teardown_intr(sc->emac_dev, sc->emac_irq, 813 sc->emac_intrhand); 814 815 if (sc->emac_miibus != NULL) { 816 device_delete_child(sc->emac_dev, sc->emac_miibus); 817 bus_generic_detach(sc->emac_dev); 818 } 819 820 if (sc->emac_clk != NULL) 821 clk_disable(sc->emac_clk); 822 823 if (sc->emac_res != NULL) 824 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res); 825 826 if (sc->emac_irq != NULL) 827 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq); 828 829 if (sc->emac_ifp != NULL) 830 if_free(sc->emac_ifp); 831 832 if (mtx_initialized(&sc->emac_mtx)) 833 mtx_destroy(&sc->emac_mtx); 834 835 return (0); 836 } 837 838 static int 839 emac_shutdown(device_t dev) 840 { 841 842 return (emac_suspend(dev)); 843 } 844 845 static int 846 emac_suspend(device_t dev) 847 { 848 struct emac_softc *sc; 849 struct ifnet *ifp; 850 851 sc = device_get_softc(dev); 852 853 EMAC_LOCK(sc); 854 ifp = sc->emac_ifp; 855 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 856 emac_stop_locked(sc); 857 EMAC_UNLOCK(sc); 858 859 return (0); 860 } 861 862 static int 863 emac_resume(device_t dev) 864 { 865 struct emac_softc *sc; 866 struct ifnet *ifp; 867 868 sc = device_get_softc(dev); 869 870 EMAC_LOCK(sc); 871 ifp = sc->emac_ifp; 872 if ((ifp->if_flags & IFF_UP) != 0) { 873 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 874 emac_init_locked(sc); 875 } 876 EMAC_UNLOCK(sc); 877 878 return (0); 879 } 880 881 static int 882 emac_attach(device_t dev) 883 { 884 struct emac_softc *sc; 885 struct ifnet *ifp; 886 int error, rid; 887 uint8_t eaddr[ETHER_ADDR_LEN]; 888 889 sc = device_get_softc(dev); 890 sc->emac_dev = dev; 891 892 error = 0; 893 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 894 MTX_DEF); 895 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0); 896 897 rid = 0; 898 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 899 RF_ACTIVE); 900 if (sc->emac_res == NULL) { 901 device_printf(dev, "unable to map memory\n"); 902 error = ENXIO; 903 goto fail; 904 } 905 906 sc->emac_tag = rman_get_bustag(sc->emac_res); 907 sc->emac_handle = rman_get_bushandle(sc->emac_res); 908 909 rid = 0; 910 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 911 RF_SHAREABLE | RF_ACTIVE); 912 if (sc->emac_irq == NULL) { 913 device_printf(dev, "cannot allocate IRQ resources.\n"); 914 error = ENXIO; 915 goto fail; 916 } 917 /* Create device sysctl node. */ 918 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 919 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 920 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 921 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I", 922 "max number of Rx events to process"); 923 924 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 925 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 926 "process_limit", &sc->emac_rx_process_limit); 927 if (error == 0) { 928 if (sc->emac_rx_process_limit < EMAC_PROC_MIN || 929 sc->emac_rx_process_limit > EMAC_PROC_MAX) { 930 device_printf(dev, "process_limit value out of range; " 931 "using default: %d\n", EMAC_PROC_DEFAULT); 932 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 933 } 934 } 935 /* Setup EMAC */ 936 error = emac_sys_setup(sc); 937 if (error != 0) 938 goto fail; 939 940 emac_reset(sc); 941 942 ifp = sc->emac_ifp = if_alloc(IFT_ETHER); 943 if (ifp == NULL) { 944 device_printf(dev, "unable to allocate ifp\n"); 945 error = ENOSPC; 946 goto fail; 947 } 948 ifp->if_softc = sc; 949 950 /* Setup MII */ 951 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd, 952 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 953 if (error != 0) { 954 device_printf(dev, "PHY probe failed\n"); 955 goto fail; 956 } 957 958 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 959 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 960 ifp->if_start = emac_start; 961 ifp->if_ioctl = emac_ioctl; 962 ifp->if_init = emac_init; 963 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 964 965 /* Get MAC address */ 966 emac_get_hwaddr(sc, eaddr); 967 ether_ifattach(ifp, eaddr); 968 969 /* VLAN capability setup. */ 970 ifp->if_capabilities |= IFCAP_VLAN_MTU; 971 ifp->if_capenable = ifp->if_capabilities; 972 /* Tell the upper layer we support VLAN over-sized frames. */ 973 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 974 975 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE, 976 NULL, emac_intr, sc, &sc->emac_intrhand); 977 if (error != 0) { 978 device_printf(dev, "could not set up interrupt handler.\n"); 979 ether_ifdetach(ifp); 980 goto fail; 981 } 982 983 fail: 984 if (error != 0) 985 emac_detach(dev); 986 return (error); 987 } 988 989 static boolean_t 990 emac_miibus_iowait(struct emac_softc *sc) 991 { 992 uint32_t timeout; 993 994 for (timeout = 100; timeout != 0; --timeout) { 995 DELAY(100); 996 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0) 997 return (true); 998 } 999 1000 return (false); 1001 } 1002 1003 /* 1004 * The MII bus interface 1005 */ 1006 static int 1007 emac_miibus_readreg(device_t dev, int phy, int reg) 1008 { 1009 struct emac_softc *sc; 1010 int rval; 1011 1012 sc = device_get_softc(dev); 1013 1014 /* Issue phy address and reg */ 1015 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1016 /* Pull up the phy io line */ 1017 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1018 if (!emac_miibus_iowait(sc)) { 1019 device_printf(dev, "timeout waiting for mii read\n"); 1020 return (0); 1021 } 1022 /* Push down the phy io line */ 1023 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1024 /* Read data */ 1025 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD); 1026 1027 return (rval); 1028 } 1029 1030 static int 1031 emac_miibus_writereg(device_t dev, int phy, int reg, int data) 1032 { 1033 struct emac_softc *sc; 1034 1035 sc = device_get_softc(dev); 1036 1037 /* Issue phy address and reg */ 1038 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1039 /* Write data */ 1040 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data); 1041 /* Pull up the phy io line */ 1042 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1043 if (!emac_miibus_iowait(sc)) { 1044 device_printf(dev, "timeout waiting for mii write\n"); 1045 return (0); 1046 } 1047 /* Push down the phy io line */ 1048 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1049 1050 return (0); 1051 } 1052 1053 static void 1054 emac_miibus_statchg(device_t dev) 1055 { 1056 struct emac_softc *sc; 1057 struct mii_data *mii; 1058 struct ifnet *ifp; 1059 uint32_t reg_val; 1060 1061 sc = device_get_softc(dev); 1062 1063 mii = device_get_softc(sc->emac_miibus); 1064 ifp = sc->emac_ifp; 1065 if (mii == NULL || ifp == NULL || 1066 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1067 return; 1068 1069 sc->emac_link = 0; 1070 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1071 (IFM_ACTIVE | IFM_AVALID)) { 1072 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1073 case IFM_10_T: 1074 case IFM_100_TX: 1075 sc->emac_link = 1; 1076 break; 1077 default: 1078 break; 1079 } 1080 } 1081 /* Program MACs with resolved speed/duplex. */ 1082 if (sc->emac_link != 0) { 1083 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT); 1084 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1085 reg_val &= ~EMAC_MAC_IPGT_HD; 1086 reg_val |= EMAC_MAC_IPGT_FD; 1087 } else { 1088 reg_val &= ~EMAC_MAC_IPGT_FD; 1089 reg_val |= EMAC_MAC_IPGT_HD; 1090 } 1091 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val); 1092 /* Enable RX/TX */ 1093 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1094 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN; 1095 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1096 } else { 1097 /* Disable RX/TX */ 1098 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1099 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 1100 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1101 } 1102 } 1103 1104 static int 1105 emac_ifmedia_upd(struct ifnet *ifp) 1106 { 1107 struct emac_softc *sc; 1108 struct mii_data *mii; 1109 struct mii_softc *miisc; 1110 int error; 1111 1112 sc = ifp->if_softc; 1113 mii = device_get_softc(sc->emac_miibus); 1114 EMAC_LOCK(sc); 1115 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1116 PHY_RESET(miisc); 1117 error = mii_mediachg(mii); 1118 EMAC_UNLOCK(sc); 1119 1120 return (error); 1121 } 1122 1123 static void 1124 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1125 { 1126 struct emac_softc *sc; 1127 struct mii_data *mii; 1128 1129 sc = ifp->if_softc; 1130 mii = device_get_softc(sc->emac_miibus); 1131 1132 EMAC_LOCK(sc); 1133 mii_pollstat(mii); 1134 ifmr->ifm_active = mii->mii_media_active; 1135 ifmr->ifm_status = mii->mii_media_status; 1136 EMAC_UNLOCK(sc); 1137 } 1138 1139 static device_method_t emac_methods[] = { 1140 /* Device interface */ 1141 DEVMETHOD(device_probe, emac_probe), 1142 DEVMETHOD(device_attach, emac_attach), 1143 DEVMETHOD(device_detach, emac_detach), 1144 DEVMETHOD(device_shutdown, emac_shutdown), 1145 DEVMETHOD(device_suspend, emac_suspend), 1146 DEVMETHOD(device_resume, emac_resume), 1147 1148 /* bus interface, for miibus */ 1149 DEVMETHOD(bus_print_child, bus_generic_print_child), 1150 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1151 1152 /* MII interface */ 1153 DEVMETHOD(miibus_readreg, emac_miibus_readreg), 1154 DEVMETHOD(miibus_writereg, emac_miibus_writereg), 1155 DEVMETHOD(miibus_statchg, emac_miibus_statchg), 1156 1157 DEVMETHOD_END 1158 }; 1159 1160 static driver_t emac_driver = { 1161 "emac", 1162 emac_methods, 1163 sizeof(struct emac_softc) 1164 }; 1165 1166 static devclass_t emac_devclass; 1167 1168 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0); 1169 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0); 1170 MODULE_DEPEND(emac, miibus, 1, 1, 1); 1171 MODULE_DEPEND(emac, ether, 1, 1, 1); 1172 1173 static int 1174 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 1175 { 1176 int error, value; 1177 1178 if (arg1 == NULL) 1179 return (EINVAL); 1180 value = *(int *)arg1; 1181 error = sysctl_handle_int(oidp, &value, 0, req); 1182 if (error || req->newptr == NULL) 1183 return (error); 1184 if (value < low || value > high) 1185 return (EINVAL); 1186 *(int *)arg1 = value; 1187 1188 return (0); 1189 } 1190 1191 static int 1192 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS) 1193 { 1194 1195 return (sysctl_int_range(oidp, arg1, arg2, req, 1196 EMAC_PROC_MIN, EMAC_PROC_MAX)); 1197 } 1198