1 /*- 2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* A10/A20 EMAC driver */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/lock.h> 40 #include <sys/mbuf.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/gpio.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/intr.h> 51 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_arp.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_mib.h> 59 #include <net/ethernet.h> 60 #include <net/if_vlan_var.h> 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #endif 68 69 #include <net/bpf.h> 70 #include <net/bpfdesc.h> 71 72 #include <dev/fdt/fdt_common.h> 73 #include <dev/ofw/ofw_bus.h> 74 #include <dev/ofw/ofw_bus_subr.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <arm/allwinner/if_emacreg.h> 80 81 #include "miibus_if.h" 82 83 #include "gpio_if.h" 84 85 #include "a10_clk.h" 86 #include "a10_sramc.h" 87 #include "a10_gpio.h" 88 89 struct emac_softc { 90 struct ifnet *emac_ifp; 91 device_t emac_dev; 92 device_t emac_miibus; 93 bus_space_handle_t emac_handle; 94 bus_space_tag_t emac_tag; 95 struct resource *emac_res; 96 struct resource *emac_irq; 97 void *emac_intrhand; 98 int emac_if_flags; 99 struct mtx emac_mtx; 100 struct callout emac_tick_ch; 101 int emac_watchdog_timer; 102 int emac_rx_process_limit; 103 int emac_link; 104 uint32_t emac_fifo_mask; 105 }; 106 107 static int emac_probe(device_t); 108 static int emac_attach(device_t); 109 static int emac_detach(device_t); 110 static int emac_shutdown(device_t); 111 static int emac_suspend(device_t); 112 static int emac_resume(device_t); 113 114 static void emac_sys_setup(void); 115 static void emac_reset(struct emac_softc *); 116 117 static void emac_init_locked(struct emac_softc *); 118 static void emac_start_locked(struct ifnet *); 119 static void emac_init(void *); 120 static void emac_stop_locked(struct emac_softc *); 121 static void emac_intr(void *); 122 static int emac_ioctl(struct ifnet *, u_long, caddr_t); 123 124 static void emac_rxeof(struct emac_softc *, int); 125 static void emac_txeof(struct emac_softc *, uint32_t); 126 127 static int emac_miibus_readreg(device_t, int, int); 128 static int emac_miibus_writereg(device_t, int, int, int); 129 static void emac_miibus_statchg(device_t); 130 131 static int emac_ifmedia_upd(struct ifnet *); 132 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *); 133 134 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 135 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS); 136 137 #define EMAC_READ_REG(sc, reg) \ 138 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg) 139 #define EMAC_WRITE_REG(sc, reg, val) \ 140 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val) 141 142 static void 143 emac_sys_setup(void) 144 { 145 int i; 146 147 a10_clk_emac_activate(); 148 149 /* 150 * Configure pin mux settings for MII. 151 * Pins PA0 from PA17. 152 */ 153 for (i = 0; i <= 17; i++) 154 a10_emac_gpio_config(i); 155 /* Map sram */ 156 a10_map_to_emac(); 157 } 158 159 static void 160 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr) 161 { 162 uint32_t val0, val1, rnd; 163 164 /* 165 * Try to get MAC address from running hardware. 166 * If there is something non-zero there just use it. 167 * 168 * Otherwise set the address to a convenient locally assigned address, 169 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 170 * assigned bit set, and the broadcast/multicast bit clear. 171 */ 172 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0); 173 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1); 174 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) { 175 hwaddr[0] = (val1 >> 16) & 0xff; 176 hwaddr[1] = (val1 >> 8) & 0xff; 177 hwaddr[2] = (val1 >> 0) & 0xff; 178 hwaddr[3] = (val0 >> 16) & 0xff; 179 hwaddr[4] = (val0 >> 8) & 0xff; 180 hwaddr[5] = (val0 >> 0) & 0xff; 181 } else { 182 rnd = arc4random() & 0x00ffffff; 183 hwaddr[0] = 'b'; 184 hwaddr[1] = 's'; 185 hwaddr[2] = 'd'; 186 hwaddr[3] = (rnd >> 16) & 0xff; 187 hwaddr[4] = (rnd >> 8) & 0xff; 188 hwaddr[5] = (rnd >> 0) & 0xff; 189 } 190 if (bootverbose) 191 printf("MAC address: %s\n", ether_sprintf(hwaddr)); 192 } 193 194 static void 195 emac_set_rx_mode(struct emac_softc *sc) 196 { 197 struct ifnet *ifp; 198 struct ifmultiaddr *ifma; 199 uint32_t h, hashes[2]; 200 uint32_t rcr = 0; 201 202 EMAC_ASSERT_LOCKED(sc); 203 204 ifp = sc->emac_ifp; 205 206 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); 207 208 /* Unicast packet and DA filtering */ 209 rcr |= EMAC_RX_UCAD; 210 rcr |= EMAC_RX_DAF; 211 212 hashes[0] = 0; 213 hashes[1] = 0; 214 if (ifp->if_flags & IFF_ALLMULTI) { 215 hashes[0] = 0xffffffff; 216 hashes[1] = 0xffffffff; 217 } else { 218 if_maddr_rlock(ifp); 219 TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) { 220 if (ifma->ifma_addr->sa_family != AF_LINK) 221 continue; 222 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 223 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 224 hashes[h >> 5] |= 1 << (h & 0x1f); 225 } 226 if_maddr_runlock(ifp); 227 } 228 rcr |= EMAC_RX_MCO; 229 rcr |= EMAC_RX_MHF; 230 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]); 231 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]); 232 233 if (ifp->if_flags & IFF_BROADCAST) { 234 rcr |= EMAC_RX_BCO; 235 rcr |= EMAC_RX_MCO; 236 } 237 238 if (ifp->if_flags & IFF_PROMISC) 239 rcr |= EMAC_RX_PA; 240 else 241 rcr |= EMAC_RX_UCAD; 242 243 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr); 244 } 245 246 static void 247 emac_reset(struct emac_softc *sc) 248 { 249 250 EMAC_WRITE_REG(sc, EMAC_CTL, 0); 251 DELAY(200); 252 EMAC_WRITE_REG(sc, EMAC_CTL, 1); 253 DELAY(200); 254 } 255 256 static void 257 emac_drain_rxfifo(struct emac_softc *sc) 258 { 259 uint32_t data; 260 261 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0) 262 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 263 } 264 265 static void 266 emac_txeof(struct emac_softc *sc, uint32_t status) 267 { 268 struct ifnet *ifp; 269 270 EMAC_ASSERT_LOCKED(sc); 271 272 ifp = sc->emac_ifp; 273 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1); 274 sc->emac_fifo_mask &= ~status; 275 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 276 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2); 277 else 278 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 279 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 280 281 /* Unarm watchdog timer if no TX */ 282 sc->emac_watchdog_timer = 0; 283 } 284 285 static void 286 emac_rxeof(struct emac_softc *sc, int count) 287 { 288 struct ifnet *ifp; 289 struct mbuf *m, *m0; 290 uint32_t reg_val, rxcount; 291 int16_t len; 292 uint16_t status; 293 int i; 294 295 ifp = sc->emac_ifp; 296 for (; count > 0 && 297 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) { 298 /* 299 * Race warning: The first packet might arrive with 300 * the interrupts disabled, but the second will fix 301 */ 302 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 303 if (!rxcount) { 304 /* Had one stuck? */ 305 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 306 if (!rxcount) 307 return; 308 } 309 /* Check packet header */ 310 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 311 if (reg_val != EMAC_PACKET_HEADER) { 312 /* Packet header is wrong */ 313 if (bootverbose) 314 if_printf(ifp, "wrong packet header\n"); 315 /* Disable RX */ 316 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 317 reg_val &= ~EMAC_CTL_RX_EN; 318 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 319 320 /* Flush RX FIFO */ 321 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 322 reg_val |= EMAC_RX_FLUSH_FIFO; 323 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 324 for (i = 100; i > 0; i--) { 325 DELAY(100); 326 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) & 327 EMAC_RX_FLUSH_FIFO) == 0) 328 break; 329 } 330 if (i == 0) { 331 device_printf(sc->emac_dev, 332 "flush FIFO timeout\n"); 333 /* Reinitialize controller */ 334 emac_init_locked(sc); 335 return; 336 } 337 /* Enable RX */ 338 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 339 reg_val |= EMAC_CTL_RX_EN; 340 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 341 342 return; 343 } 344 345 /* Get packet size and status */ 346 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 347 len = reg_val & 0xffff; 348 status = (reg_val >> 16) & 0xffff; 349 350 if (len < 64 || (status & EMAC_PKT_OK) == 0) { 351 if (bootverbose) 352 if_printf(ifp, 353 "bad packet: len = %i status = %i\n", 354 len, status); 355 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 356 emac_drain_rxfifo(sc); 357 continue; 358 } 359 #if 0 360 if (status & (EMAC_CRCERR | EMAC_LENERR)) { 361 good_packet = 0; 362 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 363 if (status & EMAC_CRCERR) 364 if_printf(ifp, "crc error\n"); 365 if (status & EMAC_LENERR) 366 if_printf(ifp, "length error\n"); 367 } 368 #endif 369 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 370 if (m == NULL) { 371 emac_drain_rxfifo(sc); 372 return; 373 } 374 m->m_len = m->m_pkthdr.len = MCLBYTES; 375 376 /* Copy entire frame to mbuf first. */ 377 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle, 378 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4); 379 380 m->m_pkthdr.rcvif = ifp; 381 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN; 382 383 /* 384 * Emac controller needs strict aligment, so to avoid 385 * copying over an entire frame to align, we allocate 386 * a new mbuf and copy ethernet header + IP header to 387 * the new mbuf. The new mbuf is prepended into the 388 * existing mbuf chain. 389 */ 390 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) { 391 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 392 m->m_data += ETHER_HDR_LEN; 393 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) && 394 m->m_len > (MHLEN - ETHER_HDR_LEN)) { 395 MGETHDR(m0, M_NOWAIT, MT_DATA); 396 if (m0 != NULL) { 397 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen; 398 bcopy(m->m_data, m0->m_data, len); 399 m->m_data += len; 400 m->m_len -= len; 401 m0->m_len = len; 402 M_MOVE_PKTHDR(m0, m); 403 m0->m_next = m; 404 m = m0; 405 } else { 406 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 407 m_freem(m); 408 m = NULL; 409 continue; 410 } 411 } else if (m->m_len > EMAC_MAC_MAXF) { 412 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 413 m_freem(m); 414 m = NULL; 415 continue; 416 } 417 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 418 EMAC_UNLOCK(sc); 419 (*ifp->if_input)(ifp, m); 420 EMAC_LOCK(sc); 421 } 422 } 423 424 static void 425 emac_watchdog(struct emac_softc *sc) 426 { 427 struct ifnet *ifp; 428 429 EMAC_ASSERT_LOCKED(sc); 430 431 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer) 432 return; 433 434 ifp = sc->emac_ifp; 435 436 if (sc->emac_link == 0) { 437 if (bootverbose) 438 if_printf(sc->emac_ifp, "watchdog timeout " 439 "(missed link)\n"); 440 } else 441 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n"); 442 443 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 444 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 445 emac_init_locked(sc); 446 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 447 emac_start_locked(ifp); 448 } 449 450 static void 451 emac_tick(void *arg) 452 { 453 struct emac_softc *sc; 454 struct mii_data *mii; 455 456 sc = (struct emac_softc *)arg; 457 mii = device_get_softc(sc->emac_miibus); 458 mii_tick(mii); 459 460 emac_watchdog(sc); 461 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 462 } 463 464 static void 465 emac_init(void *xcs) 466 { 467 struct emac_softc *sc; 468 469 sc = (struct emac_softc *)xcs; 470 EMAC_LOCK(sc); 471 emac_init_locked(sc); 472 EMAC_UNLOCK(sc); 473 } 474 475 static void 476 emac_init_locked(struct emac_softc *sc) 477 { 478 struct ifnet *ifp; 479 struct mii_data *mii; 480 uint32_t reg_val; 481 uint8_t *eaddr; 482 483 EMAC_ASSERT_LOCKED(sc); 484 485 ifp = sc->emac_ifp; 486 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 487 return; 488 489 /* Flush RX FIFO */ 490 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 491 reg_val |= EMAC_RX_FLUSH_FIFO; 492 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 493 DELAY(1); 494 495 /* Soft reset MAC */ 496 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 497 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); 498 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 499 500 /* Set MII clock */ 501 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); 502 reg_val &= (~(0xf << 2)); 503 reg_val |= (0xd << 2); 504 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); 505 506 /* Clear RX counter */ 507 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); 508 509 /* Disable all interrupt and clear interrupt status */ 510 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 511 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 512 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 513 DELAY(1); 514 515 /* Set up TX */ 516 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); 517 reg_val |= EMAC_TX_AB_M; 518 reg_val &= EMAC_TX_TM; 519 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); 520 521 /* Set up RX */ 522 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 523 reg_val |= EMAC_RX_SETUP; 524 reg_val &= EMAC_RX_TM; 525 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 526 527 /* Set up MAC CTL0. */ 528 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 529 reg_val |= EMAC_MAC_CTL0_SETUP; 530 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 531 532 /* Set up MAC CTL1. */ 533 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1); 534 reg_val |= EMAC_MAC_CTL1_SETUP; 535 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val); 536 537 /* Set up IPGT */ 538 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD); 539 540 /* Set up IPGR */ 541 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 | 542 (EMAC_MAC_NBTB_IPG1 << 8)); 543 544 /* Set up Collison window */ 545 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8)); 546 547 /* Set up Max Frame Length */ 548 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL); 549 550 /* Setup ethernet address */ 551 eaddr = IF_LLADDR(ifp); 552 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 | 553 eaddr[1] << 8 | eaddr[2]); 554 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 | 555 eaddr[4] << 8 | eaddr[5]); 556 557 /* Setup rx filter */ 558 emac_set_rx_mode(sc); 559 560 /* Enable RX/TX0/RX Hlevel interrupt */ 561 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 562 reg_val |= EMAC_INT_EN; 563 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 564 565 ifp->if_drv_flags |= IFF_DRV_RUNNING; 566 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 567 568 sc->emac_link = 0; 569 570 /* Switch to the current media. */ 571 mii = device_get_softc(sc->emac_miibus); 572 mii_mediachg(mii); 573 574 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 575 } 576 577 578 static void 579 emac_start(struct ifnet *ifp) 580 { 581 struct emac_softc *sc; 582 583 sc = ifp->if_softc; 584 EMAC_LOCK(sc); 585 emac_start_locked(ifp); 586 EMAC_UNLOCK(sc); 587 } 588 589 static void 590 emac_start_locked(struct ifnet *ifp) 591 { 592 struct emac_softc *sc; 593 struct mbuf *m, *m0; 594 uint32_t fifo, reg; 595 596 sc = ifp->if_softc; 597 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 598 return; 599 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 600 return; 601 if (sc->emac_link == 0) 602 return; 603 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 604 if (m == NULL) 605 return; 606 607 /* Select channel */ 608 if (sc->emac_fifo_mask & EMAC_TX_FIFO0) 609 fifo = 1; 610 else 611 fifo = 0; 612 sc->emac_fifo_mask |= (1 << fifo); 613 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 614 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 615 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo); 616 617 /* 618 * Emac controller wants 4 byte aligned TX buffers. 619 * We have to copy pretty much all the time. 620 */ 621 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) { 622 m0 = m_defrag(m, M_NOWAIT); 623 if (m0 == NULL) { 624 m_freem(m); 625 m = NULL; 626 return; 627 } 628 m = m0; 629 } 630 /* Write data */ 631 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle, 632 EMAC_TX_IO_DATA, mtod(m, uint32_t *), 633 roundup2(m->m_len, 4) / 4); 634 635 /* Send the data lengh. */ 636 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1; 637 EMAC_WRITE_REG(sc, reg, m->m_len); 638 639 /* Start translate from fifo to phy. */ 640 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1; 641 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1); 642 643 /* Set timeout */ 644 sc->emac_watchdog_timer = 5; 645 646 /* Data have been sent to hardware, it is okay to free the mbuf now. */ 647 BPF_MTAP(ifp, m); 648 m_freem(m); 649 } 650 651 static void 652 emac_stop_locked(struct emac_softc *sc) 653 { 654 struct ifnet *ifp; 655 uint32_t reg_val; 656 657 EMAC_ASSERT_LOCKED(sc); 658 659 ifp = sc->emac_ifp; 660 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 661 sc->emac_link = 0; 662 663 /* Disable all interrupt and clear interrupt status */ 664 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 665 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 666 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 667 668 /* Disable RX/TX */ 669 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 670 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 671 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 672 673 callout_stop(&sc->emac_tick_ch); 674 } 675 676 static void 677 emac_intr(void *arg) 678 { 679 struct emac_softc *sc; 680 struct ifnet *ifp; 681 uint32_t reg_val; 682 683 sc = (struct emac_softc *)arg; 684 EMAC_LOCK(sc); 685 686 /* Disable all interrupts */ 687 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 688 /* Get EMAC interrupt status */ 689 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 690 /* Clear ISR status */ 691 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 692 693 /* Received incoming packet */ 694 if (reg_val & EMAC_INT_STA_RX) 695 emac_rxeof(sc, sc->emac_rx_process_limit); 696 697 /* Transmit Interrupt check */ 698 if (reg_val & EMAC_INT_STA_TX) { 699 emac_txeof(sc, reg_val); 700 ifp = sc->emac_ifp; 701 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 702 emac_start_locked(ifp); 703 } 704 705 /* Re-enable interrupt mask */ 706 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 707 reg_val |= EMAC_INT_EN; 708 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 709 EMAC_UNLOCK(sc); 710 } 711 712 static int 713 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 714 { 715 struct emac_softc *sc; 716 struct mii_data *mii; 717 struct ifreq *ifr; 718 int error = 0; 719 720 sc = ifp->if_softc; 721 ifr = (struct ifreq *)data; 722 723 switch (command) { 724 case SIOCSIFFLAGS: 725 EMAC_LOCK(sc); 726 if (ifp->if_flags & IFF_UP) { 727 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 728 if ((ifp->if_flags ^ sc->emac_if_flags) & 729 (IFF_PROMISC | IFF_ALLMULTI)) 730 emac_set_rx_mode(sc); 731 } else 732 emac_init_locked(sc); 733 } else { 734 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 735 emac_stop_locked(sc); 736 } 737 sc->emac_if_flags = ifp->if_flags; 738 EMAC_UNLOCK(sc); 739 break; 740 case SIOCADDMULTI: 741 case SIOCDELMULTI: 742 EMAC_LOCK(sc); 743 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 744 emac_set_rx_mode(sc); 745 } 746 EMAC_UNLOCK(sc); 747 break; 748 case SIOCGIFMEDIA: 749 case SIOCSIFMEDIA: 750 mii = device_get_softc(sc->emac_miibus); 751 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 752 break; 753 default: 754 error = ether_ioctl(ifp, command, data); 755 break; 756 } 757 return (error); 758 } 759 760 static int 761 emac_probe(device_t dev) 762 { 763 764 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-emac")) 765 return (ENXIO); 766 767 device_set_desc(dev, "A10/A20 EMAC ethernet controller"); 768 return (BUS_PROBE_DEFAULT); 769 } 770 771 static int 772 emac_detach(device_t dev) 773 { 774 struct emac_softc *sc; 775 776 sc = device_get_softc(dev); 777 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 778 if (device_is_attached(dev)) { 779 ether_ifdetach(sc->emac_ifp); 780 EMAC_LOCK(sc); 781 emac_stop_locked(sc); 782 EMAC_UNLOCK(sc); 783 callout_drain(&sc->emac_tick_ch); 784 } 785 786 if (sc->emac_intrhand != NULL) 787 bus_teardown_intr(sc->emac_dev, sc->emac_irq, 788 sc->emac_intrhand); 789 790 if (sc->emac_miibus != NULL) { 791 device_delete_child(sc->emac_dev, sc->emac_miibus); 792 bus_generic_detach(sc->emac_dev); 793 } 794 795 if (sc->emac_res != NULL) 796 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res); 797 798 if (sc->emac_irq != NULL) 799 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq); 800 801 if (sc->emac_ifp != NULL) 802 if_free(sc->emac_ifp); 803 804 if (mtx_initialized(&sc->emac_mtx)) 805 mtx_destroy(&sc->emac_mtx); 806 807 return (0); 808 } 809 810 static int 811 emac_shutdown(device_t dev) 812 { 813 814 return (emac_suspend(dev)); 815 } 816 817 static int 818 emac_suspend(device_t dev) 819 { 820 struct emac_softc *sc; 821 struct ifnet *ifp; 822 823 sc = device_get_softc(dev); 824 825 EMAC_LOCK(sc); 826 ifp = sc->emac_ifp; 827 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 828 emac_stop_locked(sc); 829 EMAC_UNLOCK(sc); 830 831 return (0); 832 } 833 834 static int 835 emac_resume(device_t dev) 836 { 837 struct emac_softc *sc; 838 struct ifnet *ifp; 839 840 sc = device_get_softc(dev); 841 842 EMAC_LOCK(sc); 843 ifp = sc->emac_ifp; 844 if ((ifp->if_flags & IFF_UP) != 0) { 845 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 846 emac_init_locked(sc); 847 } 848 EMAC_UNLOCK(sc); 849 850 return (0); 851 } 852 853 static int 854 emac_attach(device_t dev) 855 { 856 struct emac_softc *sc; 857 struct ifnet *ifp; 858 int error, rid; 859 uint8_t eaddr[ETHER_ADDR_LEN]; 860 861 sc = device_get_softc(dev); 862 sc->emac_dev = dev; 863 864 error = 0; 865 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 866 MTX_DEF); 867 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0); 868 869 rid = 0; 870 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 871 RF_ACTIVE); 872 if (sc->emac_res == NULL) { 873 device_printf(dev, "unable to map memory\n"); 874 error = ENXIO; 875 goto fail; 876 } 877 878 sc->emac_tag = rman_get_bustag(sc->emac_res); 879 sc->emac_handle = rman_get_bushandle(sc->emac_res); 880 881 rid = 0; 882 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 883 RF_SHAREABLE | RF_ACTIVE); 884 if (sc->emac_irq == NULL) { 885 device_printf(dev, "cannot allocate IRQ resources.\n"); 886 error = ENXIO; 887 goto fail; 888 } 889 /* Create device sysctl node. */ 890 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 891 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 892 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 893 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I", 894 "max number of Rx events to process"); 895 896 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 897 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 898 "process_limit", &sc->emac_rx_process_limit); 899 if (error == 0) { 900 if (sc->emac_rx_process_limit < EMAC_PROC_MIN || 901 sc->emac_rx_process_limit > EMAC_PROC_MAX) { 902 device_printf(dev, "process_limit value out of range; " 903 "using default: %d\n", EMAC_PROC_DEFAULT); 904 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 905 } 906 } 907 /* Setup EMAC */ 908 emac_sys_setup(); 909 emac_reset(sc); 910 911 ifp = sc->emac_ifp = if_alloc(IFT_ETHER); 912 if (ifp == NULL) { 913 device_printf(dev, "unable to allocate ifp\n"); 914 error = ENOSPC; 915 goto fail; 916 } 917 ifp->if_softc = sc; 918 919 /* Setup MII */ 920 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd, 921 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 922 if (error != 0) { 923 device_printf(dev, "PHY probe failed\n"); 924 goto fail; 925 } 926 927 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 928 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 929 ifp->if_start = emac_start; 930 ifp->if_ioctl = emac_ioctl; 931 ifp->if_init = emac_init; 932 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 933 934 /* Get MAC address */ 935 emac_get_hwaddr(sc, eaddr); 936 ether_ifattach(ifp, eaddr); 937 938 /* VLAN capability setup. */ 939 ifp->if_capabilities |= IFCAP_VLAN_MTU; 940 ifp->if_capenable = ifp->if_capabilities; 941 /* Tell the upper layer we support VLAN over-sized frames. */ 942 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 943 944 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE, 945 NULL, emac_intr, sc, &sc->emac_intrhand); 946 if (error != 0) { 947 device_printf(dev, "could not set up interrupt handler.\n"); 948 ether_ifdetach(ifp); 949 goto fail; 950 } 951 952 fail: 953 if (error != 0) 954 emac_detach(dev); 955 return (error); 956 } 957 958 static boolean_t 959 emac_miibus_iowait(struct emac_softc *sc) 960 { 961 uint32_t timeout; 962 963 for (timeout = 100; timeout != 0; --timeout) { 964 DELAY(100); 965 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0) 966 return (true); 967 } 968 969 return (false); 970 } 971 972 /* 973 * The MII bus interface 974 */ 975 static int 976 emac_miibus_readreg(device_t dev, int phy, int reg) 977 { 978 struct emac_softc *sc; 979 int rval; 980 981 sc = device_get_softc(dev); 982 983 /* Issue phy address and reg */ 984 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 985 /* Pull up the phy io line */ 986 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 987 if (!emac_miibus_iowait(sc)) { 988 device_printf(dev, "timeout waiting for mii read\n"); 989 return (0); 990 } 991 /* Push down the phy io line */ 992 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 993 /* Read data */ 994 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD); 995 996 return (rval); 997 } 998 999 static int 1000 emac_miibus_writereg(device_t dev, int phy, int reg, int data) 1001 { 1002 struct emac_softc *sc; 1003 1004 sc = device_get_softc(dev); 1005 1006 /* Issue phy address and reg */ 1007 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1008 /* Write data */ 1009 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data); 1010 /* Pull up the phy io line */ 1011 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1012 if (!emac_miibus_iowait(sc)) { 1013 device_printf(dev, "timeout waiting for mii write\n"); 1014 return (0); 1015 } 1016 /* Push down the phy io line */ 1017 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1018 1019 return (0); 1020 } 1021 1022 static void 1023 emac_miibus_statchg(device_t dev) 1024 { 1025 struct emac_softc *sc; 1026 struct mii_data *mii; 1027 struct ifnet *ifp; 1028 uint32_t reg_val; 1029 1030 sc = device_get_softc(dev); 1031 1032 mii = device_get_softc(sc->emac_miibus); 1033 ifp = sc->emac_ifp; 1034 if (mii == NULL || ifp == NULL || 1035 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1036 return; 1037 1038 sc->emac_link = 0; 1039 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1040 (IFM_ACTIVE | IFM_AVALID)) { 1041 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1042 case IFM_10_T: 1043 case IFM_100_TX: 1044 sc->emac_link = 1; 1045 break; 1046 default: 1047 break; 1048 } 1049 } 1050 /* Program MACs with resolved speed/duplex. */ 1051 if (sc->emac_link != 0) { 1052 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT); 1053 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1054 reg_val &= ~EMAC_MAC_IPGT_HD; 1055 reg_val |= EMAC_MAC_IPGT_FD; 1056 } else { 1057 reg_val &= ~EMAC_MAC_IPGT_FD; 1058 reg_val |= EMAC_MAC_IPGT_HD; 1059 } 1060 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val); 1061 /* Enable RX/TX */ 1062 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1063 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN; 1064 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1065 } else { 1066 /* Disable RX/TX */ 1067 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1068 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 1069 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1070 } 1071 } 1072 1073 static int 1074 emac_ifmedia_upd(struct ifnet *ifp) 1075 { 1076 struct emac_softc *sc; 1077 struct mii_data *mii; 1078 struct mii_softc *miisc; 1079 int error; 1080 1081 sc = ifp->if_softc; 1082 mii = device_get_softc(sc->emac_miibus); 1083 EMAC_LOCK(sc); 1084 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1085 PHY_RESET(miisc); 1086 error = mii_mediachg(mii); 1087 EMAC_UNLOCK(sc); 1088 1089 return (error); 1090 } 1091 1092 static void 1093 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1094 { 1095 struct emac_softc *sc; 1096 struct mii_data *mii; 1097 1098 sc = ifp->if_softc; 1099 mii = device_get_softc(sc->emac_miibus); 1100 1101 EMAC_LOCK(sc); 1102 mii_pollstat(mii); 1103 ifmr->ifm_active = mii->mii_media_active; 1104 ifmr->ifm_status = mii->mii_media_status; 1105 EMAC_UNLOCK(sc); 1106 } 1107 1108 static device_method_t emac_methods[] = { 1109 /* Device interface */ 1110 DEVMETHOD(device_probe, emac_probe), 1111 DEVMETHOD(device_attach, emac_attach), 1112 DEVMETHOD(device_detach, emac_detach), 1113 DEVMETHOD(device_shutdown, emac_shutdown), 1114 DEVMETHOD(device_suspend, emac_suspend), 1115 DEVMETHOD(device_resume, emac_resume), 1116 1117 /* bus interface, for miibus */ 1118 DEVMETHOD(bus_print_child, bus_generic_print_child), 1119 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1120 1121 /* MII interface */ 1122 DEVMETHOD(miibus_readreg, emac_miibus_readreg), 1123 DEVMETHOD(miibus_writereg, emac_miibus_writereg), 1124 DEVMETHOD(miibus_statchg, emac_miibus_statchg), 1125 1126 DEVMETHOD_END 1127 }; 1128 1129 static driver_t emac_driver = { 1130 "emac", 1131 emac_methods, 1132 sizeof(struct emac_softc) 1133 }; 1134 1135 static devclass_t emac_devclass; 1136 1137 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0); 1138 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0); 1139 MODULE_DEPEND(emac, miibus, 1, 1, 1); 1140 MODULE_DEPEND(emac, ether, 1, 1, 1); 1141 1142 static int 1143 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 1144 { 1145 int error, value; 1146 1147 if (arg1 == NULL) 1148 return (EINVAL); 1149 value = *(int *)arg1; 1150 error = sysctl_handle_int(oidp, &value, 0, req); 1151 if (error || req->newptr == NULL) 1152 return (error); 1153 if (value < low || value > high) 1154 return (EINVAL); 1155 *(int *)arg1 = value; 1156 1157 return (0); 1158 } 1159 1160 static int 1161 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS) 1162 { 1163 1164 return (sysctl_int_range(oidp, arg1, arg2, req, 1165 EMAC_PROC_MIN, EMAC_PROC_MAX)); 1166 } 1167