1 /*- 2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* A10/A20 EMAC driver */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/lock.h> 40 #include <sys/mbuf.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/gpio.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/intr.h> 51 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_arp.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_mib.h> 59 #include <net/ethernet.h> 60 #include <net/if_vlan_var.h> 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #endif 68 69 #include <net/bpf.h> 70 #include <net/bpfdesc.h> 71 72 #include <dev/fdt/fdt_common.h> 73 #include <dev/ofw/ofw_bus.h> 74 #include <dev/ofw/ofw_bus_subr.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <arm/allwinner/if_emacreg.h> 80 81 #include "miibus_if.h" 82 83 #include "gpio_if.h" 84 85 #include "a10_clk.h" 86 #include "a10_sramc.h" 87 #include "a10_gpio.h" 88 89 struct emac_softc { 90 struct ifnet *emac_ifp; 91 device_t emac_dev; 92 device_t emac_miibus; 93 bus_space_handle_t emac_handle; 94 bus_space_tag_t emac_tag; 95 struct resource *emac_res; 96 struct resource *emac_irq; 97 void *emac_intrhand; 98 int emac_if_flags; 99 struct mtx emac_mtx; 100 struct callout emac_tick_ch; 101 int emac_watchdog_timer; 102 int emac_rx_process_limit; 103 int emac_link; 104 uint32_t emac_fifo_mask; 105 }; 106 107 static int emac_probe(device_t); 108 static int emac_attach(device_t); 109 static int emac_detach(device_t); 110 static int emac_shutdown(device_t); 111 static int emac_suspend(device_t); 112 static int emac_resume(device_t); 113 114 static void emac_sys_setup(void); 115 static void emac_reset(struct emac_softc *); 116 117 static void emac_init_locked(struct emac_softc *); 118 static void emac_start_locked(struct ifnet *); 119 static void emac_init(void *); 120 static void emac_stop_locked(struct emac_softc *); 121 static void emac_intr(void *); 122 static int emac_ioctl(struct ifnet *, u_long, caddr_t); 123 124 static void emac_rxeof(struct emac_softc *, int); 125 static void emac_txeof(struct emac_softc *, uint32_t); 126 127 static int emac_miibus_readreg(device_t, int, int); 128 static int emac_miibus_writereg(device_t, int, int, int); 129 static void emac_miibus_statchg(device_t); 130 131 static int emac_ifmedia_upd(struct ifnet *); 132 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *); 133 134 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 135 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS); 136 137 #define EMAC_READ_REG(sc, reg) \ 138 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg) 139 #define EMAC_WRITE_REG(sc, reg, val) \ 140 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val) 141 142 static void 143 emac_sys_setup(void) 144 { 145 146 /* Activate EMAC clock. */ 147 a10_clk_emac_activate(); 148 /* Set the pin mux to EMAC (mii). */ 149 a10_gpio_ethernet_activate(A10_GPIO_FUNC_MII); 150 /* Map sram. */ 151 a10_map_to_emac(); 152 } 153 154 static void 155 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr) 156 { 157 uint32_t val0, val1, rnd; 158 159 /* 160 * Try to get MAC address from running hardware. 161 * If there is something non-zero there just use it. 162 * 163 * Otherwise set the address to a convenient locally assigned address, 164 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 165 * assigned bit set, and the broadcast/multicast bit clear. 166 */ 167 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0); 168 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1); 169 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) { 170 hwaddr[0] = (val1 >> 16) & 0xff; 171 hwaddr[1] = (val1 >> 8) & 0xff; 172 hwaddr[2] = (val1 >> 0) & 0xff; 173 hwaddr[3] = (val0 >> 16) & 0xff; 174 hwaddr[4] = (val0 >> 8) & 0xff; 175 hwaddr[5] = (val0 >> 0) & 0xff; 176 } else { 177 rnd = arc4random() & 0x00ffffff; 178 hwaddr[0] = 'b'; 179 hwaddr[1] = 's'; 180 hwaddr[2] = 'd'; 181 hwaddr[3] = (rnd >> 16) & 0xff; 182 hwaddr[4] = (rnd >> 8) & 0xff; 183 hwaddr[5] = (rnd >> 0) & 0xff; 184 } 185 if (bootverbose) 186 printf("MAC address: %s\n", ether_sprintf(hwaddr)); 187 } 188 189 static void 190 emac_set_rx_mode(struct emac_softc *sc) 191 { 192 struct ifnet *ifp; 193 struct ifmultiaddr *ifma; 194 uint32_t h, hashes[2]; 195 uint32_t rcr = 0; 196 197 EMAC_ASSERT_LOCKED(sc); 198 199 ifp = sc->emac_ifp; 200 201 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); 202 203 /* Unicast packet and DA filtering */ 204 rcr |= EMAC_RX_UCAD; 205 rcr |= EMAC_RX_DAF; 206 207 hashes[0] = 0; 208 hashes[1] = 0; 209 if (ifp->if_flags & IFF_ALLMULTI) { 210 hashes[0] = 0xffffffff; 211 hashes[1] = 0xffffffff; 212 } else { 213 if_maddr_rlock(ifp); 214 TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) { 215 if (ifma->ifma_addr->sa_family != AF_LINK) 216 continue; 217 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 218 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 219 hashes[h >> 5] |= 1 << (h & 0x1f); 220 } 221 if_maddr_runlock(ifp); 222 } 223 rcr |= EMAC_RX_MCO; 224 rcr |= EMAC_RX_MHF; 225 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]); 226 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]); 227 228 if (ifp->if_flags & IFF_BROADCAST) { 229 rcr |= EMAC_RX_BCO; 230 rcr |= EMAC_RX_MCO; 231 } 232 233 if (ifp->if_flags & IFF_PROMISC) 234 rcr |= EMAC_RX_PA; 235 else 236 rcr |= EMAC_RX_UCAD; 237 238 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr); 239 } 240 241 static void 242 emac_reset(struct emac_softc *sc) 243 { 244 245 EMAC_WRITE_REG(sc, EMAC_CTL, 0); 246 DELAY(200); 247 EMAC_WRITE_REG(sc, EMAC_CTL, 1); 248 DELAY(200); 249 } 250 251 static void 252 emac_drain_rxfifo(struct emac_softc *sc) 253 { 254 uint32_t data; 255 256 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0) 257 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 258 } 259 260 static void 261 emac_txeof(struct emac_softc *sc, uint32_t status) 262 { 263 struct ifnet *ifp; 264 265 EMAC_ASSERT_LOCKED(sc); 266 267 ifp = sc->emac_ifp; 268 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1); 269 sc->emac_fifo_mask &= ~status; 270 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 271 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2); 272 else 273 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 274 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 275 276 /* Unarm watchdog timer if no TX */ 277 sc->emac_watchdog_timer = 0; 278 } 279 280 static void 281 emac_rxeof(struct emac_softc *sc, int count) 282 { 283 struct ifnet *ifp; 284 struct mbuf *m, *m0; 285 uint32_t reg_val, rxcount; 286 int16_t len; 287 uint16_t status; 288 int i; 289 290 ifp = sc->emac_ifp; 291 for (; count > 0 && 292 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) { 293 /* 294 * Race warning: The first packet might arrive with 295 * the interrupts disabled, but the second will fix 296 */ 297 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 298 if (!rxcount) { 299 /* Had one stuck? */ 300 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 301 if (!rxcount) 302 return; 303 } 304 /* Check packet header */ 305 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 306 if (reg_val != EMAC_PACKET_HEADER) { 307 /* Packet header is wrong */ 308 if (bootverbose) 309 if_printf(ifp, "wrong packet header\n"); 310 /* Disable RX */ 311 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 312 reg_val &= ~EMAC_CTL_RX_EN; 313 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 314 315 /* Flush RX FIFO */ 316 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 317 reg_val |= EMAC_RX_FLUSH_FIFO; 318 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 319 for (i = 100; i > 0; i--) { 320 DELAY(100); 321 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) & 322 EMAC_RX_FLUSH_FIFO) == 0) 323 break; 324 } 325 if (i == 0) { 326 device_printf(sc->emac_dev, 327 "flush FIFO timeout\n"); 328 /* Reinitialize controller */ 329 emac_init_locked(sc); 330 return; 331 } 332 /* Enable RX */ 333 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 334 reg_val |= EMAC_CTL_RX_EN; 335 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 336 337 return; 338 } 339 340 /* Get packet size and status */ 341 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 342 len = reg_val & 0xffff; 343 status = (reg_val >> 16) & 0xffff; 344 345 if (len < 64 || (status & EMAC_PKT_OK) == 0) { 346 if (bootverbose) 347 if_printf(ifp, 348 "bad packet: len = %i status = %i\n", 349 len, status); 350 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 351 emac_drain_rxfifo(sc); 352 continue; 353 } 354 #if 0 355 if (status & (EMAC_CRCERR | EMAC_LENERR)) { 356 good_packet = 0; 357 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 358 if (status & EMAC_CRCERR) 359 if_printf(ifp, "crc error\n"); 360 if (status & EMAC_LENERR) 361 if_printf(ifp, "length error\n"); 362 } 363 #endif 364 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 365 if (m == NULL) { 366 emac_drain_rxfifo(sc); 367 return; 368 } 369 m->m_len = m->m_pkthdr.len = MCLBYTES; 370 371 /* Copy entire frame to mbuf first. */ 372 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle, 373 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4); 374 375 m->m_pkthdr.rcvif = ifp; 376 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN; 377 378 /* 379 * Emac controller needs strict aligment, so to avoid 380 * copying over an entire frame to align, we allocate 381 * a new mbuf and copy ethernet header + IP header to 382 * the new mbuf. The new mbuf is prepended into the 383 * existing mbuf chain. 384 */ 385 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) { 386 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 387 m->m_data += ETHER_HDR_LEN; 388 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) && 389 m->m_len > (MHLEN - ETHER_HDR_LEN)) { 390 MGETHDR(m0, M_NOWAIT, MT_DATA); 391 if (m0 != NULL) { 392 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen; 393 bcopy(m->m_data, m0->m_data, len); 394 m->m_data += len; 395 m->m_len -= len; 396 m0->m_len = len; 397 M_MOVE_PKTHDR(m0, m); 398 m0->m_next = m; 399 m = m0; 400 } else { 401 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 402 m_freem(m); 403 m = NULL; 404 continue; 405 } 406 } else if (m->m_len > EMAC_MAC_MAXF) { 407 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 408 m_freem(m); 409 m = NULL; 410 continue; 411 } 412 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 413 EMAC_UNLOCK(sc); 414 (*ifp->if_input)(ifp, m); 415 EMAC_LOCK(sc); 416 } 417 } 418 419 static void 420 emac_watchdog(struct emac_softc *sc) 421 { 422 struct ifnet *ifp; 423 424 EMAC_ASSERT_LOCKED(sc); 425 426 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer) 427 return; 428 429 ifp = sc->emac_ifp; 430 431 if (sc->emac_link == 0) { 432 if (bootverbose) 433 if_printf(sc->emac_ifp, "watchdog timeout " 434 "(missed link)\n"); 435 } else 436 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n"); 437 438 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 439 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 440 emac_init_locked(sc); 441 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 442 emac_start_locked(ifp); 443 } 444 445 static void 446 emac_tick(void *arg) 447 { 448 struct emac_softc *sc; 449 struct mii_data *mii; 450 451 sc = (struct emac_softc *)arg; 452 mii = device_get_softc(sc->emac_miibus); 453 mii_tick(mii); 454 455 emac_watchdog(sc); 456 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 457 } 458 459 static void 460 emac_init(void *xcs) 461 { 462 struct emac_softc *sc; 463 464 sc = (struct emac_softc *)xcs; 465 EMAC_LOCK(sc); 466 emac_init_locked(sc); 467 EMAC_UNLOCK(sc); 468 } 469 470 static void 471 emac_init_locked(struct emac_softc *sc) 472 { 473 struct ifnet *ifp; 474 struct mii_data *mii; 475 uint32_t reg_val; 476 uint8_t *eaddr; 477 478 EMAC_ASSERT_LOCKED(sc); 479 480 ifp = sc->emac_ifp; 481 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 482 return; 483 484 /* Flush RX FIFO */ 485 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 486 reg_val |= EMAC_RX_FLUSH_FIFO; 487 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 488 DELAY(1); 489 490 /* Soft reset MAC */ 491 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 492 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); 493 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 494 495 /* Set MII clock */ 496 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); 497 reg_val &= (~(0xf << 2)); 498 reg_val |= (0xd << 2); 499 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); 500 501 /* Clear RX counter */ 502 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); 503 504 /* Disable all interrupt and clear interrupt status */ 505 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 506 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 507 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 508 DELAY(1); 509 510 /* Set up TX */ 511 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); 512 reg_val |= EMAC_TX_AB_M; 513 reg_val &= EMAC_TX_TM; 514 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); 515 516 /* Set up RX */ 517 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 518 reg_val |= EMAC_RX_SETUP; 519 reg_val &= EMAC_RX_TM; 520 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 521 522 /* Set up MAC CTL0. */ 523 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 524 reg_val |= EMAC_MAC_CTL0_SETUP; 525 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 526 527 /* Set up MAC CTL1. */ 528 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1); 529 reg_val |= EMAC_MAC_CTL1_SETUP; 530 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val); 531 532 /* Set up IPGT */ 533 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD); 534 535 /* Set up IPGR */ 536 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 | 537 (EMAC_MAC_NBTB_IPG1 << 8)); 538 539 /* Set up Collison window */ 540 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8)); 541 542 /* Set up Max Frame Length */ 543 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL); 544 545 /* Setup ethernet address */ 546 eaddr = IF_LLADDR(ifp); 547 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 | 548 eaddr[1] << 8 | eaddr[2]); 549 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 | 550 eaddr[4] << 8 | eaddr[5]); 551 552 /* Setup rx filter */ 553 emac_set_rx_mode(sc); 554 555 /* Enable RX/TX0/RX Hlevel interrupt */ 556 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 557 reg_val |= EMAC_INT_EN; 558 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 559 560 ifp->if_drv_flags |= IFF_DRV_RUNNING; 561 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 562 563 sc->emac_link = 0; 564 565 /* Switch to the current media. */ 566 mii = device_get_softc(sc->emac_miibus); 567 mii_mediachg(mii); 568 569 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 570 } 571 572 573 static void 574 emac_start(struct ifnet *ifp) 575 { 576 struct emac_softc *sc; 577 578 sc = ifp->if_softc; 579 EMAC_LOCK(sc); 580 emac_start_locked(ifp); 581 EMAC_UNLOCK(sc); 582 } 583 584 static void 585 emac_start_locked(struct ifnet *ifp) 586 { 587 struct emac_softc *sc; 588 struct mbuf *m, *m0; 589 uint32_t fifo, reg; 590 591 sc = ifp->if_softc; 592 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 593 return; 594 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 595 return; 596 if (sc->emac_link == 0) 597 return; 598 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 599 if (m == NULL) 600 return; 601 602 /* Select channel */ 603 if (sc->emac_fifo_mask & EMAC_TX_FIFO0) 604 fifo = 1; 605 else 606 fifo = 0; 607 sc->emac_fifo_mask |= (1 << fifo); 608 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 609 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 610 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo); 611 612 /* 613 * Emac controller wants 4 byte aligned TX buffers. 614 * We have to copy pretty much all the time. 615 */ 616 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) { 617 m0 = m_defrag(m, M_NOWAIT); 618 if (m0 == NULL) { 619 m_freem(m); 620 m = NULL; 621 return; 622 } 623 m = m0; 624 } 625 /* Write data */ 626 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle, 627 EMAC_TX_IO_DATA, mtod(m, uint32_t *), 628 roundup2(m->m_len, 4) / 4); 629 630 /* Send the data lengh. */ 631 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1; 632 EMAC_WRITE_REG(sc, reg, m->m_len); 633 634 /* Start translate from fifo to phy. */ 635 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1; 636 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1); 637 638 /* Set timeout */ 639 sc->emac_watchdog_timer = 5; 640 641 /* Data have been sent to hardware, it is okay to free the mbuf now. */ 642 BPF_MTAP(ifp, m); 643 m_freem(m); 644 } 645 646 static void 647 emac_stop_locked(struct emac_softc *sc) 648 { 649 struct ifnet *ifp; 650 uint32_t reg_val; 651 652 EMAC_ASSERT_LOCKED(sc); 653 654 ifp = sc->emac_ifp; 655 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 656 sc->emac_link = 0; 657 658 /* Disable all interrupt and clear interrupt status */ 659 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 660 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 661 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 662 663 /* Disable RX/TX */ 664 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 665 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 666 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 667 668 callout_stop(&sc->emac_tick_ch); 669 } 670 671 static void 672 emac_intr(void *arg) 673 { 674 struct emac_softc *sc; 675 struct ifnet *ifp; 676 uint32_t reg_val; 677 678 sc = (struct emac_softc *)arg; 679 EMAC_LOCK(sc); 680 681 /* Disable all interrupts */ 682 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 683 /* Get EMAC interrupt status */ 684 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 685 /* Clear ISR status */ 686 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 687 688 /* Received incoming packet */ 689 if (reg_val & EMAC_INT_STA_RX) 690 emac_rxeof(sc, sc->emac_rx_process_limit); 691 692 /* Transmit Interrupt check */ 693 if (reg_val & EMAC_INT_STA_TX) { 694 emac_txeof(sc, reg_val); 695 ifp = sc->emac_ifp; 696 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 697 emac_start_locked(ifp); 698 } 699 700 /* Re-enable interrupt mask */ 701 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 702 reg_val |= EMAC_INT_EN; 703 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 704 EMAC_UNLOCK(sc); 705 } 706 707 static int 708 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 709 { 710 struct emac_softc *sc; 711 struct mii_data *mii; 712 struct ifreq *ifr; 713 int error = 0; 714 715 sc = ifp->if_softc; 716 ifr = (struct ifreq *)data; 717 718 switch (command) { 719 case SIOCSIFFLAGS: 720 EMAC_LOCK(sc); 721 if (ifp->if_flags & IFF_UP) { 722 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 723 if ((ifp->if_flags ^ sc->emac_if_flags) & 724 (IFF_PROMISC | IFF_ALLMULTI)) 725 emac_set_rx_mode(sc); 726 } else 727 emac_init_locked(sc); 728 } else { 729 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 730 emac_stop_locked(sc); 731 } 732 sc->emac_if_flags = ifp->if_flags; 733 EMAC_UNLOCK(sc); 734 break; 735 case SIOCADDMULTI: 736 case SIOCDELMULTI: 737 EMAC_LOCK(sc); 738 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 739 emac_set_rx_mode(sc); 740 } 741 EMAC_UNLOCK(sc); 742 break; 743 case SIOCGIFMEDIA: 744 case SIOCSIFMEDIA: 745 mii = device_get_softc(sc->emac_miibus); 746 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 747 break; 748 default: 749 error = ether_ioctl(ifp, command, data); 750 break; 751 } 752 return (error); 753 } 754 755 static int 756 emac_probe(device_t dev) 757 { 758 759 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-emac")) 760 return (ENXIO); 761 762 device_set_desc(dev, "A10/A20 EMAC ethernet controller"); 763 return (BUS_PROBE_DEFAULT); 764 } 765 766 static int 767 emac_detach(device_t dev) 768 { 769 struct emac_softc *sc; 770 771 sc = device_get_softc(dev); 772 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 773 if (device_is_attached(dev)) { 774 ether_ifdetach(sc->emac_ifp); 775 EMAC_LOCK(sc); 776 emac_stop_locked(sc); 777 EMAC_UNLOCK(sc); 778 callout_drain(&sc->emac_tick_ch); 779 } 780 781 if (sc->emac_intrhand != NULL) 782 bus_teardown_intr(sc->emac_dev, sc->emac_irq, 783 sc->emac_intrhand); 784 785 if (sc->emac_miibus != NULL) { 786 device_delete_child(sc->emac_dev, sc->emac_miibus); 787 bus_generic_detach(sc->emac_dev); 788 } 789 790 if (sc->emac_res != NULL) 791 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res); 792 793 if (sc->emac_irq != NULL) 794 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq); 795 796 if (sc->emac_ifp != NULL) 797 if_free(sc->emac_ifp); 798 799 if (mtx_initialized(&sc->emac_mtx)) 800 mtx_destroy(&sc->emac_mtx); 801 802 return (0); 803 } 804 805 static int 806 emac_shutdown(device_t dev) 807 { 808 809 return (emac_suspend(dev)); 810 } 811 812 static int 813 emac_suspend(device_t dev) 814 { 815 struct emac_softc *sc; 816 struct ifnet *ifp; 817 818 sc = device_get_softc(dev); 819 820 EMAC_LOCK(sc); 821 ifp = sc->emac_ifp; 822 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 823 emac_stop_locked(sc); 824 EMAC_UNLOCK(sc); 825 826 return (0); 827 } 828 829 static int 830 emac_resume(device_t dev) 831 { 832 struct emac_softc *sc; 833 struct ifnet *ifp; 834 835 sc = device_get_softc(dev); 836 837 EMAC_LOCK(sc); 838 ifp = sc->emac_ifp; 839 if ((ifp->if_flags & IFF_UP) != 0) { 840 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 841 emac_init_locked(sc); 842 } 843 EMAC_UNLOCK(sc); 844 845 return (0); 846 } 847 848 static int 849 emac_attach(device_t dev) 850 { 851 struct emac_softc *sc; 852 struct ifnet *ifp; 853 int error, rid; 854 uint8_t eaddr[ETHER_ADDR_LEN]; 855 856 sc = device_get_softc(dev); 857 sc->emac_dev = dev; 858 859 error = 0; 860 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 861 MTX_DEF); 862 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0); 863 864 rid = 0; 865 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 866 RF_ACTIVE); 867 if (sc->emac_res == NULL) { 868 device_printf(dev, "unable to map memory\n"); 869 error = ENXIO; 870 goto fail; 871 } 872 873 sc->emac_tag = rman_get_bustag(sc->emac_res); 874 sc->emac_handle = rman_get_bushandle(sc->emac_res); 875 876 rid = 0; 877 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 878 RF_SHAREABLE | RF_ACTIVE); 879 if (sc->emac_irq == NULL) { 880 device_printf(dev, "cannot allocate IRQ resources.\n"); 881 error = ENXIO; 882 goto fail; 883 } 884 /* Create device sysctl node. */ 885 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 886 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 887 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 888 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I", 889 "max number of Rx events to process"); 890 891 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 892 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 893 "process_limit", &sc->emac_rx_process_limit); 894 if (error == 0) { 895 if (sc->emac_rx_process_limit < EMAC_PROC_MIN || 896 sc->emac_rx_process_limit > EMAC_PROC_MAX) { 897 device_printf(dev, "process_limit value out of range; " 898 "using default: %d\n", EMAC_PROC_DEFAULT); 899 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 900 } 901 } 902 /* Setup EMAC */ 903 emac_sys_setup(); 904 emac_reset(sc); 905 906 ifp = sc->emac_ifp = if_alloc(IFT_ETHER); 907 if (ifp == NULL) { 908 device_printf(dev, "unable to allocate ifp\n"); 909 error = ENOSPC; 910 goto fail; 911 } 912 ifp->if_softc = sc; 913 914 /* Setup MII */ 915 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd, 916 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 917 if (error != 0) { 918 device_printf(dev, "PHY probe failed\n"); 919 goto fail; 920 } 921 922 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 923 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 924 ifp->if_start = emac_start; 925 ifp->if_ioctl = emac_ioctl; 926 ifp->if_init = emac_init; 927 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 928 929 /* Get MAC address */ 930 emac_get_hwaddr(sc, eaddr); 931 ether_ifattach(ifp, eaddr); 932 933 /* VLAN capability setup. */ 934 ifp->if_capabilities |= IFCAP_VLAN_MTU; 935 ifp->if_capenable = ifp->if_capabilities; 936 /* Tell the upper layer we support VLAN over-sized frames. */ 937 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 938 939 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE, 940 NULL, emac_intr, sc, &sc->emac_intrhand); 941 if (error != 0) { 942 device_printf(dev, "could not set up interrupt handler.\n"); 943 ether_ifdetach(ifp); 944 goto fail; 945 } 946 947 fail: 948 if (error != 0) 949 emac_detach(dev); 950 return (error); 951 } 952 953 static boolean_t 954 emac_miibus_iowait(struct emac_softc *sc) 955 { 956 uint32_t timeout; 957 958 for (timeout = 100; timeout != 0; --timeout) { 959 DELAY(100); 960 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0) 961 return (true); 962 } 963 964 return (false); 965 } 966 967 /* 968 * The MII bus interface 969 */ 970 static int 971 emac_miibus_readreg(device_t dev, int phy, int reg) 972 { 973 struct emac_softc *sc; 974 int rval; 975 976 sc = device_get_softc(dev); 977 978 /* Issue phy address and reg */ 979 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 980 /* Pull up the phy io line */ 981 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 982 if (!emac_miibus_iowait(sc)) { 983 device_printf(dev, "timeout waiting for mii read\n"); 984 return (0); 985 } 986 /* Push down the phy io line */ 987 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 988 /* Read data */ 989 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD); 990 991 return (rval); 992 } 993 994 static int 995 emac_miibus_writereg(device_t dev, int phy, int reg, int data) 996 { 997 struct emac_softc *sc; 998 999 sc = device_get_softc(dev); 1000 1001 /* Issue phy address and reg */ 1002 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1003 /* Write data */ 1004 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data); 1005 /* Pull up the phy io line */ 1006 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1007 if (!emac_miibus_iowait(sc)) { 1008 device_printf(dev, "timeout waiting for mii write\n"); 1009 return (0); 1010 } 1011 /* Push down the phy io line */ 1012 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1013 1014 return (0); 1015 } 1016 1017 static void 1018 emac_miibus_statchg(device_t dev) 1019 { 1020 struct emac_softc *sc; 1021 struct mii_data *mii; 1022 struct ifnet *ifp; 1023 uint32_t reg_val; 1024 1025 sc = device_get_softc(dev); 1026 1027 mii = device_get_softc(sc->emac_miibus); 1028 ifp = sc->emac_ifp; 1029 if (mii == NULL || ifp == NULL || 1030 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1031 return; 1032 1033 sc->emac_link = 0; 1034 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1035 (IFM_ACTIVE | IFM_AVALID)) { 1036 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1037 case IFM_10_T: 1038 case IFM_100_TX: 1039 sc->emac_link = 1; 1040 break; 1041 default: 1042 break; 1043 } 1044 } 1045 /* Program MACs with resolved speed/duplex. */ 1046 if (sc->emac_link != 0) { 1047 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT); 1048 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1049 reg_val &= ~EMAC_MAC_IPGT_HD; 1050 reg_val |= EMAC_MAC_IPGT_FD; 1051 } else { 1052 reg_val &= ~EMAC_MAC_IPGT_FD; 1053 reg_val |= EMAC_MAC_IPGT_HD; 1054 } 1055 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val); 1056 /* Enable RX/TX */ 1057 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1058 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN; 1059 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1060 } else { 1061 /* Disable RX/TX */ 1062 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1063 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 1064 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1065 } 1066 } 1067 1068 static int 1069 emac_ifmedia_upd(struct ifnet *ifp) 1070 { 1071 struct emac_softc *sc; 1072 struct mii_data *mii; 1073 struct mii_softc *miisc; 1074 int error; 1075 1076 sc = ifp->if_softc; 1077 mii = device_get_softc(sc->emac_miibus); 1078 EMAC_LOCK(sc); 1079 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1080 PHY_RESET(miisc); 1081 error = mii_mediachg(mii); 1082 EMAC_UNLOCK(sc); 1083 1084 return (error); 1085 } 1086 1087 static void 1088 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1089 { 1090 struct emac_softc *sc; 1091 struct mii_data *mii; 1092 1093 sc = ifp->if_softc; 1094 mii = device_get_softc(sc->emac_miibus); 1095 1096 EMAC_LOCK(sc); 1097 mii_pollstat(mii); 1098 ifmr->ifm_active = mii->mii_media_active; 1099 ifmr->ifm_status = mii->mii_media_status; 1100 EMAC_UNLOCK(sc); 1101 } 1102 1103 static device_method_t emac_methods[] = { 1104 /* Device interface */ 1105 DEVMETHOD(device_probe, emac_probe), 1106 DEVMETHOD(device_attach, emac_attach), 1107 DEVMETHOD(device_detach, emac_detach), 1108 DEVMETHOD(device_shutdown, emac_shutdown), 1109 DEVMETHOD(device_suspend, emac_suspend), 1110 DEVMETHOD(device_resume, emac_resume), 1111 1112 /* bus interface, for miibus */ 1113 DEVMETHOD(bus_print_child, bus_generic_print_child), 1114 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1115 1116 /* MII interface */ 1117 DEVMETHOD(miibus_readreg, emac_miibus_readreg), 1118 DEVMETHOD(miibus_writereg, emac_miibus_writereg), 1119 DEVMETHOD(miibus_statchg, emac_miibus_statchg), 1120 1121 DEVMETHOD_END 1122 }; 1123 1124 static driver_t emac_driver = { 1125 "emac", 1126 emac_methods, 1127 sizeof(struct emac_softc) 1128 }; 1129 1130 static devclass_t emac_devclass; 1131 1132 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0); 1133 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0); 1134 MODULE_DEPEND(emac, miibus, 1, 1, 1); 1135 MODULE_DEPEND(emac, ether, 1, 1, 1); 1136 1137 static int 1138 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 1139 { 1140 int error, value; 1141 1142 if (arg1 == NULL) 1143 return (EINVAL); 1144 value = *(int *)arg1; 1145 error = sysctl_handle_int(oidp, &value, 0, req); 1146 if (error || req->newptr == NULL) 1147 return (error); 1148 if (value < low || value > high) 1149 return (EINVAL); 1150 *(int *)arg1 = value; 1151 1152 return (0); 1153 } 1154 1155 static int 1156 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS) 1157 { 1158 1159 return (sysctl_int_range(oidp, arg1, arg2, req, 1160 EMAC_PROC_MIN, EMAC_PROC_MAX)); 1161 } 1162