1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* A10/A20 EMAC driver */ 30 31 #include <sys/cdefs.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 #include <sys/mbuf.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/socket.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/gpio.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/intr.h> 49 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_mib.h> 57 #include <net/ethernet.h> 58 #include <net/if_vlan_var.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net/bpf.h> 68 #include <net/bpfdesc.h> 69 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <arm/allwinner/if_emacreg.h> 77 #include <arm/allwinner/aw_sid.h> 78 79 #include <dev/extres/clk/clk.h> 80 81 #include "miibus_if.h" 82 83 #include "gpio_if.h" 84 85 #include "a10_sramc.h" 86 87 struct emac_softc { 88 if_t emac_ifp; 89 device_t emac_dev; 90 device_t emac_miibus; 91 bus_space_handle_t emac_handle; 92 bus_space_tag_t emac_tag; 93 struct resource *emac_res; 94 struct resource *emac_irq; 95 void *emac_intrhand; 96 clk_t emac_clk; 97 int emac_if_flags; 98 struct mtx emac_mtx; 99 struct callout emac_tick_ch; 100 int emac_watchdog_timer; 101 int emac_rx_process_limit; 102 int emac_link; 103 uint32_t emac_fifo_mask; 104 }; 105 106 static int emac_probe(device_t); 107 static int emac_attach(device_t); 108 static int emac_detach(device_t); 109 static int emac_shutdown(device_t); 110 static int emac_suspend(device_t); 111 static int emac_resume(device_t); 112 113 static int emac_sys_setup(struct emac_softc *); 114 static void emac_reset(struct emac_softc *); 115 116 static void emac_init_locked(struct emac_softc *); 117 static void emac_start_locked(if_t); 118 static void emac_init(void *); 119 static void emac_stop_locked(struct emac_softc *); 120 static void emac_intr(void *); 121 static int emac_ioctl(if_t, u_long, caddr_t); 122 123 static void emac_rxeof(struct emac_softc *, int); 124 static void emac_txeof(struct emac_softc *, uint32_t); 125 126 static int emac_miibus_readreg(device_t, int, int); 127 static int emac_miibus_writereg(device_t, int, int, int); 128 static void emac_miibus_statchg(device_t); 129 130 static int emac_ifmedia_upd(if_t); 131 static void emac_ifmedia_sts(if_t, struct ifmediareq *); 132 133 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 134 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS); 135 136 #define EMAC_READ_REG(sc, reg) \ 137 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg) 138 #define EMAC_WRITE_REG(sc, reg, val) \ 139 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val) 140 141 static int 142 emac_sys_setup(struct emac_softc *sc) 143 { 144 int error; 145 146 /* Activate EMAC clock. */ 147 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk); 148 if (error != 0) { 149 device_printf(sc->emac_dev, "cannot get clock\n"); 150 return (error); 151 } 152 error = clk_enable(sc->emac_clk); 153 if (error != 0) { 154 device_printf(sc->emac_dev, "cannot enable clock\n"); 155 return (error); 156 } 157 158 /* Map sram. */ 159 a10_map_to_emac(); 160 161 return (0); 162 } 163 164 static void 165 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr) 166 { 167 uint32_t val0, val1, rnd; 168 u_char rootkey[16]; 169 size_t rootkey_size; 170 171 /* 172 * Try to get MAC address from running hardware. 173 * If there is something non-zero there just use it. 174 * 175 * Otherwise set the address to a convenient locally assigned address, 176 * using the SID rootkey. 177 * This is was uboot does so we end up with the same mac as if uboot 178 * did set it. 179 * If we can't get the root key, generate a random one, 180 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 181 * assigned bit set, and the broadcast/multicast bit clear. 182 */ 183 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0); 184 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1); 185 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) { 186 hwaddr[0] = (val1 >> 16) & 0xff; 187 hwaddr[1] = (val1 >> 8) & 0xff; 188 hwaddr[2] = (val1 >> 0) & 0xff; 189 hwaddr[3] = (val0 >> 16) & 0xff; 190 hwaddr[4] = (val0 >> 8) & 0xff; 191 hwaddr[5] = (val0 >> 0) & 0xff; 192 } else { 193 rootkey_size = sizeof(rootkey); 194 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey, 195 &rootkey_size) == 0) { 196 hwaddr[0] = 0x2; 197 hwaddr[1] = rootkey[3]; 198 hwaddr[2] = rootkey[12]; 199 hwaddr[3] = rootkey[13]; 200 hwaddr[4] = rootkey[14]; 201 hwaddr[5] = rootkey[15]; 202 } 203 else { 204 rnd = arc4random() & 0x00ffffff; 205 hwaddr[0] = 'b'; 206 hwaddr[1] = 's'; 207 hwaddr[2] = 'd'; 208 hwaddr[3] = (rnd >> 16) & 0xff; 209 hwaddr[4] = (rnd >> 8) & 0xff; 210 hwaddr[5] = (rnd >> 0) & 0xff; 211 } 212 } 213 if (bootverbose) 214 printf("MAC address: %s\n", ether_sprintf(hwaddr)); 215 } 216 217 static u_int 218 emac_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 219 { 220 uint32_t h, *hashes = arg; 221 222 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 223 hashes[h >> 5] |= 1 << (h & 0x1f); 224 225 return (1); 226 } 227 228 static void 229 emac_set_rx_mode(struct emac_softc *sc) 230 { 231 if_t ifp; 232 uint32_t hashes[2]; 233 uint32_t rcr = 0; 234 235 EMAC_ASSERT_LOCKED(sc); 236 237 ifp = sc->emac_ifp; 238 239 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); 240 241 /* Unicast packet and DA filtering */ 242 rcr |= EMAC_RX_UCAD; 243 rcr |= EMAC_RX_DAF; 244 245 hashes[0] = 0; 246 hashes[1] = 0; 247 if (if_getflags(ifp) & IFF_ALLMULTI) { 248 hashes[0] = 0xffffffff; 249 hashes[1] = 0xffffffff; 250 } else 251 if_foreach_llmaddr(ifp, emac_hash_maddr, hashes); 252 rcr |= EMAC_RX_MCO; 253 rcr |= EMAC_RX_MHF; 254 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]); 255 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]); 256 257 if (if_getflags(ifp) & IFF_BROADCAST) { 258 rcr |= EMAC_RX_BCO; 259 rcr |= EMAC_RX_MCO; 260 } 261 262 if (if_getflags(ifp) & IFF_PROMISC) 263 rcr |= EMAC_RX_PA; 264 else 265 rcr |= EMAC_RX_UCAD; 266 267 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr); 268 } 269 270 static void 271 emac_reset(struct emac_softc *sc) 272 { 273 274 EMAC_WRITE_REG(sc, EMAC_CTL, 0); 275 DELAY(200); 276 EMAC_WRITE_REG(sc, EMAC_CTL, 1); 277 DELAY(200); 278 } 279 280 static void 281 emac_drain_rxfifo(struct emac_softc *sc) 282 { 283 284 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0) 285 (void)EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 286 } 287 288 static void 289 emac_txeof(struct emac_softc *sc, uint32_t status) 290 { 291 if_t ifp; 292 293 EMAC_ASSERT_LOCKED(sc); 294 295 ifp = sc->emac_ifp; 296 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1); 297 sc->emac_fifo_mask &= ~status; 298 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 299 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2); 300 else 301 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 302 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 303 304 /* Unarm watchdog timer if no TX */ 305 sc->emac_watchdog_timer = 0; 306 } 307 308 static void 309 emac_rxeof(struct emac_softc *sc, int count) 310 { 311 if_t ifp; 312 struct mbuf *m, *m0; 313 uint32_t reg_val, rxcount; 314 int16_t len; 315 uint16_t status; 316 int i; 317 318 ifp = sc->emac_ifp; 319 for (; count > 0 && 320 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; count--) { 321 /* 322 * Race warning: The first packet might arrive with 323 * the interrupts disabled, but the second will fix 324 */ 325 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 326 if (!rxcount) { 327 /* Had one stuck? */ 328 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 329 if (!rxcount) 330 return; 331 } 332 /* Check packet header */ 333 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 334 if (reg_val != EMAC_PACKET_HEADER) { 335 /* Packet header is wrong */ 336 if (bootverbose) 337 if_printf(ifp, "wrong packet header\n"); 338 /* Disable RX */ 339 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 340 reg_val &= ~EMAC_CTL_RX_EN; 341 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 342 343 /* Flush RX FIFO */ 344 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 345 reg_val |= EMAC_RX_FLUSH_FIFO; 346 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 347 for (i = 100; i > 0; i--) { 348 DELAY(100); 349 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) & 350 EMAC_RX_FLUSH_FIFO) == 0) 351 break; 352 } 353 if (i == 0) { 354 device_printf(sc->emac_dev, 355 "flush FIFO timeout\n"); 356 /* Reinitialize controller */ 357 emac_init_locked(sc); 358 return; 359 } 360 /* Enable RX */ 361 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 362 reg_val |= EMAC_CTL_RX_EN; 363 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 364 365 return; 366 } 367 368 /* Get packet size and status */ 369 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 370 len = reg_val & 0xffff; 371 status = (reg_val >> 16) & 0xffff; 372 373 if (len < 64 || (status & EMAC_PKT_OK) == 0) { 374 if (bootverbose) 375 if_printf(ifp, 376 "bad packet: len = %i status = %i\n", 377 len, status); 378 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 379 emac_drain_rxfifo(sc); 380 continue; 381 } 382 #if 0 383 if (status & (EMAC_CRCERR | EMAC_LENERR)) { 384 good_packet = 0; 385 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 386 if (status & EMAC_CRCERR) 387 if_printf(ifp, "crc error\n"); 388 if (status & EMAC_LENERR) 389 if_printf(ifp, "length error\n"); 390 } 391 #endif 392 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 393 if (m == NULL) { 394 emac_drain_rxfifo(sc); 395 return; 396 } 397 m->m_len = m->m_pkthdr.len = MCLBYTES; 398 399 /* Copy entire frame to mbuf first. */ 400 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle, 401 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4); 402 403 m->m_pkthdr.rcvif = ifp; 404 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN; 405 406 /* 407 * Emac controller needs strict alignment, so to avoid 408 * copying over an entire frame to align, we allocate 409 * a new mbuf and copy ethernet header + IP header to 410 * the new mbuf. The new mbuf is prepended into the 411 * existing mbuf chain. 412 */ 413 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) { 414 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 415 m->m_data += ETHER_HDR_LEN; 416 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) && 417 m->m_len > (MHLEN - ETHER_HDR_LEN)) { 418 MGETHDR(m0, M_NOWAIT, MT_DATA); 419 if (m0 != NULL) { 420 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen; 421 bcopy(m->m_data, m0->m_data, len); 422 m->m_data += len; 423 m->m_len -= len; 424 m0->m_len = len; 425 M_MOVE_PKTHDR(m0, m); 426 m0->m_next = m; 427 m = m0; 428 } else { 429 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 430 m_freem(m); 431 m = NULL; 432 continue; 433 } 434 } else if (m->m_len > EMAC_MAC_MAXF) { 435 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 436 m_freem(m); 437 m = NULL; 438 continue; 439 } 440 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 441 EMAC_UNLOCK(sc); 442 if_input(ifp, m); 443 EMAC_LOCK(sc); 444 } 445 } 446 447 static void 448 emac_watchdog(struct emac_softc *sc) 449 { 450 if_t ifp; 451 452 EMAC_ASSERT_LOCKED(sc); 453 454 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer) 455 return; 456 457 ifp = sc->emac_ifp; 458 459 if (sc->emac_link == 0) { 460 if (bootverbose) 461 if_printf(sc->emac_ifp, "watchdog timeout " 462 "(missed link)\n"); 463 } else 464 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n"); 465 466 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 467 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 468 emac_init_locked(sc); 469 if (!if_sendq_empty(ifp)) 470 emac_start_locked(ifp); 471 } 472 473 static void 474 emac_tick(void *arg) 475 { 476 struct emac_softc *sc; 477 struct mii_data *mii; 478 479 sc = (struct emac_softc *)arg; 480 mii = device_get_softc(sc->emac_miibus); 481 mii_tick(mii); 482 483 emac_watchdog(sc); 484 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 485 } 486 487 static void 488 emac_init(void *xcs) 489 { 490 struct emac_softc *sc; 491 492 sc = (struct emac_softc *)xcs; 493 EMAC_LOCK(sc); 494 emac_init_locked(sc); 495 EMAC_UNLOCK(sc); 496 } 497 498 static void 499 emac_init_locked(struct emac_softc *sc) 500 { 501 if_t ifp; 502 struct mii_data *mii; 503 uint32_t reg_val; 504 uint8_t *eaddr; 505 506 EMAC_ASSERT_LOCKED(sc); 507 508 ifp = sc->emac_ifp; 509 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 510 return; 511 512 /* Flush RX FIFO */ 513 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 514 reg_val |= EMAC_RX_FLUSH_FIFO; 515 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 516 DELAY(1); 517 518 /* Soft reset MAC */ 519 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 520 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); 521 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 522 523 /* Set MII clock */ 524 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); 525 reg_val &= (~(0xf << 2)); 526 reg_val |= (0xd << 2); 527 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); 528 529 /* Clear RX counter */ 530 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); 531 532 /* Disable all interrupt and clear interrupt status */ 533 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 534 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 535 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 536 DELAY(1); 537 538 /* Set up TX */ 539 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); 540 reg_val |= EMAC_TX_AB_M; 541 reg_val &= EMAC_TX_TM; 542 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); 543 544 /* Set up RX */ 545 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 546 reg_val |= EMAC_RX_SETUP; 547 reg_val &= EMAC_RX_TM; 548 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 549 550 /* Set up MAC CTL0. */ 551 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 552 reg_val |= EMAC_MAC_CTL0_SETUP; 553 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 554 555 /* Set up MAC CTL1. */ 556 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1); 557 reg_val |= EMAC_MAC_CTL1_SETUP; 558 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val); 559 560 /* Set up IPGT */ 561 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD); 562 563 /* Set up IPGR */ 564 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 | 565 (EMAC_MAC_NBTB_IPG1 << 8)); 566 567 /* Set up Collison window */ 568 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8)); 569 570 /* Set up Max Frame Length */ 571 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL); 572 573 /* Setup ethernet address */ 574 eaddr = if_getlladdr(ifp); 575 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 | 576 eaddr[1] << 8 | eaddr[2]); 577 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 | 578 eaddr[4] << 8 | eaddr[5]); 579 580 /* Setup rx filter */ 581 emac_set_rx_mode(sc); 582 583 /* Enable RX/TX0/RX Hlevel interrupt */ 584 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 585 reg_val |= EMAC_INT_EN; 586 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 587 588 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 589 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 590 591 sc->emac_link = 0; 592 593 /* Switch to the current media. */ 594 mii = device_get_softc(sc->emac_miibus); 595 mii_mediachg(mii); 596 597 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 598 } 599 600 static void 601 emac_start(if_t ifp) 602 { 603 struct emac_softc *sc; 604 605 sc = if_getsoftc(ifp); 606 EMAC_LOCK(sc); 607 emac_start_locked(ifp); 608 EMAC_UNLOCK(sc); 609 } 610 611 static void 612 emac_start_locked(if_t ifp) 613 { 614 struct emac_softc *sc; 615 struct mbuf *m, *m0; 616 uint32_t fifo, reg; 617 618 sc = if_getsoftc(ifp); 619 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 620 return; 621 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 622 return; 623 if (sc->emac_link == 0) 624 return; 625 m = if_dequeue(ifp); 626 if (m == NULL) 627 return; 628 629 /* Select channel */ 630 if (sc->emac_fifo_mask & EMAC_TX_FIFO0) 631 fifo = 1; 632 else 633 fifo = 0; 634 sc->emac_fifo_mask |= (1 << fifo); 635 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 636 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 637 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo); 638 639 /* 640 * Emac controller wants 4 byte aligned TX buffers. 641 * We have to copy pretty much all the time. 642 */ 643 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) { 644 m0 = m_defrag(m, M_NOWAIT); 645 if (m0 == NULL) { 646 m_freem(m); 647 m = NULL; 648 return; 649 } 650 m = m0; 651 } 652 /* Write data */ 653 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle, 654 EMAC_TX_IO_DATA, mtod(m, uint32_t *), 655 roundup2(m->m_len, 4) / 4); 656 657 /* Send the data lengh. */ 658 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1; 659 EMAC_WRITE_REG(sc, reg, m->m_len); 660 661 /* Start translate from fifo to phy. */ 662 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1; 663 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1); 664 665 /* Set timeout */ 666 sc->emac_watchdog_timer = 5; 667 668 /* Data have been sent to hardware, it is okay to free the mbuf now. */ 669 BPF_MTAP(ifp, m); 670 m_freem(m); 671 } 672 673 static void 674 emac_stop_locked(struct emac_softc *sc) 675 { 676 if_t ifp; 677 uint32_t reg_val; 678 679 EMAC_ASSERT_LOCKED(sc); 680 681 ifp = sc->emac_ifp; 682 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 683 sc->emac_link = 0; 684 685 /* Disable all interrupt and clear interrupt status */ 686 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 687 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 688 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 689 690 /* Disable RX/TX */ 691 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 692 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 693 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 694 695 callout_stop(&sc->emac_tick_ch); 696 } 697 698 static void 699 emac_intr(void *arg) 700 { 701 struct emac_softc *sc; 702 if_t ifp; 703 uint32_t reg_val; 704 705 sc = (struct emac_softc *)arg; 706 EMAC_LOCK(sc); 707 708 /* Disable all interrupts */ 709 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 710 /* Get EMAC interrupt status */ 711 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 712 /* Clear ISR status */ 713 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 714 715 /* Received incoming packet */ 716 if (reg_val & EMAC_INT_STA_RX) 717 emac_rxeof(sc, sc->emac_rx_process_limit); 718 719 /* Transmit Interrupt check */ 720 if (reg_val & EMAC_INT_STA_TX) { 721 emac_txeof(sc, reg_val); 722 ifp = sc->emac_ifp; 723 if (!if_sendq_empty(ifp)) 724 emac_start_locked(ifp); 725 } 726 727 /* Re-enable interrupt mask */ 728 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 729 reg_val |= EMAC_INT_EN; 730 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 731 EMAC_UNLOCK(sc); 732 } 733 734 static int 735 emac_ioctl(if_t ifp, u_long command, caddr_t data) 736 { 737 struct emac_softc *sc; 738 struct mii_data *mii; 739 struct ifreq *ifr; 740 int error = 0; 741 742 sc = if_getsoftc(ifp); 743 ifr = (struct ifreq *)data; 744 745 switch (command) { 746 case SIOCSIFFLAGS: 747 EMAC_LOCK(sc); 748 if (if_getflags(ifp) & IFF_UP) { 749 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 750 if ((if_getflags(ifp) ^ sc->emac_if_flags) & 751 (IFF_PROMISC | IFF_ALLMULTI)) 752 emac_set_rx_mode(sc); 753 } else 754 emac_init_locked(sc); 755 } else { 756 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 757 emac_stop_locked(sc); 758 } 759 sc->emac_if_flags = if_getflags(ifp); 760 EMAC_UNLOCK(sc); 761 break; 762 case SIOCADDMULTI: 763 case SIOCDELMULTI: 764 EMAC_LOCK(sc); 765 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 766 emac_set_rx_mode(sc); 767 } 768 EMAC_UNLOCK(sc); 769 break; 770 case SIOCGIFMEDIA: 771 case SIOCSIFMEDIA: 772 mii = device_get_softc(sc->emac_miibus); 773 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 774 break; 775 default: 776 error = ether_ioctl(ifp, command, data); 777 break; 778 } 779 return (error); 780 } 781 782 static int 783 emac_probe(device_t dev) 784 { 785 786 if (!ofw_bus_status_okay(dev)) 787 return (ENXIO); 788 789 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac")) 790 return (ENXIO); 791 792 device_set_desc(dev, "A10/A20 EMAC ethernet controller"); 793 return (BUS_PROBE_DEFAULT); 794 } 795 796 static int 797 emac_detach(device_t dev) 798 { 799 struct emac_softc *sc; 800 801 sc = device_get_softc(dev); 802 if_setdrvflagbits(sc->emac_ifp, 0, IFF_DRV_RUNNING); 803 if (device_is_attached(dev)) { 804 ether_ifdetach(sc->emac_ifp); 805 EMAC_LOCK(sc); 806 emac_stop_locked(sc); 807 EMAC_UNLOCK(sc); 808 callout_drain(&sc->emac_tick_ch); 809 } 810 811 if (sc->emac_intrhand != NULL) 812 bus_teardown_intr(sc->emac_dev, sc->emac_irq, 813 sc->emac_intrhand); 814 815 if (sc->emac_miibus != NULL) { 816 device_delete_child(sc->emac_dev, sc->emac_miibus); 817 bus_generic_detach(sc->emac_dev); 818 } 819 820 if (sc->emac_clk != NULL) 821 clk_disable(sc->emac_clk); 822 823 if (sc->emac_res != NULL) 824 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res); 825 826 if (sc->emac_irq != NULL) 827 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq); 828 829 if (sc->emac_ifp != NULL) 830 if_free(sc->emac_ifp); 831 832 if (mtx_initialized(&sc->emac_mtx)) 833 mtx_destroy(&sc->emac_mtx); 834 835 return (0); 836 } 837 838 static int 839 emac_shutdown(device_t dev) 840 { 841 842 return (emac_suspend(dev)); 843 } 844 845 static int 846 emac_suspend(device_t dev) 847 { 848 struct emac_softc *sc; 849 if_t ifp; 850 851 sc = device_get_softc(dev); 852 853 EMAC_LOCK(sc); 854 ifp = sc->emac_ifp; 855 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 856 emac_stop_locked(sc); 857 EMAC_UNLOCK(sc); 858 859 return (0); 860 } 861 862 static int 863 emac_resume(device_t dev) 864 { 865 struct emac_softc *sc; 866 if_t ifp; 867 868 sc = device_get_softc(dev); 869 870 EMAC_LOCK(sc); 871 ifp = sc->emac_ifp; 872 if ((if_getflags(ifp) & IFF_UP) != 0) { 873 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 874 emac_init_locked(sc); 875 } 876 EMAC_UNLOCK(sc); 877 878 return (0); 879 } 880 881 static int 882 emac_attach(device_t dev) 883 { 884 struct emac_softc *sc; 885 if_t ifp; 886 int error, rid; 887 uint8_t eaddr[ETHER_ADDR_LEN]; 888 889 sc = device_get_softc(dev); 890 sc->emac_dev = dev; 891 892 error = 0; 893 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 894 MTX_DEF); 895 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0); 896 897 rid = 0; 898 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 899 RF_ACTIVE); 900 if (sc->emac_res == NULL) { 901 device_printf(dev, "unable to map memory\n"); 902 error = ENXIO; 903 goto fail; 904 } 905 906 sc->emac_tag = rman_get_bustag(sc->emac_res); 907 sc->emac_handle = rman_get_bushandle(sc->emac_res); 908 909 rid = 0; 910 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 911 RF_SHAREABLE | RF_ACTIVE); 912 if (sc->emac_irq == NULL) { 913 device_printf(dev, "cannot allocate IRQ resources.\n"); 914 error = ENXIO; 915 goto fail; 916 } 917 /* Create device sysctl node. */ 918 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 919 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 920 OID_AUTO, "process_limit", 921 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 922 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I", 923 "max number of Rx events to process"); 924 925 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 926 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 927 "process_limit", &sc->emac_rx_process_limit); 928 if (error == 0) { 929 if (sc->emac_rx_process_limit < EMAC_PROC_MIN || 930 sc->emac_rx_process_limit > EMAC_PROC_MAX) { 931 device_printf(dev, "process_limit value out of range; " 932 "using default: %d\n", EMAC_PROC_DEFAULT); 933 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 934 } 935 } 936 /* Setup EMAC */ 937 error = emac_sys_setup(sc); 938 if (error != 0) 939 goto fail; 940 941 emac_reset(sc); 942 943 ifp = sc->emac_ifp = if_alloc(IFT_ETHER); 944 if (ifp == NULL) { 945 device_printf(dev, "unable to allocate ifp\n"); 946 error = ENOSPC; 947 goto fail; 948 } 949 if_setsoftc(ifp, sc); 950 951 /* Setup MII */ 952 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd, 953 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 954 if (error != 0) { 955 device_printf(dev, "PHY probe failed\n"); 956 goto fail; 957 } 958 959 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 960 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 961 if_setstartfn(ifp, emac_start); 962 if_setioctlfn(ifp, emac_ioctl); 963 if_setinitfn(ifp, emac_init); 964 if_setsendqlen(ifp, IFQ_MAXLEN); 965 966 /* Get MAC address */ 967 emac_get_hwaddr(sc, eaddr); 968 ether_ifattach(ifp, eaddr); 969 970 /* VLAN capability setup. */ 971 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 972 if_setcapenable(ifp, if_getcapabilities(ifp)); 973 /* Tell the upper layer we support VLAN over-sized frames. */ 974 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 975 976 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE, 977 NULL, emac_intr, sc, &sc->emac_intrhand); 978 if (error != 0) { 979 device_printf(dev, "could not set up interrupt handler.\n"); 980 ether_ifdetach(ifp); 981 goto fail; 982 } 983 984 fail: 985 if (error != 0) 986 emac_detach(dev); 987 return (error); 988 } 989 990 static bool 991 emac_miibus_iowait(struct emac_softc *sc) 992 { 993 uint32_t timeout; 994 995 for (timeout = 100; timeout != 0; --timeout) { 996 DELAY(100); 997 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0) 998 return (true); 999 } 1000 1001 return (false); 1002 } 1003 1004 /* 1005 * The MII bus interface 1006 */ 1007 static int 1008 emac_miibus_readreg(device_t dev, int phy, int reg) 1009 { 1010 struct emac_softc *sc; 1011 int rval; 1012 1013 sc = device_get_softc(dev); 1014 1015 /* Issue phy address and reg */ 1016 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1017 /* Pull up the phy io line */ 1018 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1019 if (!emac_miibus_iowait(sc)) { 1020 device_printf(dev, "timeout waiting for mii read\n"); 1021 return (0); 1022 } 1023 /* Push down the phy io line */ 1024 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1025 /* Read data */ 1026 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD); 1027 1028 return (rval); 1029 } 1030 1031 static int 1032 emac_miibus_writereg(device_t dev, int phy, int reg, int data) 1033 { 1034 struct emac_softc *sc; 1035 1036 sc = device_get_softc(dev); 1037 1038 /* Issue phy address and reg */ 1039 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1040 /* Write data */ 1041 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data); 1042 /* Pull up the phy io line */ 1043 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1044 if (!emac_miibus_iowait(sc)) { 1045 device_printf(dev, "timeout waiting for mii write\n"); 1046 return (0); 1047 } 1048 /* Push down the phy io line */ 1049 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1050 1051 return (0); 1052 } 1053 1054 static void 1055 emac_miibus_statchg(device_t dev) 1056 { 1057 struct emac_softc *sc; 1058 struct mii_data *mii; 1059 if_t ifp; 1060 uint32_t reg_val; 1061 1062 sc = device_get_softc(dev); 1063 1064 mii = device_get_softc(sc->emac_miibus); 1065 ifp = sc->emac_ifp; 1066 if (mii == NULL || ifp == NULL || 1067 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1068 return; 1069 1070 sc->emac_link = 0; 1071 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1072 (IFM_ACTIVE | IFM_AVALID)) { 1073 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1074 case IFM_10_T: 1075 case IFM_100_TX: 1076 sc->emac_link = 1; 1077 break; 1078 default: 1079 break; 1080 } 1081 } 1082 /* Program MACs with resolved speed/duplex. */ 1083 if (sc->emac_link != 0) { 1084 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT); 1085 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1086 reg_val &= ~EMAC_MAC_IPGT_HD; 1087 reg_val |= EMAC_MAC_IPGT_FD; 1088 } else { 1089 reg_val &= ~EMAC_MAC_IPGT_FD; 1090 reg_val |= EMAC_MAC_IPGT_HD; 1091 } 1092 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val); 1093 /* Enable RX/TX */ 1094 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1095 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN; 1096 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1097 } else { 1098 /* Disable RX/TX */ 1099 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1100 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 1101 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1102 } 1103 } 1104 1105 static int 1106 emac_ifmedia_upd(if_t ifp) 1107 { 1108 struct emac_softc *sc; 1109 struct mii_data *mii; 1110 struct mii_softc *miisc; 1111 int error; 1112 1113 sc = if_getsoftc(ifp); 1114 mii = device_get_softc(sc->emac_miibus); 1115 EMAC_LOCK(sc); 1116 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1117 PHY_RESET(miisc); 1118 error = mii_mediachg(mii); 1119 EMAC_UNLOCK(sc); 1120 1121 return (error); 1122 } 1123 1124 static void 1125 emac_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1126 { 1127 struct emac_softc *sc; 1128 struct mii_data *mii; 1129 1130 sc = if_getsoftc(ifp); 1131 mii = device_get_softc(sc->emac_miibus); 1132 1133 EMAC_LOCK(sc); 1134 mii_pollstat(mii); 1135 ifmr->ifm_active = mii->mii_media_active; 1136 ifmr->ifm_status = mii->mii_media_status; 1137 EMAC_UNLOCK(sc); 1138 } 1139 1140 static device_method_t emac_methods[] = { 1141 /* Device interface */ 1142 DEVMETHOD(device_probe, emac_probe), 1143 DEVMETHOD(device_attach, emac_attach), 1144 DEVMETHOD(device_detach, emac_detach), 1145 DEVMETHOD(device_shutdown, emac_shutdown), 1146 DEVMETHOD(device_suspend, emac_suspend), 1147 DEVMETHOD(device_resume, emac_resume), 1148 1149 /* bus interface, for miibus */ 1150 DEVMETHOD(bus_print_child, bus_generic_print_child), 1151 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1152 1153 /* MII interface */ 1154 DEVMETHOD(miibus_readreg, emac_miibus_readreg), 1155 DEVMETHOD(miibus_writereg, emac_miibus_writereg), 1156 DEVMETHOD(miibus_statchg, emac_miibus_statchg), 1157 1158 DEVMETHOD_END 1159 }; 1160 1161 static driver_t emac_driver = { 1162 "emac", 1163 emac_methods, 1164 sizeof(struct emac_softc) 1165 }; 1166 1167 DRIVER_MODULE(emac, simplebus, emac_driver, 0, 0); 1168 DRIVER_MODULE(miibus, emac, miibus_driver, 0, 0); 1169 MODULE_DEPEND(emac, miibus, 1, 1, 1); 1170 MODULE_DEPEND(emac, ether, 1, 1, 1); 1171 1172 static int 1173 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 1174 { 1175 int error, value; 1176 1177 if (arg1 == NULL) 1178 return (EINVAL); 1179 value = *(int *)arg1; 1180 error = sysctl_handle_int(oidp, &value, 0, req); 1181 if (error || req->newptr == NULL) 1182 return (error); 1183 if (value < low || value > high) 1184 return (EINVAL); 1185 *(int *)arg1 = value; 1186 1187 return (0); 1188 } 1189 1190 static int 1191 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS) 1192 { 1193 1194 return (sysctl_int_range(oidp, arg1, arg2, req, 1195 EMAC_PROC_MIN, EMAC_PROC_MAX)); 1196 } 1197