1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* A10/A20 EMAC driver */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/bus.h> 41 #include <sys/lock.h> 42 #include <sys/mbuf.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/gpio.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/intr.h> 53 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_arp.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_mib.h> 61 #include <net/ethernet.h> 62 #include <net/if_vlan_var.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #endif 70 71 #include <net/bpf.h> 72 #include <net/bpfdesc.h> 73 74 #include <dev/ofw/ofw_bus.h> 75 #include <dev/ofw/ofw_bus_subr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <arm/allwinner/if_emacreg.h> 81 #include <arm/allwinner/aw_sid.h> 82 83 #include <dev/extres/clk/clk.h> 84 85 #include "miibus_if.h" 86 87 #include "gpio_if.h" 88 89 #include "a10_sramc.h" 90 91 struct emac_softc { 92 struct ifnet *emac_ifp; 93 device_t emac_dev; 94 device_t emac_miibus; 95 bus_space_handle_t emac_handle; 96 bus_space_tag_t emac_tag; 97 struct resource *emac_res; 98 struct resource *emac_irq; 99 void *emac_intrhand; 100 clk_t emac_clk; 101 int emac_if_flags; 102 struct mtx emac_mtx; 103 struct callout emac_tick_ch; 104 int emac_watchdog_timer; 105 int emac_rx_process_limit; 106 int emac_link; 107 uint32_t emac_fifo_mask; 108 }; 109 110 static int emac_probe(device_t); 111 static int emac_attach(device_t); 112 static int emac_detach(device_t); 113 static int emac_shutdown(device_t); 114 static int emac_suspend(device_t); 115 static int emac_resume(device_t); 116 117 static int emac_sys_setup(struct emac_softc *); 118 static void emac_reset(struct emac_softc *); 119 120 static void emac_init_locked(struct emac_softc *); 121 static void emac_start_locked(struct ifnet *); 122 static void emac_init(void *); 123 static void emac_stop_locked(struct emac_softc *); 124 static void emac_intr(void *); 125 static int emac_ioctl(struct ifnet *, u_long, caddr_t); 126 127 static void emac_rxeof(struct emac_softc *, int); 128 static void emac_txeof(struct emac_softc *, uint32_t); 129 130 static int emac_miibus_readreg(device_t, int, int); 131 static int emac_miibus_writereg(device_t, int, int, int); 132 static void emac_miibus_statchg(device_t); 133 134 static int emac_ifmedia_upd(struct ifnet *); 135 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *); 136 137 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 138 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS); 139 140 #define EMAC_READ_REG(sc, reg) \ 141 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg) 142 #define EMAC_WRITE_REG(sc, reg, val) \ 143 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val) 144 145 static int 146 emac_sys_setup(struct emac_softc *sc) 147 { 148 int error; 149 150 /* Activate EMAC clock. */ 151 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk); 152 if (error != 0) { 153 device_printf(sc->emac_dev, "cannot get clock\n"); 154 return (error); 155 } 156 error = clk_enable(sc->emac_clk); 157 if (error != 0) { 158 device_printf(sc->emac_dev, "cannot enable clock\n"); 159 return (error); 160 } 161 162 /* Map sram. */ 163 a10_map_to_emac(); 164 165 return (0); 166 } 167 168 static void 169 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr) 170 { 171 uint32_t val0, val1, rnd; 172 u_char rootkey[16]; 173 174 /* 175 * Try to get MAC address from running hardware. 176 * If there is something non-zero there just use it. 177 * 178 * Otherwise set the address to a convenient locally assigned address, 179 * using the SID rootkey. 180 * This is was uboot does so we end up with the same mac as if uboot 181 * did set it. 182 * If we can't get the root key, generate a random one, 183 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 184 * assigned bit set, and the broadcast/multicast bit clear. 185 */ 186 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0); 187 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1); 188 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) { 189 hwaddr[0] = (val1 >> 16) & 0xff; 190 hwaddr[1] = (val1 >> 8) & 0xff; 191 hwaddr[2] = (val1 >> 0) & 0xff; 192 hwaddr[3] = (val0 >> 16) & 0xff; 193 hwaddr[4] = (val0 >> 8) & 0xff; 194 hwaddr[5] = (val0 >> 0) & 0xff; 195 } else { 196 if (aw_sid_get_rootkey(rootkey) == 0) { 197 hwaddr[0] = 0x2; 198 hwaddr[1] = rootkey[3]; 199 hwaddr[2] = rootkey[12]; 200 hwaddr[3] = rootkey[13]; 201 hwaddr[4] = rootkey[14]; 202 hwaddr[5] = rootkey[15]; 203 } 204 else { 205 rnd = arc4random() & 0x00ffffff; 206 hwaddr[0] = 'b'; 207 hwaddr[1] = 's'; 208 hwaddr[2] = 'd'; 209 hwaddr[3] = (rnd >> 16) & 0xff; 210 hwaddr[4] = (rnd >> 8) & 0xff; 211 hwaddr[5] = (rnd >> 0) & 0xff; 212 } 213 } 214 if (bootverbose) 215 printf("MAC address: %s\n", ether_sprintf(hwaddr)); 216 } 217 218 static void 219 emac_set_rx_mode(struct emac_softc *sc) 220 { 221 struct ifnet *ifp; 222 struct ifmultiaddr *ifma; 223 uint32_t h, hashes[2]; 224 uint32_t rcr = 0; 225 226 EMAC_ASSERT_LOCKED(sc); 227 228 ifp = sc->emac_ifp; 229 230 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); 231 232 /* Unicast packet and DA filtering */ 233 rcr |= EMAC_RX_UCAD; 234 rcr |= EMAC_RX_DAF; 235 236 hashes[0] = 0; 237 hashes[1] = 0; 238 if (ifp->if_flags & IFF_ALLMULTI) { 239 hashes[0] = 0xffffffff; 240 hashes[1] = 0xffffffff; 241 } else { 242 if_maddr_rlock(ifp); 243 TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) { 244 if (ifma->ifma_addr->sa_family != AF_LINK) 245 continue; 246 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 247 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 248 hashes[h >> 5] |= 1 << (h & 0x1f); 249 } 250 if_maddr_runlock(ifp); 251 } 252 rcr |= EMAC_RX_MCO; 253 rcr |= EMAC_RX_MHF; 254 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]); 255 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]); 256 257 if (ifp->if_flags & IFF_BROADCAST) { 258 rcr |= EMAC_RX_BCO; 259 rcr |= EMAC_RX_MCO; 260 } 261 262 if (ifp->if_flags & IFF_PROMISC) 263 rcr |= EMAC_RX_PA; 264 else 265 rcr |= EMAC_RX_UCAD; 266 267 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr); 268 } 269 270 static void 271 emac_reset(struct emac_softc *sc) 272 { 273 274 EMAC_WRITE_REG(sc, EMAC_CTL, 0); 275 DELAY(200); 276 EMAC_WRITE_REG(sc, EMAC_CTL, 1); 277 DELAY(200); 278 } 279 280 static void 281 emac_drain_rxfifo(struct emac_softc *sc) 282 { 283 uint32_t data; 284 285 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0) 286 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 287 } 288 289 static void 290 emac_txeof(struct emac_softc *sc, uint32_t status) 291 { 292 struct ifnet *ifp; 293 294 EMAC_ASSERT_LOCKED(sc); 295 296 ifp = sc->emac_ifp; 297 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1); 298 sc->emac_fifo_mask &= ~status; 299 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 300 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2); 301 else 302 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 303 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 304 305 /* Unarm watchdog timer if no TX */ 306 sc->emac_watchdog_timer = 0; 307 } 308 309 static void 310 emac_rxeof(struct emac_softc *sc, int count) 311 { 312 struct ifnet *ifp; 313 struct mbuf *m, *m0; 314 uint32_t reg_val, rxcount; 315 int16_t len; 316 uint16_t status; 317 int i; 318 319 ifp = sc->emac_ifp; 320 for (; count > 0 && 321 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) { 322 /* 323 * Race warning: The first packet might arrive with 324 * the interrupts disabled, but the second will fix 325 */ 326 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 327 if (!rxcount) { 328 /* Had one stuck? */ 329 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 330 if (!rxcount) 331 return; 332 } 333 /* Check packet header */ 334 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 335 if (reg_val != EMAC_PACKET_HEADER) { 336 /* Packet header is wrong */ 337 if (bootverbose) 338 if_printf(ifp, "wrong packet header\n"); 339 /* Disable RX */ 340 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 341 reg_val &= ~EMAC_CTL_RX_EN; 342 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 343 344 /* Flush RX FIFO */ 345 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 346 reg_val |= EMAC_RX_FLUSH_FIFO; 347 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 348 for (i = 100; i > 0; i--) { 349 DELAY(100); 350 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) & 351 EMAC_RX_FLUSH_FIFO) == 0) 352 break; 353 } 354 if (i == 0) { 355 device_printf(sc->emac_dev, 356 "flush FIFO timeout\n"); 357 /* Reinitialize controller */ 358 emac_init_locked(sc); 359 return; 360 } 361 /* Enable RX */ 362 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 363 reg_val |= EMAC_CTL_RX_EN; 364 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 365 366 return; 367 } 368 369 /* Get packet size and status */ 370 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 371 len = reg_val & 0xffff; 372 status = (reg_val >> 16) & 0xffff; 373 374 if (len < 64 || (status & EMAC_PKT_OK) == 0) { 375 if (bootverbose) 376 if_printf(ifp, 377 "bad packet: len = %i status = %i\n", 378 len, status); 379 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 380 emac_drain_rxfifo(sc); 381 continue; 382 } 383 #if 0 384 if (status & (EMAC_CRCERR | EMAC_LENERR)) { 385 good_packet = 0; 386 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 387 if (status & EMAC_CRCERR) 388 if_printf(ifp, "crc error\n"); 389 if (status & EMAC_LENERR) 390 if_printf(ifp, "length error\n"); 391 } 392 #endif 393 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 394 if (m == NULL) { 395 emac_drain_rxfifo(sc); 396 return; 397 } 398 m->m_len = m->m_pkthdr.len = MCLBYTES; 399 400 /* Copy entire frame to mbuf first. */ 401 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle, 402 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4); 403 404 m->m_pkthdr.rcvif = ifp; 405 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN; 406 407 /* 408 * Emac controller needs strict aligment, so to avoid 409 * copying over an entire frame to align, we allocate 410 * a new mbuf and copy ethernet header + IP header to 411 * the new mbuf. The new mbuf is prepended into the 412 * existing mbuf chain. 413 */ 414 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) { 415 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 416 m->m_data += ETHER_HDR_LEN; 417 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) && 418 m->m_len > (MHLEN - ETHER_HDR_LEN)) { 419 MGETHDR(m0, M_NOWAIT, MT_DATA); 420 if (m0 != NULL) { 421 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen; 422 bcopy(m->m_data, m0->m_data, len); 423 m->m_data += len; 424 m->m_len -= len; 425 m0->m_len = len; 426 M_MOVE_PKTHDR(m0, m); 427 m0->m_next = m; 428 m = m0; 429 } else { 430 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 431 m_freem(m); 432 m = NULL; 433 continue; 434 } 435 } else if (m->m_len > EMAC_MAC_MAXF) { 436 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 437 m_freem(m); 438 m = NULL; 439 continue; 440 } 441 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 442 EMAC_UNLOCK(sc); 443 (*ifp->if_input)(ifp, m); 444 EMAC_LOCK(sc); 445 } 446 } 447 448 static void 449 emac_watchdog(struct emac_softc *sc) 450 { 451 struct ifnet *ifp; 452 453 EMAC_ASSERT_LOCKED(sc); 454 455 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer) 456 return; 457 458 ifp = sc->emac_ifp; 459 460 if (sc->emac_link == 0) { 461 if (bootverbose) 462 if_printf(sc->emac_ifp, "watchdog timeout " 463 "(missed link)\n"); 464 } else 465 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n"); 466 467 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 468 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 469 emac_init_locked(sc); 470 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 471 emac_start_locked(ifp); 472 } 473 474 static void 475 emac_tick(void *arg) 476 { 477 struct emac_softc *sc; 478 struct mii_data *mii; 479 480 sc = (struct emac_softc *)arg; 481 mii = device_get_softc(sc->emac_miibus); 482 mii_tick(mii); 483 484 emac_watchdog(sc); 485 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 486 } 487 488 static void 489 emac_init(void *xcs) 490 { 491 struct emac_softc *sc; 492 493 sc = (struct emac_softc *)xcs; 494 EMAC_LOCK(sc); 495 emac_init_locked(sc); 496 EMAC_UNLOCK(sc); 497 } 498 499 static void 500 emac_init_locked(struct emac_softc *sc) 501 { 502 struct ifnet *ifp; 503 struct mii_data *mii; 504 uint32_t reg_val; 505 uint8_t *eaddr; 506 507 EMAC_ASSERT_LOCKED(sc); 508 509 ifp = sc->emac_ifp; 510 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 511 return; 512 513 /* Flush RX FIFO */ 514 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 515 reg_val |= EMAC_RX_FLUSH_FIFO; 516 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 517 DELAY(1); 518 519 /* Soft reset MAC */ 520 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 521 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); 522 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 523 524 /* Set MII clock */ 525 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); 526 reg_val &= (~(0xf << 2)); 527 reg_val |= (0xd << 2); 528 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); 529 530 /* Clear RX counter */ 531 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); 532 533 /* Disable all interrupt and clear interrupt status */ 534 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 535 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 536 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 537 DELAY(1); 538 539 /* Set up TX */ 540 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); 541 reg_val |= EMAC_TX_AB_M; 542 reg_val &= EMAC_TX_TM; 543 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); 544 545 /* Set up RX */ 546 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 547 reg_val |= EMAC_RX_SETUP; 548 reg_val &= EMAC_RX_TM; 549 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 550 551 /* Set up MAC CTL0. */ 552 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 553 reg_val |= EMAC_MAC_CTL0_SETUP; 554 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 555 556 /* Set up MAC CTL1. */ 557 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1); 558 reg_val |= EMAC_MAC_CTL1_SETUP; 559 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val); 560 561 /* Set up IPGT */ 562 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD); 563 564 /* Set up IPGR */ 565 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 | 566 (EMAC_MAC_NBTB_IPG1 << 8)); 567 568 /* Set up Collison window */ 569 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8)); 570 571 /* Set up Max Frame Length */ 572 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL); 573 574 /* Setup ethernet address */ 575 eaddr = IF_LLADDR(ifp); 576 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 | 577 eaddr[1] << 8 | eaddr[2]); 578 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 | 579 eaddr[4] << 8 | eaddr[5]); 580 581 /* Setup rx filter */ 582 emac_set_rx_mode(sc); 583 584 /* Enable RX/TX0/RX Hlevel interrupt */ 585 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 586 reg_val |= EMAC_INT_EN; 587 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 588 589 ifp->if_drv_flags |= IFF_DRV_RUNNING; 590 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 591 592 sc->emac_link = 0; 593 594 /* Switch to the current media. */ 595 mii = device_get_softc(sc->emac_miibus); 596 mii_mediachg(mii); 597 598 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 599 } 600 601 602 static void 603 emac_start(struct ifnet *ifp) 604 { 605 struct emac_softc *sc; 606 607 sc = ifp->if_softc; 608 EMAC_LOCK(sc); 609 emac_start_locked(ifp); 610 EMAC_UNLOCK(sc); 611 } 612 613 static void 614 emac_start_locked(struct ifnet *ifp) 615 { 616 struct emac_softc *sc; 617 struct mbuf *m, *m0; 618 uint32_t fifo, reg; 619 620 sc = ifp->if_softc; 621 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 622 return; 623 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 624 return; 625 if (sc->emac_link == 0) 626 return; 627 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 628 if (m == NULL) 629 return; 630 631 /* Select channel */ 632 if (sc->emac_fifo_mask & EMAC_TX_FIFO0) 633 fifo = 1; 634 else 635 fifo = 0; 636 sc->emac_fifo_mask |= (1 << fifo); 637 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 638 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 639 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo); 640 641 /* 642 * Emac controller wants 4 byte aligned TX buffers. 643 * We have to copy pretty much all the time. 644 */ 645 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) { 646 m0 = m_defrag(m, M_NOWAIT); 647 if (m0 == NULL) { 648 m_freem(m); 649 m = NULL; 650 return; 651 } 652 m = m0; 653 } 654 /* Write data */ 655 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle, 656 EMAC_TX_IO_DATA, mtod(m, uint32_t *), 657 roundup2(m->m_len, 4) / 4); 658 659 /* Send the data lengh. */ 660 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1; 661 EMAC_WRITE_REG(sc, reg, m->m_len); 662 663 /* Start translate from fifo to phy. */ 664 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1; 665 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1); 666 667 /* Set timeout */ 668 sc->emac_watchdog_timer = 5; 669 670 /* Data have been sent to hardware, it is okay to free the mbuf now. */ 671 BPF_MTAP(ifp, m); 672 m_freem(m); 673 } 674 675 static void 676 emac_stop_locked(struct emac_softc *sc) 677 { 678 struct ifnet *ifp; 679 uint32_t reg_val; 680 681 EMAC_ASSERT_LOCKED(sc); 682 683 ifp = sc->emac_ifp; 684 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 685 sc->emac_link = 0; 686 687 /* Disable all interrupt and clear interrupt status */ 688 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 689 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 690 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 691 692 /* Disable RX/TX */ 693 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 694 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 695 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 696 697 callout_stop(&sc->emac_tick_ch); 698 } 699 700 static void 701 emac_intr(void *arg) 702 { 703 struct emac_softc *sc; 704 struct ifnet *ifp; 705 uint32_t reg_val; 706 707 sc = (struct emac_softc *)arg; 708 EMAC_LOCK(sc); 709 710 /* Disable all interrupts */ 711 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 712 /* Get EMAC interrupt status */ 713 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 714 /* Clear ISR status */ 715 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 716 717 /* Received incoming packet */ 718 if (reg_val & EMAC_INT_STA_RX) 719 emac_rxeof(sc, sc->emac_rx_process_limit); 720 721 /* Transmit Interrupt check */ 722 if (reg_val & EMAC_INT_STA_TX) { 723 emac_txeof(sc, reg_val); 724 ifp = sc->emac_ifp; 725 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 726 emac_start_locked(ifp); 727 } 728 729 /* Re-enable interrupt mask */ 730 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 731 reg_val |= EMAC_INT_EN; 732 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 733 EMAC_UNLOCK(sc); 734 } 735 736 static int 737 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 738 { 739 struct emac_softc *sc; 740 struct mii_data *mii; 741 struct ifreq *ifr; 742 int error = 0; 743 744 sc = ifp->if_softc; 745 ifr = (struct ifreq *)data; 746 747 switch (command) { 748 case SIOCSIFFLAGS: 749 EMAC_LOCK(sc); 750 if (ifp->if_flags & IFF_UP) { 751 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 752 if ((ifp->if_flags ^ sc->emac_if_flags) & 753 (IFF_PROMISC | IFF_ALLMULTI)) 754 emac_set_rx_mode(sc); 755 } else 756 emac_init_locked(sc); 757 } else { 758 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 759 emac_stop_locked(sc); 760 } 761 sc->emac_if_flags = ifp->if_flags; 762 EMAC_UNLOCK(sc); 763 break; 764 case SIOCADDMULTI: 765 case SIOCDELMULTI: 766 EMAC_LOCK(sc); 767 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 768 emac_set_rx_mode(sc); 769 } 770 EMAC_UNLOCK(sc); 771 break; 772 case SIOCGIFMEDIA: 773 case SIOCSIFMEDIA: 774 mii = device_get_softc(sc->emac_miibus); 775 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 776 break; 777 default: 778 error = ether_ioctl(ifp, command, data); 779 break; 780 } 781 return (error); 782 } 783 784 static int 785 emac_probe(device_t dev) 786 { 787 788 if (!ofw_bus_status_okay(dev)) 789 return (ENXIO); 790 791 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac")) 792 return (ENXIO); 793 794 device_set_desc(dev, "A10/A20 EMAC ethernet controller"); 795 return (BUS_PROBE_DEFAULT); 796 } 797 798 static int 799 emac_detach(device_t dev) 800 { 801 struct emac_softc *sc; 802 803 sc = device_get_softc(dev); 804 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 805 if (device_is_attached(dev)) { 806 ether_ifdetach(sc->emac_ifp); 807 EMAC_LOCK(sc); 808 emac_stop_locked(sc); 809 EMAC_UNLOCK(sc); 810 callout_drain(&sc->emac_tick_ch); 811 } 812 813 if (sc->emac_intrhand != NULL) 814 bus_teardown_intr(sc->emac_dev, sc->emac_irq, 815 sc->emac_intrhand); 816 817 if (sc->emac_miibus != NULL) { 818 device_delete_child(sc->emac_dev, sc->emac_miibus); 819 bus_generic_detach(sc->emac_dev); 820 } 821 822 if (sc->emac_clk != NULL) 823 clk_disable(sc->emac_clk); 824 825 if (sc->emac_res != NULL) 826 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res); 827 828 if (sc->emac_irq != NULL) 829 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq); 830 831 if (sc->emac_ifp != NULL) 832 if_free(sc->emac_ifp); 833 834 if (mtx_initialized(&sc->emac_mtx)) 835 mtx_destroy(&sc->emac_mtx); 836 837 return (0); 838 } 839 840 static int 841 emac_shutdown(device_t dev) 842 { 843 844 return (emac_suspend(dev)); 845 } 846 847 static int 848 emac_suspend(device_t dev) 849 { 850 struct emac_softc *sc; 851 struct ifnet *ifp; 852 853 sc = device_get_softc(dev); 854 855 EMAC_LOCK(sc); 856 ifp = sc->emac_ifp; 857 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 858 emac_stop_locked(sc); 859 EMAC_UNLOCK(sc); 860 861 return (0); 862 } 863 864 static int 865 emac_resume(device_t dev) 866 { 867 struct emac_softc *sc; 868 struct ifnet *ifp; 869 870 sc = device_get_softc(dev); 871 872 EMAC_LOCK(sc); 873 ifp = sc->emac_ifp; 874 if ((ifp->if_flags & IFF_UP) != 0) { 875 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 876 emac_init_locked(sc); 877 } 878 EMAC_UNLOCK(sc); 879 880 return (0); 881 } 882 883 static int 884 emac_attach(device_t dev) 885 { 886 struct emac_softc *sc; 887 struct ifnet *ifp; 888 int error, rid; 889 uint8_t eaddr[ETHER_ADDR_LEN]; 890 891 sc = device_get_softc(dev); 892 sc->emac_dev = dev; 893 894 error = 0; 895 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 896 MTX_DEF); 897 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0); 898 899 rid = 0; 900 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 901 RF_ACTIVE); 902 if (sc->emac_res == NULL) { 903 device_printf(dev, "unable to map memory\n"); 904 error = ENXIO; 905 goto fail; 906 } 907 908 sc->emac_tag = rman_get_bustag(sc->emac_res); 909 sc->emac_handle = rman_get_bushandle(sc->emac_res); 910 911 rid = 0; 912 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 913 RF_SHAREABLE | RF_ACTIVE); 914 if (sc->emac_irq == NULL) { 915 device_printf(dev, "cannot allocate IRQ resources.\n"); 916 error = ENXIO; 917 goto fail; 918 } 919 /* Create device sysctl node. */ 920 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 921 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 922 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 923 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I", 924 "max number of Rx events to process"); 925 926 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 927 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 928 "process_limit", &sc->emac_rx_process_limit); 929 if (error == 0) { 930 if (sc->emac_rx_process_limit < EMAC_PROC_MIN || 931 sc->emac_rx_process_limit > EMAC_PROC_MAX) { 932 device_printf(dev, "process_limit value out of range; " 933 "using default: %d\n", EMAC_PROC_DEFAULT); 934 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 935 } 936 } 937 /* Setup EMAC */ 938 error = emac_sys_setup(sc); 939 if (error != 0) 940 goto fail; 941 942 emac_reset(sc); 943 944 ifp = sc->emac_ifp = if_alloc(IFT_ETHER); 945 if (ifp == NULL) { 946 device_printf(dev, "unable to allocate ifp\n"); 947 error = ENOSPC; 948 goto fail; 949 } 950 ifp->if_softc = sc; 951 952 /* Setup MII */ 953 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd, 954 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 955 if (error != 0) { 956 device_printf(dev, "PHY probe failed\n"); 957 goto fail; 958 } 959 960 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 961 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 962 ifp->if_start = emac_start; 963 ifp->if_ioctl = emac_ioctl; 964 ifp->if_init = emac_init; 965 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 966 967 /* Get MAC address */ 968 emac_get_hwaddr(sc, eaddr); 969 ether_ifattach(ifp, eaddr); 970 971 /* VLAN capability setup. */ 972 ifp->if_capabilities |= IFCAP_VLAN_MTU; 973 ifp->if_capenable = ifp->if_capabilities; 974 /* Tell the upper layer we support VLAN over-sized frames. */ 975 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 976 977 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE, 978 NULL, emac_intr, sc, &sc->emac_intrhand); 979 if (error != 0) { 980 device_printf(dev, "could not set up interrupt handler.\n"); 981 ether_ifdetach(ifp); 982 goto fail; 983 } 984 985 fail: 986 if (error != 0) 987 emac_detach(dev); 988 return (error); 989 } 990 991 static boolean_t 992 emac_miibus_iowait(struct emac_softc *sc) 993 { 994 uint32_t timeout; 995 996 for (timeout = 100; timeout != 0; --timeout) { 997 DELAY(100); 998 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0) 999 return (true); 1000 } 1001 1002 return (false); 1003 } 1004 1005 /* 1006 * The MII bus interface 1007 */ 1008 static int 1009 emac_miibus_readreg(device_t dev, int phy, int reg) 1010 { 1011 struct emac_softc *sc; 1012 int rval; 1013 1014 sc = device_get_softc(dev); 1015 1016 /* Issue phy address and reg */ 1017 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1018 /* Pull up the phy io line */ 1019 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1020 if (!emac_miibus_iowait(sc)) { 1021 device_printf(dev, "timeout waiting for mii read\n"); 1022 return (0); 1023 } 1024 /* Push down the phy io line */ 1025 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1026 /* Read data */ 1027 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD); 1028 1029 return (rval); 1030 } 1031 1032 static int 1033 emac_miibus_writereg(device_t dev, int phy, int reg, int data) 1034 { 1035 struct emac_softc *sc; 1036 1037 sc = device_get_softc(dev); 1038 1039 /* Issue phy address and reg */ 1040 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1041 /* Write data */ 1042 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data); 1043 /* Pull up the phy io line */ 1044 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1045 if (!emac_miibus_iowait(sc)) { 1046 device_printf(dev, "timeout waiting for mii write\n"); 1047 return (0); 1048 } 1049 /* Push down the phy io line */ 1050 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1051 1052 return (0); 1053 } 1054 1055 static void 1056 emac_miibus_statchg(device_t dev) 1057 { 1058 struct emac_softc *sc; 1059 struct mii_data *mii; 1060 struct ifnet *ifp; 1061 uint32_t reg_val; 1062 1063 sc = device_get_softc(dev); 1064 1065 mii = device_get_softc(sc->emac_miibus); 1066 ifp = sc->emac_ifp; 1067 if (mii == NULL || ifp == NULL || 1068 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1069 return; 1070 1071 sc->emac_link = 0; 1072 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1073 (IFM_ACTIVE | IFM_AVALID)) { 1074 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1075 case IFM_10_T: 1076 case IFM_100_TX: 1077 sc->emac_link = 1; 1078 break; 1079 default: 1080 break; 1081 } 1082 } 1083 /* Program MACs with resolved speed/duplex. */ 1084 if (sc->emac_link != 0) { 1085 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT); 1086 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1087 reg_val &= ~EMAC_MAC_IPGT_HD; 1088 reg_val |= EMAC_MAC_IPGT_FD; 1089 } else { 1090 reg_val &= ~EMAC_MAC_IPGT_FD; 1091 reg_val |= EMAC_MAC_IPGT_HD; 1092 } 1093 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val); 1094 /* Enable RX/TX */ 1095 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1096 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN; 1097 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1098 } else { 1099 /* Disable RX/TX */ 1100 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1101 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 1102 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1103 } 1104 } 1105 1106 static int 1107 emac_ifmedia_upd(struct ifnet *ifp) 1108 { 1109 struct emac_softc *sc; 1110 struct mii_data *mii; 1111 struct mii_softc *miisc; 1112 int error; 1113 1114 sc = ifp->if_softc; 1115 mii = device_get_softc(sc->emac_miibus); 1116 EMAC_LOCK(sc); 1117 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1118 PHY_RESET(miisc); 1119 error = mii_mediachg(mii); 1120 EMAC_UNLOCK(sc); 1121 1122 return (error); 1123 } 1124 1125 static void 1126 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1127 { 1128 struct emac_softc *sc; 1129 struct mii_data *mii; 1130 1131 sc = ifp->if_softc; 1132 mii = device_get_softc(sc->emac_miibus); 1133 1134 EMAC_LOCK(sc); 1135 mii_pollstat(mii); 1136 ifmr->ifm_active = mii->mii_media_active; 1137 ifmr->ifm_status = mii->mii_media_status; 1138 EMAC_UNLOCK(sc); 1139 } 1140 1141 static device_method_t emac_methods[] = { 1142 /* Device interface */ 1143 DEVMETHOD(device_probe, emac_probe), 1144 DEVMETHOD(device_attach, emac_attach), 1145 DEVMETHOD(device_detach, emac_detach), 1146 DEVMETHOD(device_shutdown, emac_shutdown), 1147 DEVMETHOD(device_suspend, emac_suspend), 1148 DEVMETHOD(device_resume, emac_resume), 1149 1150 /* bus interface, for miibus */ 1151 DEVMETHOD(bus_print_child, bus_generic_print_child), 1152 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1153 1154 /* MII interface */ 1155 DEVMETHOD(miibus_readreg, emac_miibus_readreg), 1156 DEVMETHOD(miibus_writereg, emac_miibus_writereg), 1157 DEVMETHOD(miibus_statchg, emac_miibus_statchg), 1158 1159 DEVMETHOD_END 1160 }; 1161 1162 static driver_t emac_driver = { 1163 "emac", 1164 emac_methods, 1165 sizeof(struct emac_softc) 1166 }; 1167 1168 static devclass_t emac_devclass; 1169 1170 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0); 1171 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0); 1172 MODULE_DEPEND(emac, miibus, 1, 1, 1); 1173 MODULE_DEPEND(emac, ether, 1, 1, 1); 1174 1175 static int 1176 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 1177 { 1178 int error, value; 1179 1180 if (arg1 == NULL) 1181 return (EINVAL); 1182 value = *(int *)arg1; 1183 error = sysctl_handle_int(oidp, &value, 0, req); 1184 if (error || req->newptr == NULL) 1185 return (error); 1186 if (value < low || value > high) 1187 return (EINVAL); 1188 *(int *)arg1 = value; 1189 1190 return (0); 1191 } 1192 1193 static int 1194 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS) 1195 { 1196 1197 return (sysctl_int_range(oidp, arg1, arg2, req, 1198 EMAC_PROC_MIN, EMAC_PROC_MAX)); 1199 } 1200