1 /*- 2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* A10/A20 EMAC driver */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/lock.h> 40 #include <sys/mbuf.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/gpio.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/intr.h> 51 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_arp.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_mib.h> 59 #include <net/ethernet.h> 60 #include <net/if_vlan_var.h> 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #endif 68 69 #include <net/bpf.h> 70 #include <net/bpfdesc.h> 71 72 #include <dev/fdt/fdt_common.h> 73 #include <dev/ofw/ofw_bus.h> 74 #include <dev/ofw/ofw_bus_subr.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <arm/allwinner/if_emacreg.h> 80 81 #include "miibus_if.h" 82 83 #include "gpio_if.h" 84 85 #include "a10_clk.h" 86 #include "a10_sramc.h" 87 88 struct emac_softc { 89 struct ifnet *emac_ifp; 90 device_t emac_dev; 91 device_t emac_miibus; 92 bus_space_handle_t emac_handle; 93 bus_space_tag_t emac_tag; 94 struct resource *emac_res; 95 struct resource *emac_irq; 96 void *emac_intrhand; 97 int emac_if_flags; 98 struct mtx emac_mtx; 99 struct callout emac_tick_ch; 100 int emac_watchdog_timer; 101 int emac_rx_process_limit; 102 int emac_link; 103 uint32_t emac_fifo_mask; 104 }; 105 106 static int emac_probe(device_t); 107 static int emac_attach(device_t); 108 static int emac_detach(device_t); 109 static int emac_shutdown(device_t); 110 static int emac_suspend(device_t); 111 static int emac_resume(device_t); 112 113 static void emac_sys_setup(void); 114 static void emac_reset(struct emac_softc *); 115 116 static void emac_init_locked(struct emac_softc *); 117 static void emac_start_locked(struct ifnet *); 118 static void emac_init(void *); 119 static void emac_stop_locked(struct emac_softc *); 120 static void emac_intr(void *); 121 static int emac_ioctl(struct ifnet *, u_long, caddr_t); 122 123 static void emac_rxeof(struct emac_softc *, int); 124 static void emac_txeof(struct emac_softc *, uint32_t); 125 126 static int emac_miibus_readreg(device_t, int, int); 127 static int emac_miibus_writereg(device_t, int, int, int); 128 static void emac_miibus_statchg(device_t); 129 130 static int emac_ifmedia_upd(struct ifnet *); 131 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *); 132 133 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 134 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS); 135 136 #define EMAC_READ_REG(sc, reg) \ 137 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg) 138 #define EMAC_WRITE_REG(sc, reg, val) \ 139 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val) 140 141 static void 142 emac_sys_setup(void) 143 { 144 145 /* Activate EMAC clock. */ 146 a10_clk_emac_activate(); 147 /* Map sram. */ 148 a10_map_to_emac(); 149 } 150 151 static void 152 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr) 153 { 154 uint32_t val0, val1, rnd; 155 156 /* 157 * Try to get MAC address from running hardware. 158 * If there is something non-zero there just use it. 159 * 160 * Otherwise set the address to a convenient locally assigned address, 161 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 162 * assigned bit set, and the broadcast/multicast bit clear. 163 */ 164 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0); 165 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1); 166 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) { 167 hwaddr[0] = (val1 >> 16) & 0xff; 168 hwaddr[1] = (val1 >> 8) & 0xff; 169 hwaddr[2] = (val1 >> 0) & 0xff; 170 hwaddr[3] = (val0 >> 16) & 0xff; 171 hwaddr[4] = (val0 >> 8) & 0xff; 172 hwaddr[5] = (val0 >> 0) & 0xff; 173 } else { 174 rnd = arc4random() & 0x00ffffff; 175 hwaddr[0] = 'b'; 176 hwaddr[1] = 's'; 177 hwaddr[2] = 'd'; 178 hwaddr[3] = (rnd >> 16) & 0xff; 179 hwaddr[4] = (rnd >> 8) & 0xff; 180 hwaddr[5] = (rnd >> 0) & 0xff; 181 } 182 if (bootverbose) 183 printf("MAC address: %s\n", ether_sprintf(hwaddr)); 184 } 185 186 static void 187 emac_set_rx_mode(struct emac_softc *sc) 188 { 189 struct ifnet *ifp; 190 struct ifmultiaddr *ifma; 191 uint32_t h, hashes[2]; 192 uint32_t rcr = 0; 193 194 EMAC_ASSERT_LOCKED(sc); 195 196 ifp = sc->emac_ifp; 197 198 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); 199 200 /* Unicast packet and DA filtering */ 201 rcr |= EMAC_RX_UCAD; 202 rcr |= EMAC_RX_DAF; 203 204 hashes[0] = 0; 205 hashes[1] = 0; 206 if (ifp->if_flags & IFF_ALLMULTI) { 207 hashes[0] = 0xffffffff; 208 hashes[1] = 0xffffffff; 209 } else { 210 if_maddr_rlock(ifp); 211 TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) { 212 if (ifma->ifma_addr->sa_family != AF_LINK) 213 continue; 214 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 215 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 216 hashes[h >> 5] |= 1 << (h & 0x1f); 217 } 218 if_maddr_runlock(ifp); 219 } 220 rcr |= EMAC_RX_MCO; 221 rcr |= EMAC_RX_MHF; 222 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]); 223 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]); 224 225 if (ifp->if_flags & IFF_BROADCAST) { 226 rcr |= EMAC_RX_BCO; 227 rcr |= EMAC_RX_MCO; 228 } 229 230 if (ifp->if_flags & IFF_PROMISC) 231 rcr |= EMAC_RX_PA; 232 else 233 rcr |= EMAC_RX_UCAD; 234 235 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr); 236 } 237 238 static void 239 emac_reset(struct emac_softc *sc) 240 { 241 242 EMAC_WRITE_REG(sc, EMAC_CTL, 0); 243 DELAY(200); 244 EMAC_WRITE_REG(sc, EMAC_CTL, 1); 245 DELAY(200); 246 } 247 248 static void 249 emac_drain_rxfifo(struct emac_softc *sc) 250 { 251 uint32_t data; 252 253 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0) 254 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 255 } 256 257 static void 258 emac_txeof(struct emac_softc *sc, uint32_t status) 259 { 260 struct ifnet *ifp; 261 262 EMAC_ASSERT_LOCKED(sc); 263 264 ifp = sc->emac_ifp; 265 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1); 266 sc->emac_fifo_mask &= ~status; 267 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 268 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2); 269 else 270 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 271 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 272 273 /* Unarm watchdog timer if no TX */ 274 sc->emac_watchdog_timer = 0; 275 } 276 277 static void 278 emac_rxeof(struct emac_softc *sc, int count) 279 { 280 struct ifnet *ifp; 281 struct mbuf *m, *m0; 282 uint32_t reg_val, rxcount; 283 int16_t len; 284 uint16_t status; 285 int i; 286 287 ifp = sc->emac_ifp; 288 for (; count > 0 && 289 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) { 290 /* 291 * Race warning: The first packet might arrive with 292 * the interrupts disabled, but the second will fix 293 */ 294 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 295 if (!rxcount) { 296 /* Had one stuck? */ 297 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 298 if (!rxcount) 299 return; 300 } 301 /* Check packet header */ 302 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 303 if (reg_val != EMAC_PACKET_HEADER) { 304 /* Packet header is wrong */ 305 if (bootverbose) 306 if_printf(ifp, "wrong packet header\n"); 307 /* Disable RX */ 308 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 309 reg_val &= ~EMAC_CTL_RX_EN; 310 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 311 312 /* Flush RX FIFO */ 313 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 314 reg_val |= EMAC_RX_FLUSH_FIFO; 315 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 316 for (i = 100; i > 0; i--) { 317 DELAY(100); 318 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) & 319 EMAC_RX_FLUSH_FIFO) == 0) 320 break; 321 } 322 if (i == 0) { 323 device_printf(sc->emac_dev, 324 "flush FIFO timeout\n"); 325 /* Reinitialize controller */ 326 emac_init_locked(sc); 327 return; 328 } 329 /* Enable RX */ 330 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 331 reg_val |= EMAC_CTL_RX_EN; 332 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 333 334 return; 335 } 336 337 /* Get packet size and status */ 338 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 339 len = reg_val & 0xffff; 340 status = (reg_val >> 16) & 0xffff; 341 342 if (len < 64 || (status & EMAC_PKT_OK) == 0) { 343 if (bootverbose) 344 if_printf(ifp, 345 "bad packet: len = %i status = %i\n", 346 len, status); 347 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 348 emac_drain_rxfifo(sc); 349 continue; 350 } 351 #if 0 352 if (status & (EMAC_CRCERR | EMAC_LENERR)) { 353 good_packet = 0; 354 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 355 if (status & EMAC_CRCERR) 356 if_printf(ifp, "crc error\n"); 357 if (status & EMAC_LENERR) 358 if_printf(ifp, "length error\n"); 359 } 360 #endif 361 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 362 if (m == NULL) { 363 emac_drain_rxfifo(sc); 364 return; 365 } 366 m->m_len = m->m_pkthdr.len = MCLBYTES; 367 368 /* Copy entire frame to mbuf first. */ 369 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle, 370 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4); 371 372 m->m_pkthdr.rcvif = ifp; 373 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN; 374 375 /* 376 * Emac controller needs strict aligment, so to avoid 377 * copying over an entire frame to align, we allocate 378 * a new mbuf and copy ethernet header + IP header to 379 * the new mbuf. The new mbuf is prepended into the 380 * existing mbuf chain. 381 */ 382 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) { 383 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 384 m->m_data += ETHER_HDR_LEN; 385 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) && 386 m->m_len > (MHLEN - ETHER_HDR_LEN)) { 387 MGETHDR(m0, M_NOWAIT, MT_DATA); 388 if (m0 != NULL) { 389 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen; 390 bcopy(m->m_data, m0->m_data, len); 391 m->m_data += len; 392 m->m_len -= len; 393 m0->m_len = len; 394 M_MOVE_PKTHDR(m0, m); 395 m0->m_next = m; 396 m = m0; 397 } else { 398 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 399 m_freem(m); 400 m = NULL; 401 continue; 402 } 403 } else if (m->m_len > EMAC_MAC_MAXF) { 404 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 405 m_freem(m); 406 m = NULL; 407 continue; 408 } 409 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 410 EMAC_UNLOCK(sc); 411 (*ifp->if_input)(ifp, m); 412 EMAC_LOCK(sc); 413 } 414 } 415 416 static void 417 emac_watchdog(struct emac_softc *sc) 418 { 419 struct ifnet *ifp; 420 421 EMAC_ASSERT_LOCKED(sc); 422 423 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer) 424 return; 425 426 ifp = sc->emac_ifp; 427 428 if (sc->emac_link == 0) { 429 if (bootverbose) 430 if_printf(sc->emac_ifp, "watchdog timeout " 431 "(missed link)\n"); 432 } else 433 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n"); 434 435 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 436 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 437 emac_init_locked(sc); 438 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 439 emac_start_locked(ifp); 440 } 441 442 static void 443 emac_tick(void *arg) 444 { 445 struct emac_softc *sc; 446 struct mii_data *mii; 447 448 sc = (struct emac_softc *)arg; 449 mii = device_get_softc(sc->emac_miibus); 450 mii_tick(mii); 451 452 emac_watchdog(sc); 453 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 454 } 455 456 static void 457 emac_init(void *xcs) 458 { 459 struct emac_softc *sc; 460 461 sc = (struct emac_softc *)xcs; 462 EMAC_LOCK(sc); 463 emac_init_locked(sc); 464 EMAC_UNLOCK(sc); 465 } 466 467 static void 468 emac_init_locked(struct emac_softc *sc) 469 { 470 struct ifnet *ifp; 471 struct mii_data *mii; 472 uint32_t reg_val; 473 uint8_t *eaddr; 474 475 EMAC_ASSERT_LOCKED(sc); 476 477 ifp = sc->emac_ifp; 478 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 479 return; 480 481 /* Flush RX FIFO */ 482 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 483 reg_val |= EMAC_RX_FLUSH_FIFO; 484 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 485 DELAY(1); 486 487 /* Soft reset MAC */ 488 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 489 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); 490 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 491 492 /* Set MII clock */ 493 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); 494 reg_val &= (~(0xf << 2)); 495 reg_val |= (0xd << 2); 496 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); 497 498 /* Clear RX counter */ 499 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); 500 501 /* Disable all interrupt and clear interrupt status */ 502 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 503 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 504 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 505 DELAY(1); 506 507 /* Set up TX */ 508 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); 509 reg_val |= EMAC_TX_AB_M; 510 reg_val &= EMAC_TX_TM; 511 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); 512 513 /* Set up RX */ 514 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 515 reg_val |= EMAC_RX_SETUP; 516 reg_val &= EMAC_RX_TM; 517 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 518 519 /* Set up MAC CTL0. */ 520 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 521 reg_val |= EMAC_MAC_CTL0_SETUP; 522 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 523 524 /* Set up MAC CTL1. */ 525 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1); 526 reg_val |= EMAC_MAC_CTL1_SETUP; 527 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val); 528 529 /* Set up IPGT */ 530 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD); 531 532 /* Set up IPGR */ 533 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 | 534 (EMAC_MAC_NBTB_IPG1 << 8)); 535 536 /* Set up Collison window */ 537 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8)); 538 539 /* Set up Max Frame Length */ 540 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL); 541 542 /* Setup ethernet address */ 543 eaddr = IF_LLADDR(ifp); 544 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 | 545 eaddr[1] << 8 | eaddr[2]); 546 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 | 547 eaddr[4] << 8 | eaddr[5]); 548 549 /* Setup rx filter */ 550 emac_set_rx_mode(sc); 551 552 /* Enable RX/TX0/RX Hlevel interrupt */ 553 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 554 reg_val |= EMAC_INT_EN; 555 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 556 557 ifp->if_drv_flags |= IFF_DRV_RUNNING; 558 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 559 560 sc->emac_link = 0; 561 562 /* Switch to the current media. */ 563 mii = device_get_softc(sc->emac_miibus); 564 mii_mediachg(mii); 565 566 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 567 } 568 569 570 static void 571 emac_start(struct ifnet *ifp) 572 { 573 struct emac_softc *sc; 574 575 sc = ifp->if_softc; 576 EMAC_LOCK(sc); 577 emac_start_locked(ifp); 578 EMAC_UNLOCK(sc); 579 } 580 581 static void 582 emac_start_locked(struct ifnet *ifp) 583 { 584 struct emac_softc *sc; 585 struct mbuf *m, *m0; 586 uint32_t fifo, reg; 587 588 sc = ifp->if_softc; 589 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 590 return; 591 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 592 return; 593 if (sc->emac_link == 0) 594 return; 595 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 596 if (m == NULL) 597 return; 598 599 /* Select channel */ 600 if (sc->emac_fifo_mask & EMAC_TX_FIFO0) 601 fifo = 1; 602 else 603 fifo = 0; 604 sc->emac_fifo_mask |= (1 << fifo); 605 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 606 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 607 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo); 608 609 /* 610 * Emac controller wants 4 byte aligned TX buffers. 611 * We have to copy pretty much all the time. 612 */ 613 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) { 614 m0 = m_defrag(m, M_NOWAIT); 615 if (m0 == NULL) { 616 m_freem(m); 617 m = NULL; 618 return; 619 } 620 m = m0; 621 } 622 /* Write data */ 623 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle, 624 EMAC_TX_IO_DATA, mtod(m, uint32_t *), 625 roundup2(m->m_len, 4) / 4); 626 627 /* Send the data lengh. */ 628 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1; 629 EMAC_WRITE_REG(sc, reg, m->m_len); 630 631 /* Start translate from fifo to phy. */ 632 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1; 633 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1); 634 635 /* Set timeout */ 636 sc->emac_watchdog_timer = 5; 637 638 /* Data have been sent to hardware, it is okay to free the mbuf now. */ 639 BPF_MTAP(ifp, m); 640 m_freem(m); 641 } 642 643 static void 644 emac_stop_locked(struct emac_softc *sc) 645 { 646 struct ifnet *ifp; 647 uint32_t reg_val; 648 649 EMAC_ASSERT_LOCKED(sc); 650 651 ifp = sc->emac_ifp; 652 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 653 sc->emac_link = 0; 654 655 /* Disable all interrupt and clear interrupt status */ 656 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 657 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 658 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 659 660 /* Disable RX/TX */ 661 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 662 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 663 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 664 665 callout_stop(&sc->emac_tick_ch); 666 } 667 668 static void 669 emac_intr(void *arg) 670 { 671 struct emac_softc *sc; 672 struct ifnet *ifp; 673 uint32_t reg_val; 674 675 sc = (struct emac_softc *)arg; 676 EMAC_LOCK(sc); 677 678 /* Disable all interrupts */ 679 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 680 /* Get EMAC interrupt status */ 681 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 682 /* Clear ISR status */ 683 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 684 685 /* Received incoming packet */ 686 if (reg_val & EMAC_INT_STA_RX) 687 emac_rxeof(sc, sc->emac_rx_process_limit); 688 689 /* Transmit Interrupt check */ 690 if (reg_val & EMAC_INT_STA_TX) { 691 emac_txeof(sc, reg_val); 692 ifp = sc->emac_ifp; 693 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 694 emac_start_locked(ifp); 695 } 696 697 /* Re-enable interrupt mask */ 698 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 699 reg_val |= EMAC_INT_EN; 700 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 701 EMAC_UNLOCK(sc); 702 } 703 704 static int 705 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 706 { 707 struct emac_softc *sc; 708 struct mii_data *mii; 709 struct ifreq *ifr; 710 int error = 0; 711 712 sc = ifp->if_softc; 713 ifr = (struct ifreq *)data; 714 715 switch (command) { 716 case SIOCSIFFLAGS: 717 EMAC_LOCK(sc); 718 if (ifp->if_flags & IFF_UP) { 719 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 720 if ((ifp->if_flags ^ sc->emac_if_flags) & 721 (IFF_PROMISC | IFF_ALLMULTI)) 722 emac_set_rx_mode(sc); 723 } else 724 emac_init_locked(sc); 725 } else { 726 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 727 emac_stop_locked(sc); 728 } 729 sc->emac_if_flags = ifp->if_flags; 730 EMAC_UNLOCK(sc); 731 break; 732 case SIOCADDMULTI: 733 case SIOCDELMULTI: 734 EMAC_LOCK(sc); 735 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 736 emac_set_rx_mode(sc); 737 } 738 EMAC_UNLOCK(sc); 739 break; 740 case SIOCGIFMEDIA: 741 case SIOCSIFMEDIA: 742 mii = device_get_softc(sc->emac_miibus); 743 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 744 break; 745 default: 746 error = ether_ioctl(ifp, command, data); 747 break; 748 } 749 return (error); 750 } 751 752 static int 753 emac_probe(device_t dev) 754 { 755 756 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac")) 757 return (ENXIO); 758 759 device_set_desc(dev, "A10/A20 EMAC ethernet controller"); 760 return (BUS_PROBE_DEFAULT); 761 } 762 763 static int 764 emac_detach(device_t dev) 765 { 766 struct emac_softc *sc; 767 768 sc = device_get_softc(dev); 769 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 770 if (device_is_attached(dev)) { 771 ether_ifdetach(sc->emac_ifp); 772 EMAC_LOCK(sc); 773 emac_stop_locked(sc); 774 EMAC_UNLOCK(sc); 775 callout_drain(&sc->emac_tick_ch); 776 } 777 778 if (sc->emac_intrhand != NULL) 779 bus_teardown_intr(sc->emac_dev, sc->emac_irq, 780 sc->emac_intrhand); 781 782 if (sc->emac_miibus != NULL) { 783 device_delete_child(sc->emac_dev, sc->emac_miibus); 784 bus_generic_detach(sc->emac_dev); 785 } 786 787 if (sc->emac_res != NULL) 788 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res); 789 790 if (sc->emac_irq != NULL) 791 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq); 792 793 if (sc->emac_ifp != NULL) 794 if_free(sc->emac_ifp); 795 796 if (mtx_initialized(&sc->emac_mtx)) 797 mtx_destroy(&sc->emac_mtx); 798 799 return (0); 800 } 801 802 static int 803 emac_shutdown(device_t dev) 804 { 805 806 return (emac_suspend(dev)); 807 } 808 809 static int 810 emac_suspend(device_t dev) 811 { 812 struct emac_softc *sc; 813 struct ifnet *ifp; 814 815 sc = device_get_softc(dev); 816 817 EMAC_LOCK(sc); 818 ifp = sc->emac_ifp; 819 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 820 emac_stop_locked(sc); 821 EMAC_UNLOCK(sc); 822 823 return (0); 824 } 825 826 static int 827 emac_resume(device_t dev) 828 { 829 struct emac_softc *sc; 830 struct ifnet *ifp; 831 832 sc = device_get_softc(dev); 833 834 EMAC_LOCK(sc); 835 ifp = sc->emac_ifp; 836 if ((ifp->if_flags & IFF_UP) != 0) { 837 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 838 emac_init_locked(sc); 839 } 840 EMAC_UNLOCK(sc); 841 842 return (0); 843 } 844 845 static int 846 emac_attach(device_t dev) 847 { 848 struct emac_softc *sc; 849 struct ifnet *ifp; 850 int error, rid; 851 uint8_t eaddr[ETHER_ADDR_LEN]; 852 853 sc = device_get_softc(dev); 854 sc->emac_dev = dev; 855 856 error = 0; 857 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 858 MTX_DEF); 859 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0); 860 861 rid = 0; 862 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 863 RF_ACTIVE); 864 if (sc->emac_res == NULL) { 865 device_printf(dev, "unable to map memory\n"); 866 error = ENXIO; 867 goto fail; 868 } 869 870 sc->emac_tag = rman_get_bustag(sc->emac_res); 871 sc->emac_handle = rman_get_bushandle(sc->emac_res); 872 873 rid = 0; 874 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 875 RF_SHAREABLE | RF_ACTIVE); 876 if (sc->emac_irq == NULL) { 877 device_printf(dev, "cannot allocate IRQ resources.\n"); 878 error = ENXIO; 879 goto fail; 880 } 881 /* Create device sysctl node. */ 882 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 883 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 884 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 885 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I", 886 "max number of Rx events to process"); 887 888 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 889 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 890 "process_limit", &sc->emac_rx_process_limit); 891 if (error == 0) { 892 if (sc->emac_rx_process_limit < EMAC_PROC_MIN || 893 sc->emac_rx_process_limit > EMAC_PROC_MAX) { 894 device_printf(dev, "process_limit value out of range; " 895 "using default: %d\n", EMAC_PROC_DEFAULT); 896 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 897 } 898 } 899 /* Setup EMAC */ 900 emac_sys_setup(); 901 emac_reset(sc); 902 903 ifp = sc->emac_ifp = if_alloc(IFT_ETHER); 904 if (ifp == NULL) { 905 device_printf(dev, "unable to allocate ifp\n"); 906 error = ENOSPC; 907 goto fail; 908 } 909 ifp->if_softc = sc; 910 911 /* Setup MII */ 912 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd, 913 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 914 if (error != 0) { 915 device_printf(dev, "PHY probe failed\n"); 916 goto fail; 917 } 918 919 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 920 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 921 ifp->if_start = emac_start; 922 ifp->if_ioctl = emac_ioctl; 923 ifp->if_init = emac_init; 924 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 925 926 /* Get MAC address */ 927 emac_get_hwaddr(sc, eaddr); 928 ether_ifattach(ifp, eaddr); 929 930 /* VLAN capability setup. */ 931 ifp->if_capabilities |= IFCAP_VLAN_MTU; 932 ifp->if_capenable = ifp->if_capabilities; 933 /* Tell the upper layer we support VLAN over-sized frames. */ 934 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 935 936 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE, 937 NULL, emac_intr, sc, &sc->emac_intrhand); 938 if (error != 0) { 939 device_printf(dev, "could not set up interrupt handler.\n"); 940 ether_ifdetach(ifp); 941 goto fail; 942 } 943 944 fail: 945 if (error != 0) 946 emac_detach(dev); 947 return (error); 948 } 949 950 static boolean_t 951 emac_miibus_iowait(struct emac_softc *sc) 952 { 953 uint32_t timeout; 954 955 for (timeout = 100; timeout != 0; --timeout) { 956 DELAY(100); 957 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0) 958 return (true); 959 } 960 961 return (false); 962 } 963 964 /* 965 * The MII bus interface 966 */ 967 static int 968 emac_miibus_readreg(device_t dev, int phy, int reg) 969 { 970 struct emac_softc *sc; 971 int rval; 972 973 sc = device_get_softc(dev); 974 975 /* Issue phy address and reg */ 976 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 977 /* Pull up the phy io line */ 978 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 979 if (!emac_miibus_iowait(sc)) { 980 device_printf(dev, "timeout waiting for mii read\n"); 981 return (0); 982 } 983 /* Push down the phy io line */ 984 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 985 /* Read data */ 986 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD); 987 988 return (rval); 989 } 990 991 static int 992 emac_miibus_writereg(device_t dev, int phy, int reg, int data) 993 { 994 struct emac_softc *sc; 995 996 sc = device_get_softc(dev); 997 998 /* Issue phy address and reg */ 999 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1000 /* Write data */ 1001 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data); 1002 /* Pull up the phy io line */ 1003 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1004 if (!emac_miibus_iowait(sc)) { 1005 device_printf(dev, "timeout waiting for mii write\n"); 1006 return (0); 1007 } 1008 /* Push down the phy io line */ 1009 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1010 1011 return (0); 1012 } 1013 1014 static void 1015 emac_miibus_statchg(device_t dev) 1016 { 1017 struct emac_softc *sc; 1018 struct mii_data *mii; 1019 struct ifnet *ifp; 1020 uint32_t reg_val; 1021 1022 sc = device_get_softc(dev); 1023 1024 mii = device_get_softc(sc->emac_miibus); 1025 ifp = sc->emac_ifp; 1026 if (mii == NULL || ifp == NULL || 1027 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1028 return; 1029 1030 sc->emac_link = 0; 1031 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1032 (IFM_ACTIVE | IFM_AVALID)) { 1033 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1034 case IFM_10_T: 1035 case IFM_100_TX: 1036 sc->emac_link = 1; 1037 break; 1038 default: 1039 break; 1040 } 1041 } 1042 /* Program MACs with resolved speed/duplex. */ 1043 if (sc->emac_link != 0) { 1044 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT); 1045 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1046 reg_val &= ~EMAC_MAC_IPGT_HD; 1047 reg_val |= EMAC_MAC_IPGT_FD; 1048 } else { 1049 reg_val &= ~EMAC_MAC_IPGT_FD; 1050 reg_val |= EMAC_MAC_IPGT_HD; 1051 } 1052 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val); 1053 /* Enable RX/TX */ 1054 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1055 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN; 1056 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1057 } else { 1058 /* Disable RX/TX */ 1059 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1060 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 1061 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1062 } 1063 } 1064 1065 static int 1066 emac_ifmedia_upd(struct ifnet *ifp) 1067 { 1068 struct emac_softc *sc; 1069 struct mii_data *mii; 1070 struct mii_softc *miisc; 1071 int error; 1072 1073 sc = ifp->if_softc; 1074 mii = device_get_softc(sc->emac_miibus); 1075 EMAC_LOCK(sc); 1076 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1077 PHY_RESET(miisc); 1078 error = mii_mediachg(mii); 1079 EMAC_UNLOCK(sc); 1080 1081 return (error); 1082 } 1083 1084 static void 1085 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1086 { 1087 struct emac_softc *sc; 1088 struct mii_data *mii; 1089 1090 sc = ifp->if_softc; 1091 mii = device_get_softc(sc->emac_miibus); 1092 1093 EMAC_LOCK(sc); 1094 mii_pollstat(mii); 1095 ifmr->ifm_active = mii->mii_media_active; 1096 ifmr->ifm_status = mii->mii_media_status; 1097 EMAC_UNLOCK(sc); 1098 } 1099 1100 static device_method_t emac_methods[] = { 1101 /* Device interface */ 1102 DEVMETHOD(device_probe, emac_probe), 1103 DEVMETHOD(device_attach, emac_attach), 1104 DEVMETHOD(device_detach, emac_detach), 1105 DEVMETHOD(device_shutdown, emac_shutdown), 1106 DEVMETHOD(device_suspend, emac_suspend), 1107 DEVMETHOD(device_resume, emac_resume), 1108 1109 /* bus interface, for miibus */ 1110 DEVMETHOD(bus_print_child, bus_generic_print_child), 1111 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1112 1113 /* MII interface */ 1114 DEVMETHOD(miibus_readreg, emac_miibus_readreg), 1115 DEVMETHOD(miibus_writereg, emac_miibus_writereg), 1116 DEVMETHOD(miibus_statchg, emac_miibus_statchg), 1117 1118 DEVMETHOD_END 1119 }; 1120 1121 static driver_t emac_driver = { 1122 "emac", 1123 emac_methods, 1124 sizeof(struct emac_softc) 1125 }; 1126 1127 static devclass_t emac_devclass; 1128 1129 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0); 1130 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0); 1131 MODULE_DEPEND(emac, miibus, 1, 1, 1); 1132 MODULE_DEPEND(emac, ether, 1, 1, 1); 1133 1134 static int 1135 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 1136 { 1137 int error, value; 1138 1139 if (arg1 == NULL) 1140 return (EINVAL); 1141 value = *(int *)arg1; 1142 error = sysctl_handle_int(oidp, &value, 0, req); 1143 if (error || req->newptr == NULL) 1144 return (error); 1145 if (value < low || value > high) 1146 return (EINVAL); 1147 *(int *)arg1 = value; 1148 1149 return (0); 1150 } 1151 1152 static int 1153 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS) 1154 { 1155 1156 return (sysctl_int_range(oidp, arg1, arg2, req, 1157 EMAC_PROC_MIN, EMAC_PROC_MAX)); 1158 } 1159