1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_device_polling.h" 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/rman.h> 42 #include <sys/kernel.h> 43 #include <sys/endian.h> 44 #include <sys/mbuf.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/module.h> 48 #include <sys/taskqueue.h> 49 #include <sys/gpio.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_var.h> 58 59 #include <machine/bus.h> 60 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 64 #include <arm/allwinner/if_awgreg.h> 65 #include <arm/allwinner/aw_sid.h> 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/extres/clk/clk.h> 70 #include <dev/extres/hwreset/hwreset.h> 71 #include <dev/extres/regulator/regulator.h> 72 #include <dev/extres/syscon/syscon.h> 73 74 #include "syscon_if.h" 75 #include "miibus_if.h" 76 #include "gpio_if.h" 77 78 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg)) 79 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val)) 80 81 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx) 82 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx); 83 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 84 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 85 86 #define DESC_ALIGN 4 87 #define TX_DESC_COUNT 1024 88 #define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT) 89 #define RX_DESC_COUNT 256 90 #define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT) 91 92 #define DESC_OFF(n) ((n) * sizeof(struct emac_desc)) 93 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 94 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 95 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 96 97 #define TX_MAX_SEGS 20 98 99 #define SOFT_RST_RETRY 1000 100 #define MII_BUSY_RETRY 1000 101 #define MDIO_FREQ 2500000 102 103 #define BURST_LEN_DEFAULT 8 104 #define RX_TX_PRI_DEFAULT 0 105 #define PAUSE_TIME_DEFAULT 0x400 106 #define TX_INTERVAL_DEFAULT 64 107 #define RX_BATCH_DEFAULT 64 108 109 /* syscon EMAC clock register */ 110 #define EMAC_CLK_REG 0x30 111 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 112 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 113 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 114 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 115 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 116 #define EMAC_CLK_RMII_EN (1 << 13) 117 #define EMAC_CLK_ETXDC (0x7 << 10) 118 #define EMAC_CLK_ETXDC_SHIFT 10 119 #define EMAC_CLK_ERXDC (0x1f << 5) 120 #define EMAC_CLK_ERXDC_SHIFT 5 121 #define EMAC_CLK_PIT (0x1 << 2) 122 #define EMAC_CLK_PIT_MII (0 << 2) 123 #define EMAC_CLK_PIT_RGMII (1 << 2) 124 #define EMAC_CLK_SRC (0x3 << 0) 125 #define EMAC_CLK_SRC_MII (0 << 0) 126 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 127 #define EMAC_CLK_SRC_RGMII (2 << 0) 128 129 /* Burst length of RX and TX DMA transfers */ 130 static int awg_burst_len = BURST_LEN_DEFAULT; 131 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len); 132 133 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 134 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT; 135 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri); 136 137 /* Pause time field in the transmitted control frame */ 138 static int awg_pause_time = PAUSE_TIME_DEFAULT; 139 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time); 140 141 /* Request a TX interrupt every <n> descriptors */ 142 static int awg_tx_interval = TX_INTERVAL_DEFAULT; 143 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval); 144 145 /* Maximum number of mbufs to send to if_input */ 146 static int awg_rx_batch = RX_BATCH_DEFAULT; 147 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch); 148 149 enum awg_type { 150 EMAC_A83T = 1, 151 EMAC_H3, 152 EMAC_A64, 153 }; 154 155 static struct ofw_compat_data compat_data[] = { 156 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 157 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 158 { "allwinner,sun50i-a64-emac", EMAC_A64 }, 159 { NULL, 0 } 160 }; 161 162 struct awg_bufmap { 163 bus_dmamap_t map; 164 struct mbuf *mbuf; 165 }; 166 167 struct awg_txring { 168 bus_dma_tag_t desc_tag; 169 bus_dmamap_t desc_map; 170 struct emac_desc *desc_ring; 171 bus_addr_t desc_ring_paddr; 172 bus_dma_tag_t buf_tag; 173 struct awg_bufmap buf_map[TX_DESC_COUNT]; 174 u_int cur, next, queued; 175 u_int segs; 176 }; 177 178 struct awg_rxring { 179 bus_dma_tag_t desc_tag; 180 bus_dmamap_t desc_map; 181 struct emac_desc *desc_ring; 182 bus_addr_t desc_ring_paddr; 183 bus_dma_tag_t buf_tag; 184 struct awg_bufmap buf_map[RX_DESC_COUNT]; 185 bus_dmamap_t buf_spare_map; 186 u_int cur; 187 }; 188 189 enum { 190 _RES_EMAC, 191 _RES_IRQ, 192 _RES_SYSCON, 193 _RES_NITEMS 194 }; 195 196 struct awg_softc { 197 struct resource *res[_RES_NITEMS]; 198 struct mtx mtx; 199 if_t ifp; 200 device_t dev; 201 device_t miibus; 202 struct callout stat_ch; 203 struct task link_task; 204 void *ih; 205 u_int mdc_div_ratio_m; 206 int link; 207 int if_flags; 208 enum awg_type type; 209 struct syscon *syscon; 210 211 struct awg_txring tx; 212 struct awg_rxring rx; 213 }; 214 215 static struct resource_spec awg_spec[] = { 216 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 217 { SYS_RES_IRQ, 0, RF_ACTIVE }, 218 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 219 { -1, 0 } 220 }; 221 222 static void awg_txeof(struct awg_softc *sc); 223 224 static int awg_parse_delay(device_t dev, uint32_t *tx_delay, 225 uint32_t *rx_delay); 226 static uint32_t syscon_read_emac_clk_reg(device_t dev); 227 static void syscon_write_emac_clk_reg(device_t dev, uint32_t val); 228 static phandle_t awg_get_phy_node(device_t dev); 229 static bool awg_has_internal_phy(device_t dev); 230 231 static int 232 awg_miibus_readreg(device_t dev, int phy, int reg) 233 { 234 struct awg_softc *sc; 235 int retry, val; 236 237 sc = device_get_softc(dev); 238 val = 0; 239 240 WR4(sc, EMAC_MII_CMD, 241 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 242 (phy << PHY_ADDR_SHIFT) | 243 (reg << PHY_REG_ADDR_SHIFT) | 244 MII_BUSY); 245 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 246 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 247 val = RD4(sc, EMAC_MII_DATA); 248 break; 249 } 250 DELAY(10); 251 } 252 253 if (retry == 0) 254 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 255 phy, reg); 256 257 return (val); 258 } 259 260 static int 261 awg_miibus_writereg(device_t dev, int phy, int reg, int val) 262 { 263 struct awg_softc *sc; 264 int retry; 265 266 sc = device_get_softc(dev); 267 268 WR4(sc, EMAC_MII_DATA, val); 269 WR4(sc, EMAC_MII_CMD, 270 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 271 (phy << PHY_ADDR_SHIFT) | 272 (reg << PHY_REG_ADDR_SHIFT) | 273 MII_WR | MII_BUSY); 274 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 275 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 276 break; 277 DELAY(10); 278 } 279 280 if (retry == 0) 281 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 282 phy, reg); 283 284 return (0); 285 } 286 287 static void 288 awg_update_link_locked(struct awg_softc *sc) 289 { 290 struct mii_data *mii; 291 uint32_t val; 292 293 AWG_ASSERT_LOCKED(sc); 294 295 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) 296 return; 297 mii = device_get_softc(sc->miibus); 298 299 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 300 (IFM_ACTIVE | IFM_AVALID)) { 301 switch (IFM_SUBTYPE(mii->mii_media_active)) { 302 case IFM_1000_T: 303 case IFM_1000_SX: 304 case IFM_100_TX: 305 case IFM_10_T: 306 sc->link = 1; 307 break; 308 default: 309 sc->link = 0; 310 break; 311 } 312 } else 313 sc->link = 0; 314 315 if (sc->link == 0) 316 return; 317 318 val = RD4(sc, EMAC_BASIC_CTL_0); 319 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 320 321 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 322 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 323 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 324 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 325 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 326 else 327 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 328 329 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 330 val |= BASIC_CTL_DUPLEX; 331 332 WR4(sc, EMAC_BASIC_CTL_0, val); 333 334 val = RD4(sc, EMAC_RX_CTL_0); 335 val &= ~RX_FLOW_CTL_EN; 336 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 337 val |= RX_FLOW_CTL_EN; 338 WR4(sc, EMAC_RX_CTL_0, val); 339 340 val = RD4(sc, EMAC_TX_FLOW_CTL); 341 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 342 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 343 val |= TX_FLOW_CTL_EN; 344 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 345 val |= awg_pause_time << PAUSE_TIME_SHIFT; 346 WR4(sc, EMAC_TX_FLOW_CTL, val); 347 } 348 349 static void 350 awg_link_task(void *arg, int pending) 351 { 352 struct awg_softc *sc; 353 354 sc = arg; 355 356 AWG_LOCK(sc); 357 awg_update_link_locked(sc); 358 AWG_UNLOCK(sc); 359 } 360 361 static void 362 awg_miibus_statchg(device_t dev) 363 { 364 struct awg_softc *sc; 365 366 sc = device_get_softc(dev); 367 368 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 369 } 370 371 static void 372 awg_media_status(if_t ifp, struct ifmediareq *ifmr) 373 { 374 struct awg_softc *sc; 375 struct mii_data *mii; 376 377 sc = if_getsoftc(ifp); 378 mii = device_get_softc(sc->miibus); 379 380 AWG_LOCK(sc); 381 mii_pollstat(mii); 382 ifmr->ifm_active = mii->mii_media_active; 383 ifmr->ifm_status = mii->mii_media_status; 384 AWG_UNLOCK(sc); 385 } 386 387 static int 388 awg_media_change(if_t ifp) 389 { 390 struct awg_softc *sc; 391 struct mii_data *mii; 392 int error; 393 394 sc = if_getsoftc(ifp); 395 mii = device_get_softc(sc->miibus); 396 397 AWG_LOCK(sc); 398 error = mii_mediachg(mii); 399 AWG_UNLOCK(sc); 400 401 return (error); 402 } 403 404 static int 405 awg_encap(struct awg_softc *sc, struct mbuf **mp) 406 { 407 bus_dmamap_t map; 408 bus_dma_segment_t segs[TX_MAX_SEGS]; 409 int error, nsegs, cur, first, last, i; 410 u_int csum_flags; 411 uint32_t flags, status; 412 struct mbuf *m; 413 414 cur = first = sc->tx.cur; 415 map = sc->tx.buf_map[first].map; 416 417 m = *mp; 418 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs, 419 &nsegs, BUS_DMA_NOWAIT); 420 if (error == EFBIG) { 421 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS); 422 if (m == NULL) { 423 device_printf(sc->dev, "awg_encap: m_collapse failed\n"); 424 m_freem(*mp); 425 *mp = NULL; 426 return (ENOMEM); 427 } 428 *mp = m; 429 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, 430 segs, &nsegs, BUS_DMA_NOWAIT); 431 if (error != 0) { 432 m_freem(*mp); 433 *mp = NULL; 434 } 435 } 436 if (error != 0) { 437 device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n"); 438 return (error); 439 } 440 if (nsegs == 0) { 441 m_freem(*mp); 442 *mp = NULL; 443 return (EIO); 444 } 445 446 if (sc->tx.queued + nsegs > TX_DESC_COUNT) { 447 bus_dmamap_unload(sc->tx.buf_tag, map); 448 return (ENOBUFS); 449 } 450 451 bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE); 452 453 flags = TX_FIR_DESC; 454 status = 0; 455 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) { 456 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) 457 csum_flags = TX_CHECKSUM_CTL_FULL; 458 else 459 csum_flags = TX_CHECKSUM_CTL_IP; 460 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 461 } 462 463 for (i = 0; i < nsegs; i++) { 464 sc->tx.segs++; 465 if (i == nsegs - 1) { 466 flags |= TX_LAST_DESC; 467 /* 468 * Can only request TX completion 469 * interrupt on last descriptor. 470 */ 471 if (sc->tx.segs >= awg_tx_interval) { 472 sc->tx.segs = 0; 473 flags |= TX_INT_CTL; 474 } 475 } 476 477 sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr); 478 sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len); 479 sc->tx.desc_ring[cur].status = htole32(status); 480 481 flags &= ~TX_FIR_DESC; 482 /* 483 * Setting of the valid bit in the first descriptor is 484 * deferred until the whole chain is fully set up. 485 */ 486 status = TX_DESC_CTL; 487 488 ++sc->tx.queued; 489 cur = TX_NEXT(cur); 490 } 491 492 sc->tx.cur = cur; 493 494 /* Store mapping and mbuf in the last segment */ 495 last = TX_SKIP(cur, TX_DESC_COUNT - 1); 496 sc->tx.buf_map[first].map = sc->tx.buf_map[last].map; 497 sc->tx.buf_map[last].map = map; 498 sc->tx.buf_map[last].mbuf = m; 499 500 /* 501 * The whole mbuf chain has been DMA mapped, 502 * fix the first descriptor. 503 */ 504 sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL); 505 506 return (0); 507 } 508 509 static void 510 awg_clean_txbuf(struct awg_softc *sc, int index) 511 { 512 struct awg_bufmap *bmap; 513 514 --sc->tx.queued; 515 516 bmap = &sc->tx.buf_map[index]; 517 if (bmap->mbuf != NULL) { 518 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 519 BUS_DMASYNC_POSTWRITE); 520 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 521 m_freem(bmap->mbuf); 522 bmap->mbuf = NULL; 523 } 524 } 525 526 static void 527 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr) 528 { 529 uint32_t status, size; 530 531 status = RX_DESC_CTL; 532 size = MCLBYTES - 1; 533 534 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 535 sc->rx.desc_ring[index].size = htole32(size); 536 sc->rx.desc_ring[index].status = htole32(status); 537 } 538 539 static void 540 awg_reuse_rxdesc(struct awg_softc *sc, int index) 541 { 542 543 sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL); 544 } 545 546 static int 547 awg_newbuf_rx(struct awg_softc *sc, int index) 548 { 549 struct mbuf *m; 550 bus_dma_segment_t seg; 551 bus_dmamap_t map; 552 int nsegs; 553 554 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 555 if (m == NULL) 556 return (ENOBUFS); 557 558 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 559 m_adj(m, ETHER_ALIGN); 560 561 if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map, 562 m, &seg, &nsegs, BUS_DMA_NOWAIT) != 0) { 563 m_freem(m); 564 return (ENOBUFS); 565 } 566 567 if (sc->rx.buf_map[index].mbuf != NULL) { 568 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 569 BUS_DMASYNC_POSTREAD); 570 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 571 } 572 map = sc->rx.buf_map[index].map; 573 sc->rx.buf_map[index].map = sc->rx.buf_spare_map; 574 sc->rx.buf_spare_map = map; 575 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 576 BUS_DMASYNC_PREREAD); 577 578 sc->rx.buf_map[index].mbuf = m; 579 awg_setup_rxdesc(sc, index, seg.ds_addr); 580 581 return (0); 582 } 583 584 static void 585 awg_start_locked(struct awg_softc *sc) 586 { 587 struct mbuf *m; 588 uint32_t val; 589 if_t ifp; 590 int cnt, err; 591 592 AWG_ASSERT_LOCKED(sc); 593 594 if (!sc->link) 595 return; 596 597 ifp = sc->ifp; 598 599 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 600 IFF_DRV_RUNNING) 601 return; 602 603 for (cnt = 0; ; cnt++) { 604 m = if_dequeue(ifp); 605 if (m == NULL) 606 break; 607 608 err = awg_encap(sc, &m); 609 if (err != 0) { 610 if (err == ENOBUFS) 611 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 612 if (m != NULL) 613 if_sendq_prepend(ifp, m); 614 break; 615 } 616 if_bpfmtap(ifp, m); 617 } 618 619 if (cnt != 0) { 620 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 621 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 622 623 /* Start and run TX DMA */ 624 val = RD4(sc, EMAC_TX_CTL_1); 625 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 626 } 627 } 628 629 static void 630 awg_start(if_t ifp) 631 { 632 struct awg_softc *sc; 633 634 sc = if_getsoftc(ifp); 635 636 AWG_LOCK(sc); 637 awg_start_locked(sc); 638 AWG_UNLOCK(sc); 639 } 640 641 static void 642 awg_tick(void *softc) 643 { 644 struct awg_softc *sc; 645 struct mii_data *mii; 646 if_t ifp; 647 int link; 648 649 sc = softc; 650 ifp = sc->ifp; 651 mii = device_get_softc(sc->miibus); 652 653 AWG_ASSERT_LOCKED(sc); 654 655 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 656 return; 657 658 link = sc->link; 659 mii_tick(mii); 660 if (sc->link && !link) 661 awg_start_locked(sc); 662 663 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 664 } 665 666 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 667 static uint32_t 668 bitrev32(uint32_t x) 669 { 670 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 671 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 672 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 673 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 674 675 return (x >> 16) | (x << 16); 676 } 677 678 static u_int 679 awg_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 680 { 681 uint32_t crc, hashreg, hashbit, *hash = arg; 682 683 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7f; 684 crc = bitrev32(~crc) >> 26; 685 hashreg = (crc >> 5); 686 hashbit = (crc & 0x1f); 687 hash[hashreg] |= (1 << hashbit); 688 689 return (1); 690 } 691 692 static void 693 awg_setup_rxfilter(struct awg_softc *sc) 694 { 695 uint32_t val, hash[2], machi, maclo; 696 uint8_t *eaddr; 697 if_t ifp; 698 699 AWG_ASSERT_LOCKED(sc); 700 701 ifp = sc->ifp; 702 val = 0; 703 hash[0] = hash[1] = 0; 704 705 if (if_getflags(ifp) & IFF_PROMISC) 706 val |= DIS_ADDR_FILTER; 707 else if (if_getflags(ifp) & IFF_ALLMULTI) { 708 val |= RX_ALL_MULTICAST; 709 hash[0] = hash[1] = ~0; 710 } else if (if_foreach_llmaddr(ifp, awg_hash_maddr, hash) > 0) 711 val |= HASH_MULTICAST; 712 713 /* Write our unicast address */ 714 eaddr = IF_LLADDR(ifp); 715 machi = (eaddr[5] << 8) | eaddr[4]; 716 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 717 (eaddr[0] << 0); 718 WR4(sc, EMAC_ADDR_HIGH(0), machi); 719 WR4(sc, EMAC_ADDR_LOW(0), maclo); 720 721 /* Multicast hash filters */ 722 WR4(sc, EMAC_RX_HASH_0, hash[1]); 723 WR4(sc, EMAC_RX_HASH_1, hash[0]); 724 725 /* RX frame filter config */ 726 WR4(sc, EMAC_RX_FRM_FLT, val); 727 } 728 729 static void 730 awg_enable_intr(struct awg_softc *sc) 731 { 732 /* Enable interrupts */ 733 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 734 } 735 736 static void 737 awg_disable_intr(struct awg_softc *sc) 738 { 739 /* Disable interrupts */ 740 WR4(sc, EMAC_INT_EN, 0); 741 } 742 743 static void 744 awg_init_locked(struct awg_softc *sc) 745 { 746 struct mii_data *mii; 747 uint32_t val; 748 if_t ifp; 749 750 mii = device_get_softc(sc->miibus); 751 ifp = sc->ifp; 752 753 AWG_ASSERT_LOCKED(sc); 754 755 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 756 return; 757 758 awg_setup_rxfilter(sc); 759 760 /* Configure DMA burst length and priorities */ 761 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 762 if (awg_rx_tx_pri) 763 val |= BASIC_CTL_RX_TX_PRI; 764 WR4(sc, EMAC_BASIC_CTL_1, val); 765 766 /* Enable interrupts */ 767 #ifdef DEVICE_POLLING 768 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 769 awg_enable_intr(sc); 770 else 771 awg_disable_intr(sc); 772 #else 773 awg_enable_intr(sc); 774 #endif 775 776 /* Enable transmit DMA */ 777 val = RD4(sc, EMAC_TX_CTL_1); 778 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 779 780 /* Enable receive DMA */ 781 val = RD4(sc, EMAC_RX_CTL_1); 782 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 783 784 /* Enable transmitter */ 785 val = RD4(sc, EMAC_TX_CTL_0); 786 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 787 788 /* Enable receiver */ 789 val = RD4(sc, EMAC_RX_CTL_0); 790 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 791 792 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 793 794 mii_mediachg(mii); 795 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 796 } 797 798 static void 799 awg_init(void *softc) 800 { 801 struct awg_softc *sc; 802 803 sc = softc; 804 805 AWG_LOCK(sc); 806 awg_init_locked(sc); 807 AWG_UNLOCK(sc); 808 } 809 810 static void 811 awg_stop(struct awg_softc *sc) 812 { 813 if_t ifp; 814 uint32_t val; 815 int i; 816 817 AWG_ASSERT_LOCKED(sc); 818 819 ifp = sc->ifp; 820 821 callout_stop(&sc->stat_ch); 822 823 /* Stop transmit DMA and flush data in the TX FIFO */ 824 val = RD4(sc, EMAC_TX_CTL_1); 825 val &= ~TX_DMA_EN; 826 val |= FLUSH_TX_FIFO; 827 WR4(sc, EMAC_TX_CTL_1, val); 828 829 /* Disable transmitter */ 830 val = RD4(sc, EMAC_TX_CTL_0); 831 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 832 833 /* Disable receiver */ 834 val = RD4(sc, EMAC_RX_CTL_0); 835 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 836 837 /* Disable interrupts */ 838 awg_disable_intr(sc); 839 840 /* Disable transmit DMA */ 841 val = RD4(sc, EMAC_TX_CTL_1); 842 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 843 844 /* Disable receive DMA */ 845 val = RD4(sc, EMAC_RX_CTL_1); 846 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 847 848 sc->link = 0; 849 850 /* Finish handling transmitted buffers */ 851 awg_txeof(sc); 852 853 /* Release any untransmitted buffers. */ 854 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 855 val = le32toh(sc->tx.desc_ring[i].status); 856 if ((val & TX_DESC_CTL) != 0) 857 break; 858 awg_clean_txbuf(sc, i); 859 } 860 sc->tx.next = i; 861 for (; sc->tx.queued > 0; i = TX_NEXT(i)) { 862 sc->tx.desc_ring[i].status = 0; 863 awg_clean_txbuf(sc, i); 864 } 865 sc->tx.cur = sc->tx.next; 866 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 867 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 868 869 /* Setup RX buffers for reuse */ 870 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 871 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 872 873 for (i = sc->rx.cur; ; i = RX_NEXT(i)) { 874 val = le32toh(sc->rx.desc_ring[i].status); 875 if ((val & RX_DESC_CTL) != 0) 876 break; 877 awg_reuse_rxdesc(sc, i); 878 } 879 sc->rx.cur = i; 880 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 882 883 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 884 } 885 886 static int 887 awg_rxintr(struct awg_softc *sc) 888 { 889 if_t ifp; 890 struct mbuf *m, *mh, *mt; 891 int error, index, len, cnt, npkt; 892 uint32_t status; 893 894 ifp = sc->ifp; 895 mh = mt = NULL; 896 cnt = 0; 897 npkt = 0; 898 899 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 900 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 901 902 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 903 status = le32toh(sc->rx.desc_ring[index].status); 904 if ((status & RX_DESC_CTL) != 0) 905 break; 906 907 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 908 909 if (len == 0) { 910 if ((status & (RX_NO_ENOUGH_BUF_ERR | RX_OVERFLOW_ERR)) != 0) 911 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 912 awg_reuse_rxdesc(sc, index); 913 continue; 914 } 915 916 m = sc->rx.buf_map[index].mbuf; 917 918 error = awg_newbuf_rx(sc, index); 919 if (error != 0) { 920 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 921 awg_reuse_rxdesc(sc, index); 922 continue; 923 } 924 925 m->m_pkthdr.rcvif = ifp; 926 m->m_pkthdr.len = len; 927 m->m_len = len; 928 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 929 930 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 931 (status & RX_FRM_TYPE) != 0) { 932 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 933 if ((status & RX_HEADER_ERR) == 0) 934 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 935 if ((status & RX_PAYLOAD_ERR) == 0) { 936 m->m_pkthdr.csum_flags |= 937 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 938 m->m_pkthdr.csum_data = 0xffff; 939 } 940 } 941 942 m->m_nextpkt = NULL; 943 if (mh == NULL) 944 mh = m; 945 else 946 mt->m_nextpkt = m; 947 mt = m; 948 ++cnt; 949 ++npkt; 950 951 if (cnt == awg_rx_batch) { 952 AWG_UNLOCK(sc); 953 if_input(ifp, mh); 954 AWG_LOCK(sc); 955 mh = mt = NULL; 956 cnt = 0; 957 } 958 } 959 960 if (index != sc->rx.cur) { 961 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 962 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 963 } 964 965 if (mh != NULL) { 966 AWG_UNLOCK(sc); 967 if_input(ifp, mh); 968 AWG_LOCK(sc); 969 } 970 971 sc->rx.cur = index; 972 973 return (npkt); 974 } 975 976 static void 977 awg_txeof(struct awg_softc *sc) 978 { 979 struct emac_desc *desc; 980 uint32_t status, size; 981 if_t ifp; 982 int i, prog; 983 984 AWG_ASSERT_LOCKED(sc); 985 986 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 987 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 988 989 ifp = sc->ifp; 990 991 prog = 0; 992 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 993 desc = &sc->tx.desc_ring[i]; 994 status = le32toh(desc->status); 995 if ((status & TX_DESC_CTL) != 0) 996 break; 997 size = le32toh(desc->size); 998 if (size & TX_LAST_DESC) { 999 if ((status & (TX_HEADER_ERR | TX_PAYLOAD_ERR)) != 0) 1000 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1001 else 1002 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1003 } 1004 prog++; 1005 awg_clean_txbuf(sc, i); 1006 } 1007 1008 if (prog > 0) { 1009 sc->tx.next = i; 1010 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1011 } 1012 } 1013 1014 static void 1015 awg_intr(void *arg) 1016 { 1017 struct awg_softc *sc; 1018 uint32_t val; 1019 1020 sc = arg; 1021 1022 AWG_LOCK(sc); 1023 val = RD4(sc, EMAC_INT_STA); 1024 WR4(sc, EMAC_INT_STA, val); 1025 1026 if (val & RX_INT) 1027 awg_rxintr(sc); 1028 1029 if (val & TX_INT) 1030 awg_txeof(sc); 1031 1032 if (val & (TX_INT | TX_BUF_UA_INT)) { 1033 if (!if_sendq_empty(sc->ifp)) 1034 awg_start_locked(sc); 1035 } 1036 1037 AWG_UNLOCK(sc); 1038 } 1039 1040 #ifdef DEVICE_POLLING 1041 static int 1042 awg_poll(if_t ifp, enum poll_cmd cmd, int count) 1043 { 1044 struct awg_softc *sc; 1045 uint32_t val; 1046 int rx_npkts; 1047 1048 sc = if_getsoftc(ifp); 1049 rx_npkts = 0; 1050 1051 AWG_LOCK(sc); 1052 1053 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1054 AWG_UNLOCK(sc); 1055 return (0); 1056 } 1057 1058 rx_npkts = awg_rxintr(sc); 1059 awg_txeof(sc); 1060 if (!if_sendq_empty(ifp)) 1061 awg_start_locked(sc); 1062 1063 if (cmd == POLL_AND_CHECK_STATUS) { 1064 val = RD4(sc, EMAC_INT_STA); 1065 if (val != 0) 1066 WR4(sc, EMAC_INT_STA, val); 1067 } 1068 1069 AWG_UNLOCK(sc); 1070 1071 return (rx_npkts); 1072 } 1073 #endif 1074 1075 static int 1076 awg_ioctl(if_t ifp, u_long cmd, caddr_t data) 1077 { 1078 struct awg_softc *sc; 1079 struct mii_data *mii; 1080 struct ifreq *ifr; 1081 int flags, mask, error; 1082 1083 sc = if_getsoftc(ifp); 1084 mii = device_get_softc(sc->miibus); 1085 ifr = (struct ifreq *)data; 1086 error = 0; 1087 1088 switch (cmd) { 1089 case SIOCSIFFLAGS: 1090 AWG_LOCK(sc); 1091 if (if_getflags(ifp) & IFF_UP) { 1092 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1093 flags = if_getflags(ifp) ^ sc->if_flags; 1094 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) 1095 awg_setup_rxfilter(sc); 1096 } else 1097 awg_init_locked(sc); 1098 } else { 1099 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1100 awg_stop(sc); 1101 } 1102 sc->if_flags = if_getflags(ifp); 1103 AWG_UNLOCK(sc); 1104 break; 1105 case SIOCADDMULTI: 1106 case SIOCDELMULTI: 1107 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1108 AWG_LOCK(sc); 1109 awg_setup_rxfilter(sc); 1110 AWG_UNLOCK(sc); 1111 } 1112 break; 1113 case SIOCSIFMEDIA: 1114 case SIOCGIFMEDIA: 1115 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1116 break; 1117 case SIOCSIFCAP: 1118 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1119 #ifdef DEVICE_POLLING 1120 if (mask & IFCAP_POLLING) { 1121 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1122 error = ether_poll_register(awg_poll, ifp); 1123 if (error != 0) 1124 break; 1125 AWG_LOCK(sc); 1126 awg_disable_intr(sc); 1127 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1128 AWG_UNLOCK(sc); 1129 } else { 1130 error = ether_poll_deregister(ifp); 1131 AWG_LOCK(sc); 1132 awg_enable_intr(sc); 1133 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1134 AWG_UNLOCK(sc); 1135 } 1136 } 1137 #endif 1138 if (mask & IFCAP_VLAN_MTU) 1139 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 1140 if (mask & IFCAP_RXCSUM) 1141 if_togglecapenable(ifp, IFCAP_RXCSUM); 1142 if (mask & IFCAP_TXCSUM) 1143 if_togglecapenable(ifp, IFCAP_TXCSUM); 1144 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1145 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0); 1146 else 1147 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP); 1148 break; 1149 default: 1150 error = ether_ioctl(ifp, cmd, data); 1151 break; 1152 } 1153 1154 return (error); 1155 } 1156 1157 static uint32_t 1158 syscon_read_emac_clk_reg(device_t dev) 1159 { 1160 struct awg_softc *sc; 1161 1162 sc = device_get_softc(dev); 1163 if (sc->syscon != NULL) 1164 return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG)); 1165 else if (sc->res[_RES_SYSCON] != NULL) 1166 return (bus_read_4(sc->res[_RES_SYSCON], 0)); 1167 1168 return (0); 1169 } 1170 1171 static void 1172 syscon_write_emac_clk_reg(device_t dev, uint32_t val) 1173 { 1174 struct awg_softc *sc; 1175 1176 sc = device_get_softc(dev); 1177 if (sc->syscon != NULL) 1178 SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val); 1179 else if (sc->res[_RES_SYSCON] != NULL) 1180 bus_write_4(sc->res[_RES_SYSCON], 0, val); 1181 } 1182 1183 static phandle_t 1184 awg_get_phy_node(device_t dev) 1185 { 1186 phandle_t node; 1187 pcell_t phy_handle; 1188 1189 node = ofw_bus_get_node(dev); 1190 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle, 1191 sizeof(phy_handle)) <= 0) 1192 return (0); 1193 1194 return (OF_node_from_xref(phy_handle)); 1195 } 1196 1197 static bool 1198 awg_has_internal_phy(device_t dev) 1199 { 1200 phandle_t node, phy_node; 1201 1202 node = ofw_bus_get_node(dev); 1203 /* Legacy binding */ 1204 if (OF_hasprop(node, "allwinner,use-internal-phy")) 1205 return (true); 1206 1207 phy_node = awg_get_phy_node(dev); 1208 return (phy_node != 0 && ofw_bus_node_is_compatible(OF_parent(phy_node), 1209 "allwinner,sun8i-h3-mdio-internal") != 0); 1210 } 1211 1212 static int 1213 awg_parse_delay(device_t dev, uint32_t *tx_delay, uint32_t *rx_delay) 1214 { 1215 phandle_t node; 1216 uint32_t delay; 1217 1218 if (tx_delay == NULL || rx_delay == NULL) 1219 return (EINVAL); 1220 *tx_delay = *rx_delay = 0; 1221 node = ofw_bus_get_node(dev); 1222 1223 if (OF_getencprop(node, "tx-delay", &delay, sizeof(delay)) >= 0) 1224 *tx_delay = delay; 1225 else if (OF_getencprop(node, "allwinner,tx-delay-ps", &delay, 1226 sizeof(delay)) >= 0) { 1227 if ((delay % 100) != 0) { 1228 device_printf(dev, "tx-delay-ps is not a multiple of 100\n"); 1229 return (EDOM); 1230 } 1231 *tx_delay = delay / 100; 1232 } 1233 if (*tx_delay > 7) { 1234 device_printf(dev, "tx-delay out of range\n"); 1235 return (ERANGE); 1236 } 1237 1238 if (OF_getencprop(node, "rx-delay", &delay, sizeof(delay)) >= 0) 1239 *rx_delay = delay; 1240 else if (OF_getencprop(node, "allwinner,rx-delay-ps", &delay, 1241 sizeof(delay)) >= 0) { 1242 if ((delay % 100) != 0) { 1243 device_printf(dev, "rx-delay-ps is not within documented domain\n"); 1244 return (EDOM); 1245 } 1246 *rx_delay = delay / 100; 1247 } 1248 if (*rx_delay > 31) { 1249 device_printf(dev, "rx-delay out of range\n"); 1250 return (ERANGE); 1251 } 1252 1253 return (0); 1254 } 1255 1256 static int 1257 awg_setup_phy(device_t dev) 1258 { 1259 struct awg_softc *sc; 1260 clk_t clk_tx, clk_tx_parent; 1261 const char *tx_parent_name; 1262 char *phy_type; 1263 phandle_t node; 1264 uint32_t reg, tx_delay, rx_delay; 1265 int error; 1266 bool use_syscon; 1267 1268 sc = device_get_softc(dev); 1269 node = ofw_bus_get_node(dev); 1270 use_syscon = false; 1271 1272 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_type) == 0) 1273 return (0); 1274 1275 if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL) 1276 use_syscon = true; 1277 1278 if (bootverbose) 1279 device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type, 1280 use_syscon ? "reg" : "clk"); 1281 1282 if (use_syscon) { 1283 /* 1284 * Abstract away writing to syscon for devices like the pine64. 1285 * For the pine64, we get dtb from U-Boot and it still uses the 1286 * legacy setup of specifying syscon register in emac node 1287 * rather than as its own node and using an xref in emac. 1288 * These abstractions can go away once U-Boot dts is up-to-date. 1289 */ 1290 reg = syscon_read_emac_clk_reg(dev); 1291 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 1292 if (strncmp(phy_type, "rgmii", 5) == 0) 1293 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 1294 else if (strcmp(phy_type, "rmii") == 0) 1295 reg |= EMAC_CLK_RMII_EN; 1296 else 1297 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 1298 1299 /* 1300 * Fail attach if we fail to parse either of the delay 1301 * parameters. If we don't have the proper delay to write to 1302 * syscon, then awg likely won't function properly anyways. 1303 * Lack of delay is not an error! 1304 */ 1305 error = awg_parse_delay(dev, &tx_delay, &rx_delay); 1306 if (error != 0) 1307 goto fail; 1308 1309 /* Default to 0 and we'll increase it if we need to. */ 1310 reg &= ~(EMAC_CLK_ETXDC | EMAC_CLK_ERXDC); 1311 if (tx_delay > 0) 1312 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 1313 if (rx_delay > 0) 1314 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 1315 1316 if (sc->type == EMAC_H3) { 1317 if (awg_has_internal_phy(dev)) { 1318 reg |= EMAC_CLK_EPHY_SELECT; 1319 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 1320 if (OF_hasprop(node, 1321 "allwinner,leds-active-low")) 1322 reg |= EMAC_CLK_EPHY_LED_POL; 1323 else 1324 reg &= ~EMAC_CLK_EPHY_LED_POL; 1325 1326 /* Set internal PHY addr to 1 */ 1327 reg &= ~EMAC_CLK_EPHY_ADDR; 1328 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 1329 } else { 1330 reg &= ~EMAC_CLK_EPHY_SELECT; 1331 } 1332 } 1333 1334 if (bootverbose) 1335 device_printf(dev, "EMAC clock: 0x%08x\n", reg); 1336 syscon_write_emac_clk_reg(dev, reg); 1337 } else { 1338 if (strncmp(phy_type, "rgmii", 5) == 0) 1339 tx_parent_name = "emac_int_tx"; 1340 else 1341 tx_parent_name = "mii_phy_tx"; 1342 1343 /* Get the TX clock */ 1344 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx); 1345 if (error != 0) { 1346 device_printf(dev, "cannot get tx clock\n"); 1347 goto fail; 1348 } 1349 1350 /* Find the desired parent clock based on phy-mode property */ 1351 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent); 1352 if (error != 0) { 1353 device_printf(dev, "cannot get clock '%s'\n", 1354 tx_parent_name); 1355 goto fail; 1356 } 1357 1358 /* Set TX clock parent */ 1359 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent); 1360 if (error != 0) { 1361 device_printf(dev, "cannot set tx clock parent\n"); 1362 goto fail; 1363 } 1364 1365 /* Enable TX clock */ 1366 error = clk_enable(clk_tx); 1367 if (error != 0) { 1368 device_printf(dev, "cannot enable tx clock\n"); 1369 goto fail; 1370 } 1371 } 1372 1373 error = 0; 1374 1375 fail: 1376 OF_prop_free(phy_type); 1377 return (error); 1378 } 1379 1380 static int 1381 awg_setup_extres(device_t dev) 1382 { 1383 struct awg_softc *sc; 1384 phandle_t node, phy_node; 1385 hwreset_t rst_ahb, rst_ephy; 1386 clk_t clk_ahb, clk_ephy; 1387 regulator_t reg; 1388 uint64_t freq; 1389 int error, div; 1390 1391 sc = device_get_softc(dev); 1392 rst_ahb = rst_ephy = NULL; 1393 clk_ahb = clk_ephy = NULL; 1394 reg = NULL; 1395 node = ofw_bus_get_node(dev); 1396 phy_node = awg_get_phy_node(dev); 1397 1398 if (phy_node == 0 && OF_hasprop(node, "phy-handle")) { 1399 error = ENXIO; 1400 device_printf(dev, "cannot get phy handle\n"); 1401 goto fail; 1402 } 1403 1404 /* Get AHB clock and reset resources */ 1405 error = hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst_ahb); 1406 if (error != 0) 1407 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb); 1408 if (error != 0) { 1409 device_printf(dev, "cannot get ahb reset\n"); 1410 goto fail; 1411 } 1412 if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0) 1413 if (phy_node == 0 || hwreset_get_by_ofw_idx(dev, phy_node, 0, 1414 &rst_ephy) != 0) 1415 rst_ephy = NULL; 1416 error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk_ahb); 1417 if (error != 0) 1418 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb); 1419 if (error != 0) { 1420 device_printf(dev, "cannot get ahb clock\n"); 1421 goto fail; 1422 } 1423 if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0) 1424 if (phy_node == 0 || clk_get_by_ofw_index(dev, phy_node, 0, 1425 &clk_ephy) != 0) 1426 clk_ephy = NULL; 1427 1428 if (OF_hasprop(node, "syscon") && syscon_get_by_ofw_property(dev, node, 1429 "syscon", &sc->syscon) != 0) { 1430 device_printf(dev, "cannot get syscon driver handle\n"); 1431 goto fail; 1432 } 1433 1434 /* Configure PHY for MII or RGMII mode */ 1435 if (awg_setup_phy(dev) != 0) 1436 goto fail; 1437 1438 /* Enable clocks */ 1439 error = clk_enable(clk_ahb); 1440 if (error != 0) { 1441 device_printf(dev, "cannot enable ahb clock\n"); 1442 goto fail; 1443 } 1444 if (clk_ephy != NULL) { 1445 error = clk_enable(clk_ephy); 1446 if (error != 0) { 1447 device_printf(dev, "cannot enable ephy clock\n"); 1448 goto fail; 1449 } 1450 } 1451 1452 /* De-assert reset */ 1453 error = hwreset_deassert(rst_ahb); 1454 if (error != 0) { 1455 device_printf(dev, "cannot de-assert ahb reset\n"); 1456 goto fail; 1457 } 1458 if (rst_ephy != NULL) { 1459 /* 1460 * The ephy reset is left de-asserted by U-Boot. Assert it 1461 * here to make sure that we're in a known good state going 1462 * into the PHY reset. 1463 */ 1464 hwreset_assert(rst_ephy); 1465 error = hwreset_deassert(rst_ephy); 1466 if (error != 0) { 1467 device_printf(dev, "cannot de-assert ephy reset\n"); 1468 goto fail; 1469 } 1470 } 1471 1472 /* Enable PHY regulator if applicable */ 1473 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) { 1474 error = regulator_enable(reg); 1475 if (error != 0) { 1476 device_printf(dev, "cannot enable PHY regulator\n"); 1477 goto fail; 1478 } 1479 } 1480 1481 /* Determine MDC clock divide ratio based on AHB clock */ 1482 error = clk_get_freq(clk_ahb, &freq); 1483 if (error != 0) { 1484 device_printf(dev, "cannot get AHB clock frequency\n"); 1485 goto fail; 1486 } 1487 div = freq / MDIO_FREQ; 1488 if (div <= 16) 1489 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1490 else if (div <= 32) 1491 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1492 else if (div <= 64) 1493 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1494 else if (div <= 128) 1495 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1496 else { 1497 device_printf(dev, "cannot determine MDC clock divide ratio\n"); 1498 error = ENXIO; 1499 goto fail; 1500 } 1501 1502 if (bootverbose) 1503 device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n", 1504 (uintmax_t)freq, sc->mdc_div_ratio_m); 1505 1506 return (0); 1507 1508 fail: 1509 if (reg != NULL) 1510 regulator_release(reg); 1511 if (clk_ephy != NULL) 1512 clk_release(clk_ephy); 1513 if (clk_ahb != NULL) 1514 clk_release(clk_ahb); 1515 if (rst_ephy != NULL) 1516 hwreset_release(rst_ephy); 1517 if (rst_ahb != NULL) 1518 hwreset_release(rst_ahb); 1519 return (error); 1520 } 1521 1522 static void 1523 awg_get_eaddr(device_t dev, uint8_t *eaddr) 1524 { 1525 struct awg_softc *sc; 1526 uint32_t maclo, machi, rnd; 1527 u_char rootkey[16]; 1528 uint32_t rootkey_size; 1529 1530 sc = device_get_softc(dev); 1531 1532 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1533 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1534 1535 rootkey_size = sizeof(rootkey); 1536 if (maclo == 0xffffffff && machi == 0xffff) { 1537 /* MAC address in hardware is invalid, create one */ 1538 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey, 1539 &rootkey_size) == 0 && 1540 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1541 rootkey[15]) != 0) { 1542 /* MAC address is derived from the root key in SID */ 1543 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1544 (rootkey[3] << 8) | 0x02; 1545 machi = (rootkey[15] << 8) | rootkey[14]; 1546 } else { 1547 /* Create one */ 1548 rnd = arc4random(); 1549 maclo = 0x00f2 | (rnd & 0xffff0000); 1550 machi = rnd & 0xffff; 1551 } 1552 } 1553 1554 eaddr[0] = maclo & 0xff; 1555 eaddr[1] = (maclo >> 8) & 0xff; 1556 eaddr[2] = (maclo >> 16) & 0xff; 1557 eaddr[3] = (maclo >> 24) & 0xff; 1558 eaddr[4] = machi & 0xff; 1559 eaddr[5] = (machi >> 8) & 0xff; 1560 } 1561 1562 #ifdef AWG_DEBUG 1563 static void 1564 awg_dump_regs(device_t dev) 1565 { 1566 static const struct { 1567 const char *name; 1568 u_int reg; 1569 } regs[] = { 1570 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1571 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1572 { "INT_STA", EMAC_INT_STA }, 1573 { "INT_EN", EMAC_INT_EN }, 1574 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1575 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1576 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1577 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1578 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1579 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1580 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1581 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1582 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1583 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1584 { "MII_CMD", EMAC_MII_CMD }, 1585 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1586 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1587 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1588 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1589 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1590 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1591 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1592 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1593 { "RGMII_STA", EMAC_RGMII_STA }, 1594 }; 1595 struct awg_softc *sc; 1596 unsigned int n; 1597 1598 sc = device_get_softc(dev); 1599 1600 for (n = 0; n < nitems(regs); n++) 1601 device_printf(dev, " %-20s %08x\n", regs[n].name, 1602 RD4(sc, regs[n].reg)); 1603 } 1604 #endif 1605 1606 #define GPIO_ACTIVE_LOW 1 1607 1608 static int 1609 awg_phy_reset(device_t dev) 1610 { 1611 pcell_t gpio_prop[4], delay_prop[3]; 1612 phandle_t node, gpio_node; 1613 device_t gpio; 1614 uint32_t pin, flags; 1615 uint32_t pin_value; 1616 1617 node = ofw_bus_get_node(dev); 1618 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop, 1619 sizeof(gpio_prop)) <= 0) 1620 return (0); 1621 1622 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop, 1623 sizeof(delay_prop)) <= 0) 1624 return (ENXIO); 1625 1626 gpio_node = OF_node_from_xref(gpio_prop[0]); 1627 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) 1628 return (ENXIO); 1629 1630 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1, 1631 gpio_prop + 1, &pin, &flags) != 0) 1632 return (ENXIO); 1633 1634 pin_value = GPIO_PIN_LOW; 1635 if (OF_hasprop(node, "allwinner,reset-active-low")) 1636 pin_value = GPIO_PIN_HIGH; 1637 1638 if (flags & GPIO_ACTIVE_LOW) 1639 pin_value = !pin_value; 1640 1641 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 1642 GPIO_PIN_SET(gpio, pin, pin_value); 1643 DELAY(delay_prop[0]); 1644 GPIO_PIN_SET(gpio, pin, !pin_value); 1645 DELAY(delay_prop[1]); 1646 GPIO_PIN_SET(gpio, pin, pin_value); 1647 DELAY(delay_prop[2]); 1648 1649 return (0); 1650 } 1651 1652 static int 1653 awg_reset(device_t dev) 1654 { 1655 struct awg_softc *sc; 1656 int retry; 1657 1658 sc = device_get_softc(dev); 1659 1660 /* Reset PHY if necessary */ 1661 if (awg_phy_reset(dev) != 0) { 1662 device_printf(dev, "failed to reset PHY\n"); 1663 return (ENXIO); 1664 } 1665 1666 /* Soft reset all registers and logic */ 1667 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1668 1669 /* Wait for soft reset bit to self-clear */ 1670 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1671 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1672 break; 1673 DELAY(10); 1674 } 1675 if (retry == 0) { 1676 device_printf(dev, "soft reset timed out\n"); 1677 #ifdef AWG_DEBUG 1678 awg_dump_regs(dev); 1679 #endif 1680 return (ETIMEDOUT); 1681 } 1682 1683 return (0); 1684 } 1685 1686 static void 1687 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1688 { 1689 if (error != 0) 1690 return; 1691 *(bus_addr_t *)arg = segs[0].ds_addr; 1692 } 1693 1694 static int 1695 awg_setup_dma(device_t dev) 1696 { 1697 struct awg_softc *sc; 1698 int error, i; 1699 1700 sc = device_get_softc(dev); 1701 1702 /* Setup TX ring */ 1703 error = bus_dma_tag_create( 1704 bus_get_dma_tag(dev), /* Parent tag */ 1705 DESC_ALIGN, 0, /* alignment, boundary */ 1706 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1707 BUS_SPACE_MAXADDR, /* highaddr */ 1708 NULL, NULL, /* filter, filterarg */ 1709 TX_DESC_SIZE, 1, /* maxsize, nsegs */ 1710 TX_DESC_SIZE, /* maxsegsize */ 1711 0, /* flags */ 1712 NULL, NULL, /* lockfunc, lockarg */ 1713 &sc->tx.desc_tag); 1714 if (error != 0) { 1715 device_printf(dev, "cannot create TX descriptor ring tag\n"); 1716 return (error); 1717 } 1718 1719 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring, 1720 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map); 1721 if (error != 0) { 1722 device_printf(dev, "cannot allocate TX descriptor ring\n"); 1723 return (error); 1724 } 1725 1726 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map, 1727 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb, 1728 &sc->tx.desc_ring_paddr, 0); 1729 if (error != 0) { 1730 device_printf(dev, "cannot load TX descriptor ring\n"); 1731 return (error); 1732 } 1733 1734 for (i = 0; i < TX_DESC_COUNT; i++) 1735 sc->tx.desc_ring[i].next = 1736 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1737 1738 error = bus_dma_tag_create( 1739 bus_get_dma_tag(dev), /* Parent tag */ 1740 1, 0, /* alignment, boundary */ 1741 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1742 BUS_SPACE_MAXADDR, /* highaddr */ 1743 NULL, NULL, /* filter, filterarg */ 1744 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */ 1745 MCLBYTES, /* maxsegsize */ 1746 0, /* flags */ 1747 NULL, NULL, /* lockfunc, lockarg */ 1748 &sc->tx.buf_tag); 1749 if (error != 0) { 1750 device_printf(dev, "cannot create TX buffer tag\n"); 1751 return (error); 1752 } 1753 1754 sc->tx.queued = 0; 1755 for (i = 0; i < TX_DESC_COUNT; i++) { 1756 error = bus_dmamap_create(sc->tx.buf_tag, 0, 1757 &sc->tx.buf_map[i].map); 1758 if (error != 0) { 1759 device_printf(dev, "cannot create TX buffer map\n"); 1760 return (error); 1761 } 1762 } 1763 1764 /* Setup RX ring */ 1765 error = bus_dma_tag_create( 1766 bus_get_dma_tag(dev), /* Parent tag */ 1767 DESC_ALIGN, 0, /* alignment, boundary */ 1768 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1769 BUS_SPACE_MAXADDR, /* highaddr */ 1770 NULL, NULL, /* filter, filterarg */ 1771 RX_DESC_SIZE, 1, /* maxsize, nsegs */ 1772 RX_DESC_SIZE, /* maxsegsize */ 1773 0, /* flags */ 1774 NULL, NULL, /* lockfunc, lockarg */ 1775 &sc->rx.desc_tag); 1776 if (error != 0) { 1777 device_printf(dev, "cannot create RX descriptor ring tag\n"); 1778 return (error); 1779 } 1780 1781 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring, 1782 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map); 1783 if (error != 0) { 1784 device_printf(dev, "cannot allocate RX descriptor ring\n"); 1785 return (error); 1786 } 1787 1788 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map, 1789 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb, 1790 &sc->rx.desc_ring_paddr, 0); 1791 if (error != 0) { 1792 device_printf(dev, "cannot load RX descriptor ring\n"); 1793 return (error); 1794 } 1795 1796 error = bus_dma_tag_create( 1797 bus_get_dma_tag(dev), /* Parent tag */ 1798 1, 0, /* alignment, boundary */ 1799 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1800 BUS_SPACE_MAXADDR, /* highaddr */ 1801 NULL, NULL, /* filter, filterarg */ 1802 MCLBYTES, 1, /* maxsize, nsegs */ 1803 MCLBYTES, /* maxsegsize */ 1804 0, /* flags */ 1805 NULL, NULL, /* lockfunc, lockarg */ 1806 &sc->rx.buf_tag); 1807 if (error != 0) { 1808 device_printf(dev, "cannot create RX buffer tag\n"); 1809 return (error); 1810 } 1811 1812 error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map); 1813 if (error != 0) { 1814 device_printf(dev, 1815 "cannot create RX buffer spare map\n"); 1816 return (error); 1817 } 1818 1819 for (i = 0; i < RX_DESC_COUNT; i++) { 1820 sc->rx.desc_ring[i].next = 1821 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i))); 1822 1823 error = bus_dmamap_create(sc->rx.buf_tag, 0, 1824 &sc->rx.buf_map[i].map); 1825 if (error != 0) { 1826 device_printf(dev, "cannot create RX buffer map\n"); 1827 return (error); 1828 } 1829 sc->rx.buf_map[i].mbuf = NULL; 1830 error = awg_newbuf_rx(sc, i); 1831 if (error != 0) { 1832 device_printf(dev, "cannot create RX buffer\n"); 1833 return (error); 1834 } 1835 } 1836 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1837 BUS_DMASYNC_PREWRITE); 1838 1839 /* Write transmit and receive descriptor base address registers */ 1840 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1841 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1842 1843 return (0); 1844 } 1845 1846 static int 1847 awg_probe(device_t dev) 1848 { 1849 if (!ofw_bus_status_okay(dev)) 1850 return (ENXIO); 1851 1852 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1853 return (ENXIO); 1854 1855 device_set_desc(dev, "Allwinner Gigabit Ethernet"); 1856 return (BUS_PROBE_DEFAULT); 1857 } 1858 1859 static int 1860 awg_attach(device_t dev) 1861 { 1862 uint8_t eaddr[ETHER_ADDR_LEN]; 1863 struct awg_softc *sc; 1864 int error; 1865 1866 sc = device_get_softc(dev); 1867 sc->dev = dev; 1868 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1869 1870 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) { 1871 device_printf(dev, "cannot allocate resources for device\n"); 1872 return (ENXIO); 1873 } 1874 1875 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 1876 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0); 1877 TASK_INIT(&sc->link_task, 0, awg_link_task, sc); 1878 1879 /* Setup clocks and regulators */ 1880 error = awg_setup_extres(dev); 1881 if (error != 0) 1882 return (error); 1883 1884 /* Read MAC address before resetting the chip */ 1885 awg_get_eaddr(dev, eaddr); 1886 1887 /* Soft reset EMAC core */ 1888 error = awg_reset(dev); 1889 if (error != 0) 1890 return (error); 1891 1892 /* Setup DMA descriptors */ 1893 error = awg_setup_dma(dev); 1894 if (error != 0) 1895 return (error); 1896 1897 /* Install interrupt handler */ 1898 error = bus_setup_intr(dev, sc->res[_RES_IRQ], 1899 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih); 1900 if (error != 0) { 1901 device_printf(dev, "cannot setup interrupt handler\n"); 1902 return (error); 1903 } 1904 1905 /* Setup ethernet interface */ 1906 sc->ifp = if_alloc(IFT_ETHER); 1907 if_setsoftc(sc->ifp, sc); 1908 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev)); 1909 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1910 if_setstartfn(sc->ifp, awg_start); 1911 if_setioctlfn(sc->ifp, awg_ioctl); 1912 if_setinitfn(sc->ifp, awg_init); 1913 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1); 1914 if_setsendqready(sc->ifp); 1915 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); 1916 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM); 1917 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp)); 1918 #ifdef DEVICE_POLLING 1919 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0); 1920 #endif 1921 1922 /* Attach MII driver */ 1923 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change, 1924 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 1925 MIIF_DOPAUSE); 1926 if (error != 0) { 1927 device_printf(dev, "cannot attach PHY\n"); 1928 return (error); 1929 } 1930 1931 /* Attach ethernet interface */ 1932 ether_ifattach(sc->ifp, eaddr); 1933 1934 return (0); 1935 } 1936 1937 static device_method_t awg_methods[] = { 1938 /* Device interface */ 1939 DEVMETHOD(device_probe, awg_probe), 1940 DEVMETHOD(device_attach, awg_attach), 1941 1942 /* MII interface */ 1943 DEVMETHOD(miibus_readreg, awg_miibus_readreg), 1944 DEVMETHOD(miibus_writereg, awg_miibus_writereg), 1945 DEVMETHOD(miibus_statchg, awg_miibus_statchg), 1946 1947 DEVMETHOD_END 1948 }; 1949 1950 static driver_t awg_driver = { 1951 "awg", 1952 awg_methods, 1953 sizeof(struct awg_softc), 1954 }; 1955 1956 static devclass_t awg_devclass; 1957 1958 DRIVER_MODULE(awg, simplebus, awg_driver, awg_devclass, 0, 0); 1959 DRIVER_MODULE(miibus, awg, miibus_driver, miibus_devclass, 0, 0); 1960 MODULE_DEPEND(awg, ether, 1, 1, 1); 1961 MODULE_DEPEND(awg, miibus, 1, 1, 1); 1962 MODULE_DEPEND(awg, aw_sid, 1, 1, 1); 1963 SIMPLEBUS_PNP_INFO(compat_data); 1964