1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 /* 29 * Allwinner Gigabit Ethernet MAC (EMAC) controller 30 */ 31 32 #include "opt_device_polling.h" 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/rman.h> 41 #include <sys/kernel.h> 42 #include <sys/endian.h> 43 #include <sys/mbuf.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/module.h> 47 #include <sys/taskqueue.h> 48 #include <sys/gpio.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_var.h> 57 58 #include <machine/bus.h> 59 60 #include <dev/ofw/ofw_bus.h> 61 #include <dev/ofw/ofw_bus_subr.h> 62 63 #include <arm/allwinner/if_awgreg.h> 64 #include <arm/allwinner/aw_sid.h> 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/extres/clk/clk.h> 69 #include <dev/extres/hwreset/hwreset.h> 70 #include <dev/extres/regulator/regulator.h> 71 #include <dev/extres/syscon/syscon.h> 72 73 #include "syscon_if.h" 74 #include "miibus_if.h" 75 #include "gpio_if.h" 76 77 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg)) 78 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val)) 79 80 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx) 81 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx); 82 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 83 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 84 85 #define DESC_ALIGN 4 86 #define TX_DESC_COUNT 1024 87 #define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT) 88 #define RX_DESC_COUNT 256 89 #define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT) 90 91 #define DESC_OFF(n) ((n) * sizeof(struct emac_desc)) 92 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 93 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 94 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 95 96 #define TX_MAX_SEGS 20 97 98 #define SOFT_RST_RETRY 1000 99 #define MII_BUSY_RETRY 1000 100 #define MDIO_FREQ 2500000 101 102 #define BURST_LEN_DEFAULT 8 103 #define RX_TX_PRI_DEFAULT 0 104 #define PAUSE_TIME_DEFAULT 0x400 105 #define TX_INTERVAL_DEFAULT 64 106 #define RX_BATCH_DEFAULT 64 107 108 /* syscon EMAC clock register */ 109 #define EMAC_CLK_REG 0x30 110 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 111 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 112 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 113 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 114 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 115 #define EMAC_CLK_RMII_EN (1 << 13) 116 #define EMAC_CLK_ETXDC (0x7 << 10) 117 #define EMAC_CLK_ETXDC_SHIFT 10 118 #define EMAC_CLK_ERXDC (0x1f << 5) 119 #define EMAC_CLK_ERXDC_SHIFT 5 120 #define EMAC_CLK_PIT (0x1 << 2) 121 #define EMAC_CLK_PIT_MII (0 << 2) 122 #define EMAC_CLK_PIT_RGMII (1 << 2) 123 #define EMAC_CLK_SRC (0x3 << 0) 124 #define EMAC_CLK_SRC_MII (0 << 0) 125 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 126 #define EMAC_CLK_SRC_RGMII (2 << 0) 127 128 /* Burst length of RX and TX DMA transfers */ 129 static int awg_burst_len = BURST_LEN_DEFAULT; 130 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len); 131 132 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 133 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT; 134 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri); 135 136 /* Pause time field in the transmitted control frame */ 137 static int awg_pause_time = PAUSE_TIME_DEFAULT; 138 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time); 139 140 /* Request a TX interrupt every <n> descriptors */ 141 static int awg_tx_interval = TX_INTERVAL_DEFAULT; 142 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval); 143 144 /* Maximum number of mbufs to send to if_input */ 145 static int awg_rx_batch = RX_BATCH_DEFAULT; 146 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch); 147 148 enum awg_type { 149 EMAC_A83T = 1, 150 EMAC_H3, 151 EMAC_A64, 152 }; 153 154 static struct ofw_compat_data compat_data[] = { 155 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 156 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 157 { "allwinner,sun50i-a64-emac", EMAC_A64 }, 158 { NULL, 0 } 159 }; 160 161 struct awg_bufmap { 162 bus_dmamap_t map; 163 struct mbuf *mbuf; 164 }; 165 166 struct awg_txring { 167 bus_dma_tag_t desc_tag; 168 bus_dmamap_t desc_map; 169 struct emac_desc *desc_ring; 170 bus_addr_t desc_ring_paddr; 171 bus_dma_tag_t buf_tag; 172 struct awg_bufmap buf_map[TX_DESC_COUNT]; 173 u_int cur, next, queued; 174 u_int segs; 175 }; 176 177 struct awg_rxring { 178 bus_dma_tag_t desc_tag; 179 bus_dmamap_t desc_map; 180 struct emac_desc *desc_ring; 181 bus_addr_t desc_ring_paddr; 182 bus_dma_tag_t buf_tag; 183 struct awg_bufmap buf_map[RX_DESC_COUNT]; 184 bus_dmamap_t buf_spare_map; 185 u_int cur; 186 }; 187 188 enum { 189 _RES_EMAC, 190 _RES_IRQ, 191 _RES_SYSCON, 192 _RES_NITEMS 193 }; 194 195 struct awg_softc { 196 struct resource *res[_RES_NITEMS]; 197 struct mtx mtx; 198 if_t ifp; 199 device_t dev; 200 device_t miibus; 201 struct callout stat_ch; 202 struct task link_task; 203 void *ih; 204 u_int mdc_div_ratio_m; 205 int link; 206 int if_flags; 207 enum awg_type type; 208 struct syscon *syscon; 209 210 struct awg_txring tx; 211 struct awg_rxring rx; 212 }; 213 214 static struct resource_spec awg_spec[] = { 215 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 216 { SYS_RES_IRQ, 0, RF_ACTIVE }, 217 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 218 { -1, 0 } 219 }; 220 221 static void awg_txeof(struct awg_softc *sc); 222 223 static int awg_parse_delay(device_t dev, uint32_t *tx_delay, 224 uint32_t *rx_delay); 225 static uint32_t syscon_read_emac_clk_reg(device_t dev); 226 static void syscon_write_emac_clk_reg(device_t dev, uint32_t val); 227 static phandle_t awg_get_phy_node(device_t dev); 228 static bool awg_has_internal_phy(device_t dev); 229 230 static int 231 awg_miibus_readreg(device_t dev, int phy, int reg) 232 { 233 struct awg_softc *sc; 234 int retry, val; 235 236 sc = device_get_softc(dev); 237 val = 0; 238 239 WR4(sc, EMAC_MII_CMD, 240 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 241 (phy << PHY_ADDR_SHIFT) | 242 (reg << PHY_REG_ADDR_SHIFT) | 243 MII_BUSY); 244 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 245 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 246 val = RD4(sc, EMAC_MII_DATA); 247 break; 248 } 249 DELAY(10); 250 } 251 252 if (retry == 0) 253 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 254 phy, reg); 255 256 return (val); 257 } 258 259 static int 260 awg_miibus_writereg(device_t dev, int phy, int reg, int val) 261 { 262 struct awg_softc *sc; 263 int retry; 264 265 sc = device_get_softc(dev); 266 267 WR4(sc, EMAC_MII_DATA, val); 268 WR4(sc, EMAC_MII_CMD, 269 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 270 (phy << PHY_ADDR_SHIFT) | 271 (reg << PHY_REG_ADDR_SHIFT) | 272 MII_WR | MII_BUSY); 273 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 274 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 275 break; 276 DELAY(10); 277 } 278 279 if (retry == 0) 280 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 281 phy, reg); 282 283 return (0); 284 } 285 286 static void 287 awg_update_link_locked(struct awg_softc *sc) 288 { 289 struct mii_data *mii; 290 uint32_t val; 291 292 AWG_ASSERT_LOCKED(sc); 293 294 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) 295 return; 296 mii = device_get_softc(sc->miibus); 297 298 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 299 (IFM_ACTIVE | IFM_AVALID)) { 300 switch (IFM_SUBTYPE(mii->mii_media_active)) { 301 case IFM_1000_T: 302 case IFM_1000_SX: 303 case IFM_100_TX: 304 case IFM_10_T: 305 sc->link = 1; 306 break; 307 default: 308 sc->link = 0; 309 break; 310 } 311 } else 312 sc->link = 0; 313 314 if (sc->link == 0) 315 return; 316 317 val = RD4(sc, EMAC_BASIC_CTL_0); 318 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 319 320 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 321 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 322 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 323 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 324 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 325 else 326 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 327 328 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 329 val |= BASIC_CTL_DUPLEX; 330 331 WR4(sc, EMAC_BASIC_CTL_0, val); 332 333 val = RD4(sc, EMAC_RX_CTL_0); 334 val &= ~RX_FLOW_CTL_EN; 335 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 336 val |= RX_FLOW_CTL_EN; 337 WR4(sc, EMAC_RX_CTL_0, val); 338 339 val = RD4(sc, EMAC_TX_FLOW_CTL); 340 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 341 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 342 val |= TX_FLOW_CTL_EN; 343 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 344 val |= awg_pause_time << PAUSE_TIME_SHIFT; 345 WR4(sc, EMAC_TX_FLOW_CTL, val); 346 } 347 348 static void 349 awg_link_task(void *arg, int pending) 350 { 351 struct awg_softc *sc; 352 353 sc = arg; 354 355 AWG_LOCK(sc); 356 awg_update_link_locked(sc); 357 AWG_UNLOCK(sc); 358 } 359 360 static void 361 awg_miibus_statchg(device_t dev) 362 { 363 struct awg_softc *sc; 364 365 sc = device_get_softc(dev); 366 367 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 368 } 369 370 static void 371 awg_media_status(if_t ifp, struct ifmediareq *ifmr) 372 { 373 struct awg_softc *sc; 374 struct mii_data *mii; 375 376 sc = if_getsoftc(ifp); 377 mii = device_get_softc(sc->miibus); 378 379 AWG_LOCK(sc); 380 mii_pollstat(mii); 381 ifmr->ifm_active = mii->mii_media_active; 382 ifmr->ifm_status = mii->mii_media_status; 383 AWG_UNLOCK(sc); 384 } 385 386 static int 387 awg_media_change(if_t ifp) 388 { 389 struct awg_softc *sc; 390 struct mii_data *mii; 391 int error; 392 393 sc = if_getsoftc(ifp); 394 mii = device_get_softc(sc->miibus); 395 396 AWG_LOCK(sc); 397 error = mii_mediachg(mii); 398 AWG_UNLOCK(sc); 399 400 return (error); 401 } 402 403 static int 404 awg_encap(struct awg_softc *sc, struct mbuf **mp) 405 { 406 bus_dmamap_t map; 407 bus_dma_segment_t segs[TX_MAX_SEGS]; 408 int error, nsegs, cur, first, last, i; 409 u_int csum_flags; 410 uint32_t flags, status; 411 struct mbuf *m; 412 413 cur = first = sc->tx.cur; 414 map = sc->tx.buf_map[first].map; 415 416 m = *mp; 417 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs, 418 &nsegs, BUS_DMA_NOWAIT); 419 if (error == EFBIG) { 420 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS); 421 if (m == NULL) { 422 device_printf(sc->dev, "awg_encap: m_collapse failed\n"); 423 m_freem(*mp); 424 *mp = NULL; 425 return (ENOMEM); 426 } 427 *mp = m; 428 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, 429 segs, &nsegs, BUS_DMA_NOWAIT); 430 if (error != 0) { 431 m_freem(*mp); 432 *mp = NULL; 433 } 434 } 435 if (error != 0) { 436 device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n"); 437 return (error); 438 } 439 if (nsegs == 0) { 440 m_freem(*mp); 441 *mp = NULL; 442 return (EIO); 443 } 444 445 if (sc->tx.queued + nsegs > TX_DESC_COUNT) { 446 bus_dmamap_unload(sc->tx.buf_tag, map); 447 return (ENOBUFS); 448 } 449 450 bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE); 451 452 flags = TX_FIR_DESC; 453 status = 0; 454 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) { 455 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) 456 csum_flags = TX_CHECKSUM_CTL_FULL; 457 else 458 csum_flags = TX_CHECKSUM_CTL_IP; 459 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 460 } 461 462 for (i = 0; i < nsegs; i++) { 463 sc->tx.segs++; 464 if (i == nsegs - 1) { 465 flags |= TX_LAST_DESC; 466 /* 467 * Can only request TX completion 468 * interrupt on last descriptor. 469 */ 470 if (sc->tx.segs >= awg_tx_interval) { 471 sc->tx.segs = 0; 472 flags |= TX_INT_CTL; 473 } 474 } 475 476 sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr); 477 sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len); 478 sc->tx.desc_ring[cur].status = htole32(status); 479 480 flags &= ~TX_FIR_DESC; 481 /* 482 * Setting of the valid bit in the first descriptor is 483 * deferred until the whole chain is fully set up. 484 */ 485 status = TX_DESC_CTL; 486 487 ++sc->tx.queued; 488 cur = TX_NEXT(cur); 489 } 490 491 sc->tx.cur = cur; 492 493 /* Store mapping and mbuf in the last segment */ 494 last = TX_SKIP(cur, TX_DESC_COUNT - 1); 495 sc->tx.buf_map[first].map = sc->tx.buf_map[last].map; 496 sc->tx.buf_map[last].map = map; 497 sc->tx.buf_map[last].mbuf = m; 498 499 /* 500 * The whole mbuf chain has been DMA mapped, 501 * fix the first descriptor. 502 */ 503 sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL); 504 505 return (0); 506 } 507 508 static void 509 awg_clean_txbuf(struct awg_softc *sc, int index) 510 { 511 struct awg_bufmap *bmap; 512 513 --sc->tx.queued; 514 515 bmap = &sc->tx.buf_map[index]; 516 if (bmap->mbuf != NULL) { 517 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 518 BUS_DMASYNC_POSTWRITE); 519 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 520 m_freem(bmap->mbuf); 521 bmap->mbuf = NULL; 522 } 523 } 524 525 static void 526 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr) 527 { 528 uint32_t status, size; 529 530 status = RX_DESC_CTL; 531 size = MCLBYTES - 1; 532 533 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 534 sc->rx.desc_ring[index].size = htole32(size); 535 sc->rx.desc_ring[index].status = htole32(status); 536 } 537 538 static void 539 awg_reuse_rxdesc(struct awg_softc *sc, int index) 540 { 541 542 sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL); 543 } 544 545 static int 546 awg_newbuf_rx(struct awg_softc *sc, int index) 547 { 548 struct mbuf *m; 549 bus_dma_segment_t seg; 550 bus_dmamap_t map; 551 int nsegs; 552 553 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 554 if (m == NULL) 555 return (ENOBUFS); 556 557 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 558 m_adj(m, ETHER_ALIGN); 559 560 if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map, 561 m, &seg, &nsegs, BUS_DMA_NOWAIT) != 0) { 562 m_freem(m); 563 return (ENOBUFS); 564 } 565 566 if (sc->rx.buf_map[index].mbuf != NULL) { 567 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 568 BUS_DMASYNC_POSTREAD); 569 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 570 } 571 map = sc->rx.buf_map[index].map; 572 sc->rx.buf_map[index].map = sc->rx.buf_spare_map; 573 sc->rx.buf_spare_map = map; 574 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 575 BUS_DMASYNC_PREREAD); 576 577 sc->rx.buf_map[index].mbuf = m; 578 awg_setup_rxdesc(sc, index, seg.ds_addr); 579 580 return (0); 581 } 582 583 static void 584 awg_start_locked(struct awg_softc *sc) 585 { 586 struct mbuf *m; 587 uint32_t val; 588 if_t ifp; 589 int cnt, err; 590 591 AWG_ASSERT_LOCKED(sc); 592 593 if (!sc->link) 594 return; 595 596 ifp = sc->ifp; 597 598 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 599 IFF_DRV_RUNNING) 600 return; 601 602 for (cnt = 0; ; cnt++) { 603 m = if_dequeue(ifp); 604 if (m == NULL) 605 break; 606 607 err = awg_encap(sc, &m); 608 if (err != 0) { 609 if (err == ENOBUFS) 610 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 611 if (m != NULL) 612 if_sendq_prepend(ifp, m); 613 break; 614 } 615 if_bpfmtap(ifp, m); 616 } 617 618 if (cnt != 0) { 619 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 620 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 621 622 /* Start and run TX DMA */ 623 val = RD4(sc, EMAC_TX_CTL_1); 624 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 625 } 626 } 627 628 static void 629 awg_start(if_t ifp) 630 { 631 struct awg_softc *sc; 632 633 sc = if_getsoftc(ifp); 634 635 AWG_LOCK(sc); 636 awg_start_locked(sc); 637 AWG_UNLOCK(sc); 638 } 639 640 static void 641 awg_tick(void *softc) 642 { 643 struct awg_softc *sc; 644 struct mii_data *mii; 645 if_t ifp; 646 int link; 647 648 sc = softc; 649 ifp = sc->ifp; 650 mii = device_get_softc(sc->miibus); 651 652 AWG_ASSERT_LOCKED(sc); 653 654 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 655 return; 656 657 link = sc->link; 658 mii_tick(mii); 659 if (sc->link && !link) 660 awg_start_locked(sc); 661 662 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 663 } 664 665 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 666 static uint32_t 667 bitrev32(uint32_t x) 668 { 669 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 670 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 671 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 672 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 673 674 return (x >> 16) | (x << 16); 675 } 676 677 static u_int 678 awg_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 679 { 680 uint32_t crc, hashreg, hashbit, *hash = arg; 681 682 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7f; 683 crc = bitrev32(~crc) >> 26; 684 hashreg = (crc >> 5); 685 hashbit = (crc & 0x1f); 686 hash[hashreg] |= (1 << hashbit); 687 688 return (1); 689 } 690 691 static void 692 awg_setup_rxfilter(struct awg_softc *sc) 693 { 694 uint32_t val, hash[2], machi, maclo; 695 uint8_t *eaddr; 696 if_t ifp; 697 698 AWG_ASSERT_LOCKED(sc); 699 700 ifp = sc->ifp; 701 val = 0; 702 hash[0] = hash[1] = 0; 703 704 if (if_getflags(ifp) & IFF_PROMISC) 705 val |= DIS_ADDR_FILTER; 706 else if (if_getflags(ifp) & IFF_ALLMULTI) { 707 val |= RX_ALL_MULTICAST; 708 hash[0] = hash[1] = ~0; 709 } else if (if_foreach_llmaddr(ifp, awg_hash_maddr, hash) > 0) 710 val |= HASH_MULTICAST; 711 712 /* Write our unicast address */ 713 eaddr = IF_LLADDR(ifp); 714 machi = (eaddr[5] << 8) | eaddr[4]; 715 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 716 (eaddr[0] << 0); 717 WR4(sc, EMAC_ADDR_HIGH(0), machi); 718 WR4(sc, EMAC_ADDR_LOW(0), maclo); 719 720 /* Multicast hash filters */ 721 WR4(sc, EMAC_RX_HASH_0, hash[1]); 722 WR4(sc, EMAC_RX_HASH_1, hash[0]); 723 724 /* RX frame filter config */ 725 WR4(sc, EMAC_RX_FRM_FLT, val); 726 } 727 728 static void 729 awg_enable_intr(struct awg_softc *sc) 730 { 731 /* Enable interrupts */ 732 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 733 } 734 735 static void 736 awg_disable_intr(struct awg_softc *sc) 737 { 738 /* Disable interrupts */ 739 WR4(sc, EMAC_INT_EN, 0); 740 } 741 742 static void 743 awg_init_locked(struct awg_softc *sc) 744 { 745 struct mii_data *mii; 746 uint32_t val; 747 if_t ifp; 748 749 mii = device_get_softc(sc->miibus); 750 ifp = sc->ifp; 751 752 AWG_ASSERT_LOCKED(sc); 753 754 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 755 return; 756 757 awg_setup_rxfilter(sc); 758 759 /* Configure DMA burst length and priorities */ 760 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 761 if (awg_rx_tx_pri) 762 val |= BASIC_CTL_RX_TX_PRI; 763 WR4(sc, EMAC_BASIC_CTL_1, val); 764 765 /* Enable interrupts */ 766 #ifdef DEVICE_POLLING 767 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 768 awg_enable_intr(sc); 769 else 770 awg_disable_intr(sc); 771 #else 772 awg_enable_intr(sc); 773 #endif 774 775 /* Enable transmit DMA */ 776 val = RD4(sc, EMAC_TX_CTL_1); 777 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 778 779 /* Enable receive DMA */ 780 val = RD4(sc, EMAC_RX_CTL_1); 781 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 782 783 /* Enable transmitter */ 784 val = RD4(sc, EMAC_TX_CTL_0); 785 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 786 787 /* Enable receiver */ 788 val = RD4(sc, EMAC_RX_CTL_0); 789 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 790 791 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 792 793 mii_mediachg(mii); 794 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 795 } 796 797 static void 798 awg_init(void *softc) 799 { 800 struct awg_softc *sc; 801 802 sc = softc; 803 804 AWG_LOCK(sc); 805 awg_init_locked(sc); 806 AWG_UNLOCK(sc); 807 } 808 809 static void 810 awg_stop(struct awg_softc *sc) 811 { 812 if_t ifp; 813 uint32_t val; 814 int i; 815 816 AWG_ASSERT_LOCKED(sc); 817 818 ifp = sc->ifp; 819 820 callout_stop(&sc->stat_ch); 821 822 /* Stop transmit DMA and flush data in the TX FIFO */ 823 val = RD4(sc, EMAC_TX_CTL_1); 824 val &= ~TX_DMA_EN; 825 val |= FLUSH_TX_FIFO; 826 WR4(sc, EMAC_TX_CTL_1, val); 827 828 /* Disable transmitter */ 829 val = RD4(sc, EMAC_TX_CTL_0); 830 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 831 832 /* Disable receiver */ 833 val = RD4(sc, EMAC_RX_CTL_0); 834 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 835 836 /* Disable interrupts */ 837 awg_disable_intr(sc); 838 839 /* Disable transmit DMA */ 840 val = RD4(sc, EMAC_TX_CTL_1); 841 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 842 843 /* Disable receive DMA */ 844 val = RD4(sc, EMAC_RX_CTL_1); 845 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 846 847 sc->link = 0; 848 849 /* Finish handling transmitted buffers */ 850 awg_txeof(sc); 851 852 /* Release any untransmitted buffers. */ 853 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 854 val = le32toh(sc->tx.desc_ring[i].status); 855 if ((val & TX_DESC_CTL) != 0) 856 break; 857 awg_clean_txbuf(sc, i); 858 } 859 sc->tx.next = i; 860 for (; sc->tx.queued > 0; i = TX_NEXT(i)) { 861 sc->tx.desc_ring[i].status = 0; 862 awg_clean_txbuf(sc, i); 863 } 864 sc->tx.cur = sc->tx.next; 865 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 866 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 867 868 /* Setup RX buffers for reuse */ 869 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 870 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 871 872 for (i = sc->rx.cur; ; i = RX_NEXT(i)) { 873 val = le32toh(sc->rx.desc_ring[i].status); 874 if ((val & RX_DESC_CTL) != 0) 875 break; 876 awg_reuse_rxdesc(sc, i); 877 } 878 sc->rx.cur = i; 879 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 880 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 881 882 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 883 } 884 885 static int 886 awg_rxintr(struct awg_softc *sc) 887 { 888 if_t ifp; 889 struct mbuf *m, *mh, *mt; 890 int error, index, len, cnt, npkt; 891 uint32_t status; 892 893 ifp = sc->ifp; 894 mh = mt = NULL; 895 cnt = 0; 896 npkt = 0; 897 898 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 899 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 900 901 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 902 status = le32toh(sc->rx.desc_ring[index].status); 903 if ((status & RX_DESC_CTL) != 0) 904 break; 905 906 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 907 908 if (len == 0) { 909 if ((status & (RX_NO_ENOUGH_BUF_ERR | RX_OVERFLOW_ERR)) != 0) 910 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 911 awg_reuse_rxdesc(sc, index); 912 continue; 913 } 914 915 m = sc->rx.buf_map[index].mbuf; 916 917 error = awg_newbuf_rx(sc, index); 918 if (error != 0) { 919 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 920 awg_reuse_rxdesc(sc, index); 921 continue; 922 } 923 924 m->m_pkthdr.rcvif = ifp; 925 m->m_pkthdr.len = len; 926 m->m_len = len; 927 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 928 929 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 930 (status & RX_FRM_TYPE) != 0) { 931 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 932 if ((status & RX_HEADER_ERR) == 0) 933 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 934 if ((status & RX_PAYLOAD_ERR) == 0) { 935 m->m_pkthdr.csum_flags |= 936 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 937 m->m_pkthdr.csum_data = 0xffff; 938 } 939 } 940 941 m->m_nextpkt = NULL; 942 if (mh == NULL) 943 mh = m; 944 else 945 mt->m_nextpkt = m; 946 mt = m; 947 ++cnt; 948 ++npkt; 949 950 if (cnt == awg_rx_batch) { 951 AWG_UNLOCK(sc); 952 if_input(ifp, mh); 953 AWG_LOCK(sc); 954 mh = mt = NULL; 955 cnt = 0; 956 } 957 } 958 959 if (index != sc->rx.cur) { 960 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 962 } 963 964 if (mh != NULL) { 965 AWG_UNLOCK(sc); 966 if_input(ifp, mh); 967 AWG_LOCK(sc); 968 } 969 970 sc->rx.cur = index; 971 972 return (npkt); 973 } 974 975 static void 976 awg_txeof(struct awg_softc *sc) 977 { 978 struct emac_desc *desc; 979 uint32_t status, size; 980 if_t ifp; 981 int i, prog; 982 983 AWG_ASSERT_LOCKED(sc); 984 985 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 986 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 987 988 ifp = sc->ifp; 989 990 prog = 0; 991 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 992 desc = &sc->tx.desc_ring[i]; 993 status = le32toh(desc->status); 994 if ((status & TX_DESC_CTL) != 0) 995 break; 996 size = le32toh(desc->size); 997 if (size & TX_LAST_DESC) { 998 if ((status & (TX_HEADER_ERR | TX_PAYLOAD_ERR)) != 0) 999 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1000 else 1001 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1002 } 1003 prog++; 1004 awg_clean_txbuf(sc, i); 1005 } 1006 1007 if (prog > 0) { 1008 sc->tx.next = i; 1009 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1010 } 1011 } 1012 1013 static void 1014 awg_intr(void *arg) 1015 { 1016 struct awg_softc *sc; 1017 uint32_t val; 1018 1019 sc = arg; 1020 1021 AWG_LOCK(sc); 1022 val = RD4(sc, EMAC_INT_STA); 1023 WR4(sc, EMAC_INT_STA, val); 1024 1025 if (val & RX_INT) 1026 awg_rxintr(sc); 1027 1028 if (val & TX_INT) 1029 awg_txeof(sc); 1030 1031 if (val & (TX_INT | TX_BUF_UA_INT)) { 1032 if (!if_sendq_empty(sc->ifp)) 1033 awg_start_locked(sc); 1034 } 1035 1036 AWG_UNLOCK(sc); 1037 } 1038 1039 #ifdef DEVICE_POLLING 1040 static int 1041 awg_poll(if_t ifp, enum poll_cmd cmd, int count) 1042 { 1043 struct awg_softc *sc; 1044 uint32_t val; 1045 int rx_npkts; 1046 1047 sc = if_getsoftc(ifp); 1048 rx_npkts = 0; 1049 1050 AWG_LOCK(sc); 1051 1052 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1053 AWG_UNLOCK(sc); 1054 return (0); 1055 } 1056 1057 rx_npkts = awg_rxintr(sc); 1058 awg_txeof(sc); 1059 if (!if_sendq_empty(ifp)) 1060 awg_start_locked(sc); 1061 1062 if (cmd == POLL_AND_CHECK_STATUS) { 1063 val = RD4(sc, EMAC_INT_STA); 1064 if (val != 0) 1065 WR4(sc, EMAC_INT_STA, val); 1066 } 1067 1068 AWG_UNLOCK(sc); 1069 1070 return (rx_npkts); 1071 } 1072 #endif 1073 1074 static int 1075 awg_ioctl(if_t ifp, u_long cmd, caddr_t data) 1076 { 1077 struct awg_softc *sc; 1078 struct mii_data *mii; 1079 struct ifreq *ifr; 1080 int flags, mask, error; 1081 1082 sc = if_getsoftc(ifp); 1083 mii = device_get_softc(sc->miibus); 1084 ifr = (struct ifreq *)data; 1085 error = 0; 1086 1087 switch (cmd) { 1088 case SIOCSIFFLAGS: 1089 AWG_LOCK(sc); 1090 if (if_getflags(ifp) & IFF_UP) { 1091 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1092 flags = if_getflags(ifp) ^ sc->if_flags; 1093 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) 1094 awg_setup_rxfilter(sc); 1095 } else 1096 awg_init_locked(sc); 1097 } else { 1098 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1099 awg_stop(sc); 1100 } 1101 sc->if_flags = if_getflags(ifp); 1102 AWG_UNLOCK(sc); 1103 break; 1104 case SIOCADDMULTI: 1105 case SIOCDELMULTI: 1106 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1107 AWG_LOCK(sc); 1108 awg_setup_rxfilter(sc); 1109 AWG_UNLOCK(sc); 1110 } 1111 break; 1112 case SIOCSIFMEDIA: 1113 case SIOCGIFMEDIA: 1114 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1115 break; 1116 case SIOCSIFCAP: 1117 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1118 #ifdef DEVICE_POLLING 1119 if (mask & IFCAP_POLLING) { 1120 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1121 error = ether_poll_register(awg_poll, ifp); 1122 if (error != 0) 1123 break; 1124 AWG_LOCK(sc); 1125 awg_disable_intr(sc); 1126 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1127 AWG_UNLOCK(sc); 1128 } else { 1129 error = ether_poll_deregister(ifp); 1130 AWG_LOCK(sc); 1131 awg_enable_intr(sc); 1132 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1133 AWG_UNLOCK(sc); 1134 } 1135 } 1136 #endif 1137 if (mask & IFCAP_VLAN_MTU) 1138 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 1139 if (mask & IFCAP_RXCSUM) 1140 if_togglecapenable(ifp, IFCAP_RXCSUM); 1141 if (mask & IFCAP_TXCSUM) 1142 if_togglecapenable(ifp, IFCAP_TXCSUM); 1143 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1144 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0); 1145 else 1146 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP); 1147 break; 1148 default: 1149 error = ether_ioctl(ifp, cmd, data); 1150 break; 1151 } 1152 1153 return (error); 1154 } 1155 1156 static uint32_t 1157 syscon_read_emac_clk_reg(device_t dev) 1158 { 1159 struct awg_softc *sc; 1160 1161 sc = device_get_softc(dev); 1162 if (sc->syscon != NULL) 1163 return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG)); 1164 else if (sc->res[_RES_SYSCON] != NULL) 1165 return (bus_read_4(sc->res[_RES_SYSCON], 0)); 1166 1167 return (0); 1168 } 1169 1170 static void 1171 syscon_write_emac_clk_reg(device_t dev, uint32_t val) 1172 { 1173 struct awg_softc *sc; 1174 1175 sc = device_get_softc(dev); 1176 if (sc->syscon != NULL) 1177 SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val); 1178 else if (sc->res[_RES_SYSCON] != NULL) 1179 bus_write_4(sc->res[_RES_SYSCON], 0, val); 1180 } 1181 1182 static phandle_t 1183 awg_get_phy_node(device_t dev) 1184 { 1185 phandle_t node; 1186 pcell_t phy_handle; 1187 1188 node = ofw_bus_get_node(dev); 1189 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle, 1190 sizeof(phy_handle)) <= 0) 1191 return (0); 1192 1193 return (OF_node_from_xref(phy_handle)); 1194 } 1195 1196 static bool 1197 awg_has_internal_phy(device_t dev) 1198 { 1199 phandle_t node, phy_node; 1200 1201 node = ofw_bus_get_node(dev); 1202 /* Legacy binding */ 1203 if (OF_hasprop(node, "allwinner,use-internal-phy")) 1204 return (true); 1205 1206 phy_node = awg_get_phy_node(dev); 1207 return (phy_node != 0 && ofw_bus_node_is_compatible(OF_parent(phy_node), 1208 "allwinner,sun8i-h3-mdio-internal") != 0); 1209 } 1210 1211 static int 1212 awg_parse_delay(device_t dev, uint32_t *tx_delay, uint32_t *rx_delay) 1213 { 1214 phandle_t node; 1215 uint32_t delay; 1216 1217 if (tx_delay == NULL || rx_delay == NULL) 1218 return (EINVAL); 1219 *tx_delay = *rx_delay = 0; 1220 node = ofw_bus_get_node(dev); 1221 1222 if (OF_getencprop(node, "tx-delay", &delay, sizeof(delay)) >= 0) 1223 *tx_delay = delay; 1224 else if (OF_getencprop(node, "allwinner,tx-delay-ps", &delay, 1225 sizeof(delay)) >= 0) { 1226 if ((delay % 100) != 0) { 1227 device_printf(dev, "tx-delay-ps is not a multiple of 100\n"); 1228 return (EDOM); 1229 } 1230 *tx_delay = delay / 100; 1231 } 1232 if (*tx_delay > 7) { 1233 device_printf(dev, "tx-delay out of range\n"); 1234 return (ERANGE); 1235 } 1236 1237 if (OF_getencprop(node, "rx-delay", &delay, sizeof(delay)) >= 0) 1238 *rx_delay = delay; 1239 else if (OF_getencprop(node, "allwinner,rx-delay-ps", &delay, 1240 sizeof(delay)) >= 0) { 1241 if ((delay % 100) != 0) { 1242 device_printf(dev, "rx-delay-ps is not within documented domain\n"); 1243 return (EDOM); 1244 } 1245 *rx_delay = delay / 100; 1246 } 1247 if (*rx_delay > 31) { 1248 device_printf(dev, "rx-delay out of range\n"); 1249 return (ERANGE); 1250 } 1251 1252 return (0); 1253 } 1254 1255 static int 1256 awg_setup_phy(device_t dev) 1257 { 1258 struct awg_softc *sc; 1259 clk_t clk_tx, clk_tx_parent; 1260 const char *tx_parent_name; 1261 char *phy_type; 1262 phandle_t node; 1263 uint32_t reg, tx_delay, rx_delay; 1264 int error; 1265 bool use_syscon; 1266 1267 sc = device_get_softc(dev); 1268 node = ofw_bus_get_node(dev); 1269 use_syscon = false; 1270 1271 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_type) == 0) 1272 return (0); 1273 1274 if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL) 1275 use_syscon = true; 1276 1277 if (bootverbose) 1278 device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type, 1279 use_syscon ? "reg" : "clk"); 1280 1281 if (use_syscon) { 1282 /* 1283 * Abstract away writing to syscon for devices like the pine64. 1284 * For the pine64, we get dtb from U-Boot and it still uses the 1285 * legacy setup of specifying syscon register in emac node 1286 * rather than as its own node and using an xref in emac. 1287 * These abstractions can go away once U-Boot dts is up-to-date. 1288 */ 1289 reg = syscon_read_emac_clk_reg(dev); 1290 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 1291 if (strncmp(phy_type, "rgmii", 5) == 0) 1292 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 1293 else if (strcmp(phy_type, "rmii") == 0) 1294 reg |= EMAC_CLK_RMII_EN; 1295 else 1296 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 1297 1298 /* 1299 * Fail attach if we fail to parse either of the delay 1300 * parameters. If we don't have the proper delay to write to 1301 * syscon, then awg likely won't function properly anyways. 1302 * Lack of delay is not an error! 1303 */ 1304 error = awg_parse_delay(dev, &tx_delay, &rx_delay); 1305 if (error != 0) 1306 goto fail; 1307 1308 /* Default to 0 and we'll increase it if we need to. */ 1309 reg &= ~(EMAC_CLK_ETXDC | EMAC_CLK_ERXDC); 1310 if (tx_delay > 0) 1311 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 1312 if (rx_delay > 0) 1313 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 1314 1315 if (sc->type == EMAC_H3) { 1316 if (awg_has_internal_phy(dev)) { 1317 reg |= EMAC_CLK_EPHY_SELECT; 1318 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 1319 if (OF_hasprop(node, 1320 "allwinner,leds-active-low")) 1321 reg |= EMAC_CLK_EPHY_LED_POL; 1322 else 1323 reg &= ~EMAC_CLK_EPHY_LED_POL; 1324 1325 /* Set internal PHY addr to 1 */ 1326 reg &= ~EMAC_CLK_EPHY_ADDR; 1327 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 1328 } else { 1329 reg &= ~EMAC_CLK_EPHY_SELECT; 1330 } 1331 } 1332 1333 if (bootverbose) 1334 device_printf(dev, "EMAC clock: 0x%08x\n", reg); 1335 syscon_write_emac_clk_reg(dev, reg); 1336 } else { 1337 if (strncmp(phy_type, "rgmii", 5) == 0) 1338 tx_parent_name = "emac_int_tx"; 1339 else 1340 tx_parent_name = "mii_phy_tx"; 1341 1342 /* Get the TX clock */ 1343 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx); 1344 if (error != 0) { 1345 device_printf(dev, "cannot get tx clock\n"); 1346 goto fail; 1347 } 1348 1349 /* Find the desired parent clock based on phy-mode property */ 1350 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent); 1351 if (error != 0) { 1352 device_printf(dev, "cannot get clock '%s'\n", 1353 tx_parent_name); 1354 goto fail; 1355 } 1356 1357 /* Set TX clock parent */ 1358 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent); 1359 if (error != 0) { 1360 device_printf(dev, "cannot set tx clock parent\n"); 1361 goto fail; 1362 } 1363 1364 /* Enable TX clock */ 1365 error = clk_enable(clk_tx); 1366 if (error != 0) { 1367 device_printf(dev, "cannot enable tx clock\n"); 1368 goto fail; 1369 } 1370 } 1371 1372 error = 0; 1373 1374 fail: 1375 OF_prop_free(phy_type); 1376 return (error); 1377 } 1378 1379 static int 1380 awg_setup_extres(device_t dev) 1381 { 1382 struct awg_softc *sc; 1383 phandle_t node, phy_node; 1384 hwreset_t rst_ahb, rst_ephy; 1385 clk_t clk_ahb, clk_ephy; 1386 regulator_t reg; 1387 uint64_t freq; 1388 int error, div; 1389 1390 sc = device_get_softc(dev); 1391 rst_ahb = rst_ephy = NULL; 1392 clk_ahb = clk_ephy = NULL; 1393 reg = NULL; 1394 node = ofw_bus_get_node(dev); 1395 phy_node = awg_get_phy_node(dev); 1396 1397 if (phy_node == 0 && OF_hasprop(node, "phy-handle")) { 1398 error = ENXIO; 1399 device_printf(dev, "cannot get phy handle\n"); 1400 goto fail; 1401 } 1402 1403 /* Get AHB clock and reset resources */ 1404 error = hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst_ahb); 1405 if (error != 0) 1406 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb); 1407 if (error != 0) { 1408 device_printf(dev, "cannot get ahb reset\n"); 1409 goto fail; 1410 } 1411 if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0) 1412 if (phy_node == 0 || hwreset_get_by_ofw_idx(dev, phy_node, 0, 1413 &rst_ephy) != 0) 1414 rst_ephy = NULL; 1415 error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk_ahb); 1416 if (error != 0) 1417 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb); 1418 if (error != 0) { 1419 device_printf(dev, "cannot get ahb clock\n"); 1420 goto fail; 1421 } 1422 if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0) 1423 if (phy_node == 0 || clk_get_by_ofw_index(dev, phy_node, 0, 1424 &clk_ephy) != 0) 1425 clk_ephy = NULL; 1426 1427 if (OF_hasprop(node, "syscon") && syscon_get_by_ofw_property(dev, node, 1428 "syscon", &sc->syscon) != 0) { 1429 device_printf(dev, "cannot get syscon driver handle\n"); 1430 goto fail; 1431 } 1432 1433 /* Configure PHY for MII or RGMII mode */ 1434 if (awg_setup_phy(dev) != 0) 1435 goto fail; 1436 1437 /* Enable clocks */ 1438 error = clk_enable(clk_ahb); 1439 if (error != 0) { 1440 device_printf(dev, "cannot enable ahb clock\n"); 1441 goto fail; 1442 } 1443 if (clk_ephy != NULL) { 1444 error = clk_enable(clk_ephy); 1445 if (error != 0) { 1446 device_printf(dev, "cannot enable ephy clock\n"); 1447 goto fail; 1448 } 1449 } 1450 1451 /* De-assert reset */ 1452 error = hwreset_deassert(rst_ahb); 1453 if (error != 0) { 1454 device_printf(dev, "cannot de-assert ahb reset\n"); 1455 goto fail; 1456 } 1457 if (rst_ephy != NULL) { 1458 /* 1459 * The ephy reset is left de-asserted by U-Boot. Assert it 1460 * here to make sure that we're in a known good state going 1461 * into the PHY reset. 1462 */ 1463 hwreset_assert(rst_ephy); 1464 error = hwreset_deassert(rst_ephy); 1465 if (error != 0) { 1466 device_printf(dev, "cannot de-assert ephy reset\n"); 1467 goto fail; 1468 } 1469 } 1470 1471 /* Enable PHY regulator if applicable */ 1472 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) { 1473 error = regulator_enable(reg); 1474 if (error != 0) { 1475 device_printf(dev, "cannot enable PHY regulator\n"); 1476 goto fail; 1477 } 1478 } 1479 1480 /* Determine MDC clock divide ratio based on AHB clock */ 1481 error = clk_get_freq(clk_ahb, &freq); 1482 if (error != 0) { 1483 device_printf(dev, "cannot get AHB clock frequency\n"); 1484 goto fail; 1485 } 1486 div = freq / MDIO_FREQ; 1487 if (div <= 16) 1488 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1489 else if (div <= 32) 1490 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1491 else if (div <= 64) 1492 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1493 else if (div <= 128) 1494 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1495 else { 1496 device_printf(dev, "cannot determine MDC clock divide ratio\n"); 1497 error = ENXIO; 1498 goto fail; 1499 } 1500 1501 if (bootverbose) 1502 device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n", 1503 (uintmax_t)freq, sc->mdc_div_ratio_m); 1504 1505 return (0); 1506 1507 fail: 1508 if (reg != NULL) 1509 regulator_release(reg); 1510 if (clk_ephy != NULL) 1511 clk_release(clk_ephy); 1512 if (clk_ahb != NULL) 1513 clk_release(clk_ahb); 1514 if (rst_ephy != NULL) 1515 hwreset_release(rst_ephy); 1516 if (rst_ahb != NULL) 1517 hwreset_release(rst_ahb); 1518 return (error); 1519 } 1520 1521 static void 1522 awg_get_eaddr(device_t dev, uint8_t *eaddr) 1523 { 1524 struct awg_softc *sc; 1525 uint32_t maclo, machi, rnd; 1526 u_char rootkey[16]; 1527 uint32_t rootkey_size; 1528 1529 sc = device_get_softc(dev); 1530 1531 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1532 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1533 1534 rootkey_size = sizeof(rootkey); 1535 if (maclo == 0xffffffff && machi == 0xffff) { 1536 /* MAC address in hardware is invalid, create one */ 1537 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey, 1538 &rootkey_size) == 0 && 1539 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1540 rootkey[15]) != 0) { 1541 /* MAC address is derived from the root key in SID */ 1542 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1543 (rootkey[3] << 8) | 0x02; 1544 machi = (rootkey[15] << 8) | rootkey[14]; 1545 } else { 1546 /* Create one */ 1547 rnd = arc4random(); 1548 maclo = 0x00f2 | (rnd & 0xffff0000); 1549 machi = rnd & 0xffff; 1550 } 1551 } 1552 1553 eaddr[0] = maclo & 0xff; 1554 eaddr[1] = (maclo >> 8) & 0xff; 1555 eaddr[2] = (maclo >> 16) & 0xff; 1556 eaddr[3] = (maclo >> 24) & 0xff; 1557 eaddr[4] = machi & 0xff; 1558 eaddr[5] = (machi >> 8) & 0xff; 1559 } 1560 1561 #ifdef AWG_DEBUG 1562 static void 1563 awg_dump_regs(device_t dev) 1564 { 1565 static const struct { 1566 const char *name; 1567 u_int reg; 1568 } regs[] = { 1569 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1570 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1571 { "INT_STA", EMAC_INT_STA }, 1572 { "INT_EN", EMAC_INT_EN }, 1573 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1574 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1575 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1576 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1577 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1578 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1579 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1580 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1581 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1582 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1583 { "MII_CMD", EMAC_MII_CMD }, 1584 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1585 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1586 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1587 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1588 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1589 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1590 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1591 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1592 { "RGMII_STA", EMAC_RGMII_STA }, 1593 }; 1594 struct awg_softc *sc; 1595 unsigned int n; 1596 1597 sc = device_get_softc(dev); 1598 1599 for (n = 0; n < nitems(regs); n++) 1600 device_printf(dev, " %-20s %08x\n", regs[n].name, 1601 RD4(sc, regs[n].reg)); 1602 } 1603 #endif 1604 1605 #define GPIO_ACTIVE_LOW 1 1606 1607 static int 1608 awg_phy_reset(device_t dev) 1609 { 1610 pcell_t gpio_prop[4], delay_prop[3]; 1611 phandle_t node, gpio_node; 1612 device_t gpio; 1613 uint32_t pin, flags; 1614 uint32_t pin_value; 1615 1616 node = ofw_bus_get_node(dev); 1617 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop, 1618 sizeof(gpio_prop)) <= 0) 1619 return (0); 1620 1621 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop, 1622 sizeof(delay_prop)) <= 0) 1623 return (ENXIO); 1624 1625 gpio_node = OF_node_from_xref(gpio_prop[0]); 1626 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) 1627 return (ENXIO); 1628 1629 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1, 1630 gpio_prop + 1, &pin, &flags) != 0) 1631 return (ENXIO); 1632 1633 pin_value = GPIO_PIN_LOW; 1634 if (OF_hasprop(node, "allwinner,reset-active-low")) 1635 pin_value = GPIO_PIN_HIGH; 1636 1637 if (flags & GPIO_ACTIVE_LOW) 1638 pin_value = !pin_value; 1639 1640 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 1641 GPIO_PIN_SET(gpio, pin, pin_value); 1642 DELAY(delay_prop[0]); 1643 GPIO_PIN_SET(gpio, pin, !pin_value); 1644 DELAY(delay_prop[1]); 1645 GPIO_PIN_SET(gpio, pin, pin_value); 1646 DELAY(delay_prop[2]); 1647 1648 return (0); 1649 } 1650 1651 static int 1652 awg_reset(device_t dev) 1653 { 1654 struct awg_softc *sc; 1655 int retry; 1656 1657 sc = device_get_softc(dev); 1658 1659 /* Reset PHY if necessary */ 1660 if (awg_phy_reset(dev) != 0) { 1661 device_printf(dev, "failed to reset PHY\n"); 1662 return (ENXIO); 1663 } 1664 1665 /* Soft reset all registers and logic */ 1666 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1667 1668 /* Wait for soft reset bit to self-clear */ 1669 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1670 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1671 break; 1672 DELAY(10); 1673 } 1674 if (retry == 0) { 1675 device_printf(dev, "soft reset timed out\n"); 1676 #ifdef AWG_DEBUG 1677 awg_dump_regs(dev); 1678 #endif 1679 return (ETIMEDOUT); 1680 } 1681 1682 return (0); 1683 } 1684 1685 static void 1686 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1687 { 1688 if (error != 0) 1689 return; 1690 *(bus_addr_t *)arg = segs[0].ds_addr; 1691 } 1692 1693 static int 1694 awg_setup_dma(device_t dev) 1695 { 1696 struct awg_softc *sc; 1697 int error, i; 1698 1699 sc = device_get_softc(dev); 1700 1701 /* Setup TX ring */ 1702 error = bus_dma_tag_create( 1703 bus_get_dma_tag(dev), /* Parent tag */ 1704 DESC_ALIGN, 0, /* alignment, boundary */ 1705 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1706 BUS_SPACE_MAXADDR, /* highaddr */ 1707 NULL, NULL, /* filter, filterarg */ 1708 TX_DESC_SIZE, 1, /* maxsize, nsegs */ 1709 TX_DESC_SIZE, /* maxsegsize */ 1710 0, /* flags */ 1711 NULL, NULL, /* lockfunc, lockarg */ 1712 &sc->tx.desc_tag); 1713 if (error != 0) { 1714 device_printf(dev, "cannot create TX descriptor ring tag\n"); 1715 return (error); 1716 } 1717 1718 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring, 1719 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map); 1720 if (error != 0) { 1721 device_printf(dev, "cannot allocate TX descriptor ring\n"); 1722 return (error); 1723 } 1724 1725 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map, 1726 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb, 1727 &sc->tx.desc_ring_paddr, 0); 1728 if (error != 0) { 1729 device_printf(dev, "cannot load TX descriptor ring\n"); 1730 return (error); 1731 } 1732 1733 for (i = 0; i < TX_DESC_COUNT; i++) 1734 sc->tx.desc_ring[i].next = 1735 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1736 1737 error = bus_dma_tag_create( 1738 bus_get_dma_tag(dev), /* Parent tag */ 1739 1, 0, /* alignment, boundary */ 1740 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1741 BUS_SPACE_MAXADDR, /* highaddr */ 1742 NULL, NULL, /* filter, filterarg */ 1743 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */ 1744 MCLBYTES, /* maxsegsize */ 1745 0, /* flags */ 1746 NULL, NULL, /* lockfunc, lockarg */ 1747 &sc->tx.buf_tag); 1748 if (error != 0) { 1749 device_printf(dev, "cannot create TX buffer tag\n"); 1750 return (error); 1751 } 1752 1753 sc->tx.queued = 0; 1754 for (i = 0; i < TX_DESC_COUNT; i++) { 1755 error = bus_dmamap_create(sc->tx.buf_tag, 0, 1756 &sc->tx.buf_map[i].map); 1757 if (error != 0) { 1758 device_printf(dev, "cannot create TX buffer map\n"); 1759 return (error); 1760 } 1761 } 1762 1763 /* Setup RX ring */ 1764 error = bus_dma_tag_create( 1765 bus_get_dma_tag(dev), /* Parent tag */ 1766 DESC_ALIGN, 0, /* alignment, boundary */ 1767 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1768 BUS_SPACE_MAXADDR, /* highaddr */ 1769 NULL, NULL, /* filter, filterarg */ 1770 RX_DESC_SIZE, 1, /* maxsize, nsegs */ 1771 RX_DESC_SIZE, /* maxsegsize */ 1772 0, /* flags */ 1773 NULL, NULL, /* lockfunc, lockarg */ 1774 &sc->rx.desc_tag); 1775 if (error != 0) { 1776 device_printf(dev, "cannot create RX descriptor ring tag\n"); 1777 return (error); 1778 } 1779 1780 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring, 1781 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map); 1782 if (error != 0) { 1783 device_printf(dev, "cannot allocate RX descriptor ring\n"); 1784 return (error); 1785 } 1786 1787 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map, 1788 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb, 1789 &sc->rx.desc_ring_paddr, 0); 1790 if (error != 0) { 1791 device_printf(dev, "cannot load RX descriptor ring\n"); 1792 return (error); 1793 } 1794 1795 error = bus_dma_tag_create( 1796 bus_get_dma_tag(dev), /* Parent tag */ 1797 1, 0, /* alignment, boundary */ 1798 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1799 BUS_SPACE_MAXADDR, /* highaddr */ 1800 NULL, NULL, /* filter, filterarg */ 1801 MCLBYTES, 1, /* maxsize, nsegs */ 1802 MCLBYTES, /* maxsegsize */ 1803 0, /* flags */ 1804 NULL, NULL, /* lockfunc, lockarg */ 1805 &sc->rx.buf_tag); 1806 if (error != 0) { 1807 device_printf(dev, "cannot create RX buffer tag\n"); 1808 return (error); 1809 } 1810 1811 error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map); 1812 if (error != 0) { 1813 device_printf(dev, 1814 "cannot create RX buffer spare map\n"); 1815 return (error); 1816 } 1817 1818 for (i = 0; i < RX_DESC_COUNT; i++) { 1819 sc->rx.desc_ring[i].next = 1820 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i))); 1821 1822 error = bus_dmamap_create(sc->rx.buf_tag, 0, 1823 &sc->rx.buf_map[i].map); 1824 if (error != 0) { 1825 device_printf(dev, "cannot create RX buffer map\n"); 1826 return (error); 1827 } 1828 sc->rx.buf_map[i].mbuf = NULL; 1829 error = awg_newbuf_rx(sc, i); 1830 if (error != 0) { 1831 device_printf(dev, "cannot create RX buffer\n"); 1832 return (error); 1833 } 1834 } 1835 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1836 BUS_DMASYNC_PREWRITE); 1837 1838 /* Write transmit and receive descriptor base address registers */ 1839 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1840 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1841 1842 return (0); 1843 } 1844 1845 static int 1846 awg_probe(device_t dev) 1847 { 1848 if (!ofw_bus_status_okay(dev)) 1849 return (ENXIO); 1850 1851 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1852 return (ENXIO); 1853 1854 device_set_desc(dev, "Allwinner Gigabit Ethernet"); 1855 return (BUS_PROBE_DEFAULT); 1856 } 1857 1858 static int 1859 awg_attach(device_t dev) 1860 { 1861 uint8_t eaddr[ETHER_ADDR_LEN]; 1862 struct awg_softc *sc; 1863 int error; 1864 1865 sc = device_get_softc(dev); 1866 sc->dev = dev; 1867 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1868 1869 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) { 1870 device_printf(dev, "cannot allocate resources for device\n"); 1871 return (ENXIO); 1872 } 1873 1874 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 1875 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0); 1876 TASK_INIT(&sc->link_task, 0, awg_link_task, sc); 1877 1878 /* Setup clocks and regulators */ 1879 error = awg_setup_extres(dev); 1880 if (error != 0) 1881 return (error); 1882 1883 /* Read MAC address before resetting the chip */ 1884 awg_get_eaddr(dev, eaddr); 1885 1886 /* Soft reset EMAC core */ 1887 error = awg_reset(dev); 1888 if (error != 0) 1889 return (error); 1890 1891 /* Setup DMA descriptors */ 1892 error = awg_setup_dma(dev); 1893 if (error != 0) 1894 return (error); 1895 1896 /* Install interrupt handler */ 1897 error = bus_setup_intr(dev, sc->res[_RES_IRQ], 1898 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih); 1899 if (error != 0) { 1900 device_printf(dev, "cannot setup interrupt handler\n"); 1901 return (error); 1902 } 1903 1904 /* Setup ethernet interface */ 1905 sc->ifp = if_alloc(IFT_ETHER); 1906 if_setsoftc(sc->ifp, sc); 1907 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev)); 1908 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1909 if_setstartfn(sc->ifp, awg_start); 1910 if_setioctlfn(sc->ifp, awg_ioctl); 1911 if_setinitfn(sc->ifp, awg_init); 1912 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1); 1913 if_setsendqready(sc->ifp); 1914 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); 1915 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM); 1916 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp)); 1917 #ifdef DEVICE_POLLING 1918 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0); 1919 #endif 1920 1921 /* Attach MII driver */ 1922 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change, 1923 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 1924 MIIF_DOPAUSE); 1925 if (error != 0) { 1926 device_printf(dev, "cannot attach PHY\n"); 1927 return (error); 1928 } 1929 1930 /* Attach ethernet interface */ 1931 ether_ifattach(sc->ifp, eaddr); 1932 1933 return (0); 1934 } 1935 1936 static device_method_t awg_methods[] = { 1937 /* Device interface */ 1938 DEVMETHOD(device_probe, awg_probe), 1939 DEVMETHOD(device_attach, awg_attach), 1940 1941 /* MII interface */ 1942 DEVMETHOD(miibus_readreg, awg_miibus_readreg), 1943 DEVMETHOD(miibus_writereg, awg_miibus_writereg), 1944 DEVMETHOD(miibus_statchg, awg_miibus_statchg), 1945 1946 DEVMETHOD_END 1947 }; 1948 1949 static driver_t awg_driver = { 1950 "awg", 1951 awg_methods, 1952 sizeof(struct awg_softc), 1953 }; 1954 1955 static devclass_t awg_devclass; 1956 1957 DRIVER_MODULE(awg, simplebus, awg_driver, awg_devclass, 0, 0); 1958 DRIVER_MODULE(miibus, awg, miibus_driver, miibus_devclass, 0, 0); 1959 MODULE_DEPEND(awg, ether, 1, 1, 1); 1960 MODULE_DEPEND(awg, miibus, 1, 1, 1); 1961 MODULE_DEPEND(awg, aw_sid, 1, 1, 1); 1962 SIMPLEBUS_PNP_INFO(compat_data); 1963