1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_device_polling.h" 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/rman.h> 42 #include <sys/kernel.h> 43 #include <sys/endian.h> 44 #include <sys/mbuf.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/module.h> 48 #include <sys/taskqueue.h> 49 #include <sys/gpio.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_var.h> 58 59 #include <machine/bus.h> 60 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 64 #include <arm/allwinner/if_awgreg.h> 65 #include <arm/allwinner/aw_sid.h> 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/extres/clk/clk.h> 70 #include <dev/extres/hwreset/hwreset.h> 71 #include <dev/extres/regulator/regulator.h> 72 73 #include "miibus_if.h" 74 #include "gpio_if.h" 75 76 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg)) 77 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val)) 78 79 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx) 80 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx); 81 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 82 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 83 84 #define DESC_ALIGN 4 85 #define TX_DESC_COUNT 1024 86 #define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT) 87 #define RX_DESC_COUNT 256 88 #define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT) 89 90 #define DESC_OFF(n) ((n) * sizeof(struct emac_desc)) 91 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 92 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 93 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 94 95 #define TX_MAX_SEGS 10 96 97 #define SOFT_RST_RETRY 1000 98 #define MII_BUSY_RETRY 1000 99 #define MDIO_FREQ 2500000 100 101 #define BURST_LEN_DEFAULT 8 102 #define RX_TX_PRI_DEFAULT 0 103 #define PAUSE_TIME_DEFAULT 0x400 104 #define TX_INTERVAL_DEFAULT 64 105 #define RX_BATCH_DEFAULT 64 106 107 /* syscon EMAC clock register */ 108 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 109 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 110 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 111 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 112 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 113 #define EMAC_CLK_RMII_EN (1 << 13) 114 #define EMAC_CLK_ETXDC (0x7 << 10) 115 #define EMAC_CLK_ETXDC_SHIFT 10 116 #define EMAC_CLK_ERXDC (0x1f << 5) 117 #define EMAC_CLK_ERXDC_SHIFT 5 118 #define EMAC_CLK_PIT (0x1 << 2) 119 #define EMAC_CLK_PIT_MII (0 << 2) 120 #define EMAC_CLK_PIT_RGMII (1 << 2) 121 #define EMAC_CLK_SRC (0x3 << 0) 122 #define EMAC_CLK_SRC_MII (0 << 0) 123 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 124 #define EMAC_CLK_SRC_RGMII (2 << 0) 125 126 /* Burst length of RX and TX DMA transfers */ 127 static int awg_burst_len = BURST_LEN_DEFAULT; 128 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len); 129 130 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 131 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT; 132 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri); 133 134 /* Pause time field in the transmitted control frame */ 135 static int awg_pause_time = PAUSE_TIME_DEFAULT; 136 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time); 137 138 /* Request a TX interrupt every <n> descriptors */ 139 static int awg_tx_interval = TX_INTERVAL_DEFAULT; 140 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval); 141 142 /* Maximum number of mbufs to send to if_input */ 143 static int awg_rx_batch = RX_BATCH_DEFAULT; 144 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch); 145 146 enum awg_type { 147 EMAC_A83T = 1, 148 EMAC_H3, 149 }; 150 151 static struct ofw_compat_data compat_data[] = { 152 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 153 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 154 { NULL, 0 } 155 }; 156 157 struct awg_bufmap { 158 bus_dmamap_t map; 159 struct mbuf *mbuf; 160 }; 161 162 struct awg_txring { 163 bus_dma_tag_t desc_tag; 164 bus_dmamap_t desc_map; 165 struct emac_desc *desc_ring; 166 bus_addr_t desc_ring_paddr; 167 bus_dma_tag_t buf_tag; 168 struct awg_bufmap buf_map[TX_DESC_COUNT]; 169 u_int cur, next, queued; 170 }; 171 172 struct awg_rxring { 173 bus_dma_tag_t desc_tag; 174 bus_dmamap_t desc_map; 175 struct emac_desc *desc_ring; 176 bus_addr_t desc_ring_paddr; 177 bus_dma_tag_t buf_tag; 178 struct awg_bufmap buf_map[RX_DESC_COUNT]; 179 u_int cur; 180 }; 181 182 enum { 183 _RES_EMAC, 184 _RES_IRQ, 185 _RES_SYSCON, 186 _RES_NITEMS 187 }; 188 189 struct awg_softc { 190 struct resource *res[_RES_NITEMS]; 191 struct mtx mtx; 192 if_t ifp; 193 device_t miibus; 194 struct callout stat_ch; 195 struct task link_task; 196 void *ih; 197 u_int mdc_div_ratio_m; 198 int link; 199 int if_flags; 200 enum awg_type type; 201 202 struct awg_txring tx; 203 struct awg_rxring rx; 204 }; 205 206 static struct resource_spec awg_spec[] = { 207 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 208 { SYS_RES_IRQ, 0, RF_ACTIVE }, 209 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 210 { -1, 0 } 211 }; 212 213 static int 214 awg_miibus_readreg(device_t dev, int phy, int reg) 215 { 216 struct awg_softc *sc; 217 int retry, val; 218 219 sc = device_get_softc(dev); 220 val = 0; 221 222 WR4(sc, EMAC_MII_CMD, 223 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 224 (phy << PHY_ADDR_SHIFT) | 225 (reg << PHY_REG_ADDR_SHIFT) | 226 MII_BUSY); 227 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 228 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 229 val = RD4(sc, EMAC_MII_DATA); 230 break; 231 } 232 DELAY(10); 233 } 234 235 if (retry == 0) 236 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 237 phy, reg); 238 239 return (val); 240 } 241 242 static int 243 awg_miibus_writereg(device_t dev, int phy, int reg, int val) 244 { 245 struct awg_softc *sc; 246 int retry; 247 248 sc = device_get_softc(dev); 249 250 WR4(sc, EMAC_MII_DATA, val); 251 WR4(sc, EMAC_MII_CMD, 252 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 253 (phy << PHY_ADDR_SHIFT) | 254 (reg << PHY_REG_ADDR_SHIFT) | 255 MII_WR | MII_BUSY); 256 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 257 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 258 break; 259 DELAY(10); 260 } 261 262 if (retry == 0) 263 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 264 phy, reg); 265 266 return (0); 267 } 268 269 static void 270 awg_update_link_locked(struct awg_softc *sc) 271 { 272 struct mii_data *mii; 273 uint32_t val; 274 275 AWG_ASSERT_LOCKED(sc); 276 277 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) 278 return; 279 mii = device_get_softc(sc->miibus); 280 281 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 282 (IFM_ACTIVE | IFM_AVALID)) { 283 switch (IFM_SUBTYPE(mii->mii_media_active)) { 284 case IFM_1000_T: 285 case IFM_1000_SX: 286 case IFM_100_TX: 287 case IFM_10_T: 288 sc->link = 1; 289 break; 290 default: 291 sc->link = 0; 292 break; 293 } 294 } else 295 sc->link = 0; 296 297 if (sc->link == 0) 298 return; 299 300 val = RD4(sc, EMAC_BASIC_CTL_0); 301 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 302 303 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 304 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 305 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 306 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 307 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 308 else 309 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 310 311 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 312 val |= BASIC_CTL_DUPLEX; 313 314 WR4(sc, EMAC_BASIC_CTL_0, val); 315 316 val = RD4(sc, EMAC_RX_CTL_0); 317 val &= ~RX_FLOW_CTL_EN; 318 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 319 val |= RX_FLOW_CTL_EN; 320 WR4(sc, EMAC_RX_CTL_0, val); 321 322 val = RD4(sc, EMAC_TX_FLOW_CTL); 323 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 324 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 325 val |= TX_FLOW_CTL_EN; 326 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 327 val |= awg_pause_time << PAUSE_TIME_SHIFT; 328 WR4(sc, EMAC_TX_FLOW_CTL, val); 329 } 330 331 static void 332 awg_link_task(void *arg, int pending) 333 { 334 struct awg_softc *sc; 335 336 sc = arg; 337 338 AWG_LOCK(sc); 339 awg_update_link_locked(sc); 340 AWG_UNLOCK(sc); 341 } 342 343 static void 344 awg_miibus_statchg(device_t dev) 345 { 346 struct awg_softc *sc; 347 348 sc = device_get_softc(dev); 349 350 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 351 } 352 353 static void 354 awg_media_status(if_t ifp, struct ifmediareq *ifmr) 355 { 356 struct awg_softc *sc; 357 struct mii_data *mii; 358 359 sc = if_getsoftc(ifp); 360 mii = device_get_softc(sc->miibus); 361 362 AWG_LOCK(sc); 363 mii_pollstat(mii); 364 ifmr->ifm_active = mii->mii_media_active; 365 ifmr->ifm_status = mii->mii_media_status; 366 AWG_UNLOCK(sc); 367 } 368 369 static int 370 awg_media_change(if_t ifp) 371 { 372 struct awg_softc *sc; 373 struct mii_data *mii; 374 int error; 375 376 sc = if_getsoftc(ifp); 377 mii = device_get_softc(sc->miibus); 378 379 AWG_LOCK(sc); 380 error = mii_mediachg(mii); 381 AWG_UNLOCK(sc); 382 383 return (error); 384 } 385 386 static void 387 awg_setup_txdesc(struct awg_softc *sc, int index, int flags, bus_addr_t paddr, 388 u_int len) 389 { 390 uint32_t status, size; 391 392 if (paddr == 0 || len == 0) { 393 status = 0; 394 size = 0; 395 --sc->tx.queued; 396 } else { 397 status = TX_DESC_CTL; 398 size = flags | len; 399 if ((index & (awg_tx_interval - 1)) == 0) 400 size |= TX_INT_CTL; 401 ++sc->tx.queued; 402 } 403 404 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 405 sc->tx.desc_ring[index].size = htole32(size); 406 sc->tx.desc_ring[index].status = htole32(status); 407 } 408 409 static int 410 awg_setup_txbuf(struct awg_softc *sc, int index, struct mbuf **mp) 411 { 412 bus_dma_segment_t segs[TX_MAX_SEGS]; 413 int error, nsegs, cur, i, flags; 414 u_int csum_flags; 415 struct mbuf *m; 416 417 m = *mp; 418 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, 419 sc->tx.buf_map[index].map, m, segs, &nsegs, BUS_DMA_NOWAIT); 420 if (error == EFBIG) { 421 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS); 422 if (m == NULL) 423 return (0); 424 *mp = m; 425 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, 426 sc->tx.buf_map[index].map, m, segs, &nsegs, BUS_DMA_NOWAIT); 427 } 428 if (error != 0) 429 return (0); 430 431 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 432 BUS_DMASYNC_PREWRITE); 433 434 flags = TX_FIR_DESC; 435 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) { 436 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) 437 csum_flags = TX_CHECKSUM_CTL_FULL; 438 else 439 csum_flags = TX_CHECKSUM_CTL_IP; 440 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 441 } 442 443 for (cur = index, i = 0; i < nsegs; i++) { 444 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 445 if (i == nsegs - 1) 446 flags |= TX_LAST_DESC; 447 awg_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 448 segs[i].ds_len); 449 flags &= ~TX_FIR_DESC; 450 cur = TX_NEXT(cur); 451 } 452 453 return (nsegs); 454 } 455 456 static void 457 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr) 458 { 459 uint32_t status, size; 460 461 status = RX_DESC_CTL; 462 size = MCLBYTES - 1; 463 464 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 465 sc->rx.desc_ring[index].size = htole32(size); 466 sc->rx.desc_ring[index].next = 467 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 468 sc->rx.desc_ring[index].status = htole32(status); 469 } 470 471 static int 472 awg_setup_rxbuf(struct awg_softc *sc, int index, struct mbuf *m) 473 { 474 bus_dma_segment_t seg; 475 int error, nsegs; 476 477 m_adj(m, ETHER_ALIGN); 478 479 error = bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, 480 sc->rx.buf_map[index].map, m, &seg, &nsegs, 0); 481 if (error != 0) 482 return (error); 483 484 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 485 BUS_DMASYNC_PREREAD); 486 487 sc->rx.buf_map[index].mbuf = m; 488 awg_setup_rxdesc(sc, index, seg.ds_addr); 489 490 return (0); 491 } 492 493 static struct mbuf * 494 awg_alloc_mbufcl(struct awg_softc *sc) 495 { 496 struct mbuf *m; 497 498 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 499 if (m != NULL) 500 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 501 502 return (m); 503 } 504 505 static void 506 awg_start_locked(struct awg_softc *sc) 507 { 508 struct mbuf *m; 509 uint32_t val; 510 if_t ifp; 511 int cnt, nsegs; 512 513 AWG_ASSERT_LOCKED(sc); 514 515 if (!sc->link) 516 return; 517 518 ifp = sc->ifp; 519 520 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 521 IFF_DRV_RUNNING) 522 return; 523 524 for (cnt = 0; ; cnt++) { 525 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 526 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 527 break; 528 } 529 530 m = if_dequeue(ifp); 531 if (m == NULL) 532 break; 533 534 nsegs = awg_setup_txbuf(sc, sc->tx.cur, &m); 535 if (nsegs == 0) { 536 if_sendq_prepend(ifp, m); 537 break; 538 } 539 if_bpfmtap(ifp, m); 540 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 541 } 542 543 if (cnt != 0) { 544 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 545 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 546 547 /* Start and run TX DMA */ 548 val = RD4(sc, EMAC_TX_CTL_1); 549 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 550 } 551 } 552 553 static void 554 awg_start(if_t ifp) 555 { 556 struct awg_softc *sc; 557 558 sc = if_getsoftc(ifp); 559 560 AWG_LOCK(sc); 561 awg_start_locked(sc); 562 AWG_UNLOCK(sc); 563 } 564 565 static void 566 awg_tick(void *softc) 567 { 568 struct awg_softc *sc; 569 struct mii_data *mii; 570 if_t ifp; 571 int link; 572 573 sc = softc; 574 ifp = sc->ifp; 575 mii = device_get_softc(sc->miibus); 576 577 AWG_ASSERT_LOCKED(sc); 578 579 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 580 return; 581 582 link = sc->link; 583 mii_tick(mii); 584 if (sc->link && !link) 585 awg_start_locked(sc); 586 587 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 588 } 589 590 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 591 static uint32_t 592 bitrev32(uint32_t x) 593 { 594 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 595 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 596 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 597 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 598 599 return (x >> 16) | (x << 16); 600 } 601 602 static void 603 awg_setup_rxfilter(struct awg_softc *sc) 604 { 605 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 606 int mc_count, mcnt, i; 607 uint8_t *eaddr, *mta; 608 if_t ifp; 609 610 AWG_ASSERT_LOCKED(sc); 611 612 ifp = sc->ifp; 613 val = 0; 614 hash[0] = hash[1] = 0; 615 616 mc_count = if_multiaddr_count(ifp, -1); 617 618 if (if_getflags(ifp) & IFF_PROMISC) 619 val |= DIS_ADDR_FILTER; 620 else if (if_getflags(ifp) & IFF_ALLMULTI) { 621 val |= RX_ALL_MULTICAST; 622 hash[0] = hash[1] = ~0; 623 } else if (mc_count > 0) { 624 val |= HASH_MULTICAST; 625 626 mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN * mc_count, 627 M_DEVBUF, M_NOWAIT); 628 if (mta == NULL) { 629 if_printf(ifp, 630 "failed to allocate temporary multicast list\n"); 631 return; 632 } 633 634 if_multiaddr_array(ifp, mta, &mcnt, mc_count); 635 for (i = 0; i < mcnt; i++) { 636 crc = ether_crc32_le(mta + (i * ETHER_ADDR_LEN), 637 ETHER_ADDR_LEN) & 0x7f; 638 crc = bitrev32(~crc) >> 26; 639 hashreg = (crc >> 5); 640 hashbit = (crc & 0x1f); 641 hash[hashreg] |= (1 << hashbit); 642 } 643 644 free(mta, M_DEVBUF); 645 } 646 647 /* Write our unicast address */ 648 eaddr = IF_LLADDR(ifp); 649 machi = (eaddr[5] << 8) | eaddr[4]; 650 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 651 (eaddr[0] << 0); 652 WR4(sc, EMAC_ADDR_HIGH(0), machi); 653 WR4(sc, EMAC_ADDR_LOW(0), maclo); 654 655 /* Multicast hash filters */ 656 WR4(sc, EMAC_RX_HASH_0, hash[1]); 657 WR4(sc, EMAC_RX_HASH_1, hash[0]); 658 659 /* RX frame filter config */ 660 WR4(sc, EMAC_RX_FRM_FLT, val); 661 } 662 663 static void 664 awg_enable_intr(struct awg_softc *sc) 665 { 666 /* Enable interrupts */ 667 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 668 } 669 670 static void 671 awg_disable_intr(struct awg_softc *sc) 672 { 673 /* Disable interrupts */ 674 WR4(sc, EMAC_INT_EN, 0); 675 } 676 677 static void 678 awg_init_locked(struct awg_softc *sc) 679 { 680 struct mii_data *mii; 681 uint32_t val; 682 if_t ifp; 683 684 mii = device_get_softc(sc->miibus); 685 ifp = sc->ifp; 686 687 AWG_ASSERT_LOCKED(sc); 688 689 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 690 return; 691 692 awg_setup_rxfilter(sc); 693 694 /* Configure DMA burst length and priorities */ 695 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 696 if (awg_rx_tx_pri) 697 val |= BASIC_CTL_RX_TX_PRI; 698 WR4(sc, EMAC_BASIC_CTL_1, val); 699 700 /* Enable interrupts */ 701 #ifdef DEVICE_POLLING 702 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 703 awg_enable_intr(sc); 704 else 705 awg_disable_intr(sc); 706 #else 707 awg_enable_intr(sc); 708 #endif 709 710 /* Enable transmit DMA */ 711 val = RD4(sc, EMAC_TX_CTL_1); 712 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 713 714 /* Enable receive DMA */ 715 val = RD4(sc, EMAC_RX_CTL_1); 716 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 717 718 /* Enable transmitter */ 719 val = RD4(sc, EMAC_TX_CTL_0); 720 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 721 722 /* Enable receiver */ 723 val = RD4(sc, EMAC_RX_CTL_0); 724 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 725 726 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 727 728 mii_mediachg(mii); 729 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 730 } 731 732 static void 733 awg_init(void *softc) 734 { 735 struct awg_softc *sc; 736 737 sc = softc; 738 739 AWG_LOCK(sc); 740 awg_init_locked(sc); 741 AWG_UNLOCK(sc); 742 } 743 744 static void 745 awg_stop(struct awg_softc *sc) 746 { 747 if_t ifp; 748 uint32_t val; 749 750 AWG_ASSERT_LOCKED(sc); 751 752 ifp = sc->ifp; 753 754 callout_stop(&sc->stat_ch); 755 756 /* Stop transmit DMA and flush data in the TX FIFO */ 757 val = RD4(sc, EMAC_TX_CTL_1); 758 val &= ~TX_DMA_EN; 759 val |= FLUSH_TX_FIFO; 760 WR4(sc, EMAC_TX_CTL_1, val); 761 762 /* Disable transmitter */ 763 val = RD4(sc, EMAC_TX_CTL_0); 764 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 765 766 /* Disable receiver */ 767 val = RD4(sc, EMAC_RX_CTL_0); 768 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 769 770 /* Disable interrupts */ 771 awg_disable_intr(sc); 772 773 /* Disable transmit DMA */ 774 val = RD4(sc, EMAC_TX_CTL_1); 775 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 776 777 /* Disable receive DMA */ 778 val = RD4(sc, EMAC_RX_CTL_1); 779 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 780 781 sc->link = 0; 782 783 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 784 } 785 786 static int 787 awg_rxintr(struct awg_softc *sc) 788 { 789 if_t ifp; 790 struct mbuf *m, *m0, *mh, *mt; 791 int error, index, len, cnt, npkt; 792 uint32_t status; 793 794 ifp = sc->ifp; 795 mh = mt = NULL; 796 cnt = 0; 797 npkt = 0; 798 799 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 800 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 801 802 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 803 status = le32toh(sc->rx.desc_ring[index].status); 804 if ((status & RX_DESC_CTL) != 0) 805 break; 806 807 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 808 BUS_DMASYNC_POSTREAD); 809 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 810 811 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 812 if (len != 0) { 813 m = sc->rx.buf_map[index].mbuf; 814 m->m_pkthdr.rcvif = ifp; 815 m->m_pkthdr.len = len; 816 m->m_len = len; 817 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 818 819 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 820 (status & RX_FRM_TYPE) != 0) { 821 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 822 if ((status & RX_HEADER_ERR) == 0) 823 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 824 if ((status & RX_PAYLOAD_ERR) == 0) { 825 m->m_pkthdr.csum_flags |= 826 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 827 m->m_pkthdr.csum_data = 0xffff; 828 } 829 } 830 831 m->m_nextpkt = NULL; 832 if (mh == NULL) 833 mh = m; 834 else 835 mt->m_nextpkt = m; 836 mt = m; 837 ++cnt; 838 ++npkt; 839 840 if (cnt == awg_rx_batch) { 841 AWG_UNLOCK(sc); 842 if_input(ifp, mh); 843 AWG_LOCK(sc); 844 mh = mt = NULL; 845 cnt = 0; 846 } 847 848 } 849 850 if ((m0 = awg_alloc_mbufcl(sc)) != NULL) { 851 error = awg_setup_rxbuf(sc, index, m0); 852 if (error != 0) { 853 /* XXX hole in RX ring */ 854 } 855 } else 856 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 857 } 858 859 if (index != sc->rx.cur) { 860 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 861 BUS_DMASYNC_PREWRITE); 862 } 863 864 if (mh != NULL) { 865 AWG_UNLOCK(sc); 866 if_input(ifp, mh); 867 AWG_LOCK(sc); 868 } 869 870 sc->rx.cur = index; 871 872 return (npkt); 873 } 874 875 static void 876 awg_txintr(struct awg_softc *sc) 877 { 878 struct awg_bufmap *bmap; 879 struct emac_desc *desc; 880 uint32_t status; 881 if_t ifp; 882 int i; 883 884 AWG_ASSERT_LOCKED(sc); 885 886 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 887 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 888 889 ifp = sc->ifp; 890 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 891 desc = &sc->tx.desc_ring[i]; 892 status = le32toh(desc->status); 893 if ((status & TX_DESC_CTL) != 0) 894 break; 895 bmap = &sc->tx.buf_map[i]; 896 if (bmap->mbuf != NULL) { 897 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 898 BUS_DMASYNC_POSTWRITE); 899 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 900 m_freem(bmap->mbuf); 901 bmap->mbuf = NULL; 902 } 903 awg_setup_txdesc(sc, i, 0, 0, 0); 904 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 905 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 906 } 907 908 sc->tx.next = i; 909 910 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 911 BUS_DMASYNC_PREWRITE); 912 } 913 914 static void 915 awg_intr(void *arg) 916 { 917 struct awg_softc *sc; 918 uint32_t val; 919 920 sc = arg; 921 922 AWG_LOCK(sc); 923 val = RD4(sc, EMAC_INT_STA); 924 WR4(sc, EMAC_INT_STA, val); 925 926 if (val & RX_INT) 927 awg_rxintr(sc); 928 929 if (val & (TX_INT|TX_BUF_UA_INT)) { 930 awg_txintr(sc); 931 if (!if_sendq_empty(sc->ifp)) 932 awg_start_locked(sc); 933 } 934 935 AWG_UNLOCK(sc); 936 } 937 938 #ifdef DEVICE_POLLING 939 static int 940 awg_poll(if_t ifp, enum poll_cmd cmd, int count) 941 { 942 struct awg_softc *sc; 943 uint32_t val; 944 int rx_npkts; 945 946 sc = if_getsoftc(ifp); 947 rx_npkts = 0; 948 949 AWG_LOCK(sc); 950 951 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 952 AWG_UNLOCK(sc); 953 return (0); 954 } 955 956 rx_npkts = awg_rxintr(sc); 957 awg_txintr(sc); 958 if (!if_sendq_empty(ifp)) 959 awg_start_locked(sc); 960 961 if (cmd == POLL_AND_CHECK_STATUS) { 962 val = RD4(sc, EMAC_INT_STA); 963 if (val != 0) 964 WR4(sc, EMAC_INT_STA, val); 965 } 966 967 AWG_UNLOCK(sc); 968 969 return (rx_npkts); 970 } 971 #endif 972 973 static int 974 awg_ioctl(if_t ifp, u_long cmd, caddr_t data) 975 { 976 struct awg_softc *sc; 977 struct mii_data *mii; 978 struct ifreq *ifr; 979 int flags, mask, error; 980 981 sc = if_getsoftc(ifp); 982 mii = device_get_softc(sc->miibus); 983 ifr = (struct ifreq *)data; 984 error = 0; 985 986 switch (cmd) { 987 case SIOCSIFFLAGS: 988 AWG_LOCK(sc); 989 if (if_getflags(ifp) & IFF_UP) { 990 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 991 flags = if_getflags(ifp) ^ sc->if_flags; 992 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) 993 awg_setup_rxfilter(sc); 994 } else 995 awg_init_locked(sc); 996 } else { 997 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 998 awg_stop(sc); 999 } 1000 sc->if_flags = if_getflags(ifp); 1001 AWG_UNLOCK(sc); 1002 break; 1003 case SIOCADDMULTI: 1004 case SIOCDELMULTI: 1005 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1006 AWG_LOCK(sc); 1007 awg_setup_rxfilter(sc); 1008 AWG_UNLOCK(sc); 1009 } 1010 break; 1011 case SIOCSIFMEDIA: 1012 case SIOCGIFMEDIA: 1013 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1014 break; 1015 case SIOCSIFCAP: 1016 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1017 #ifdef DEVICE_POLLING 1018 if (mask & IFCAP_POLLING) { 1019 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1020 error = ether_poll_register(awg_poll, ifp); 1021 if (error != 0) 1022 break; 1023 AWG_LOCK(sc); 1024 awg_disable_intr(sc); 1025 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1026 AWG_UNLOCK(sc); 1027 } else { 1028 error = ether_poll_deregister(ifp); 1029 AWG_LOCK(sc); 1030 awg_enable_intr(sc); 1031 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1032 AWG_UNLOCK(sc); 1033 } 1034 } 1035 #endif 1036 if (mask & IFCAP_VLAN_MTU) 1037 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 1038 if (mask & IFCAP_RXCSUM) 1039 if_togglecapenable(ifp, IFCAP_RXCSUM); 1040 if (mask & IFCAP_TXCSUM) 1041 if_togglecapenable(ifp, IFCAP_TXCSUM); 1042 if ((if_getcapenable(ifp) & (IFCAP_RXCSUM|IFCAP_TXCSUM)) != 0) 1043 if_sethwassistbits(ifp, CSUM_IP, 0); 1044 else 1045 if_sethwassistbits(ifp, 0, CSUM_IP); 1046 break; 1047 default: 1048 error = ether_ioctl(ifp, cmd, data); 1049 break; 1050 } 1051 1052 return (error); 1053 } 1054 1055 static int 1056 awg_setup_phy(device_t dev) 1057 { 1058 struct awg_softc *sc; 1059 clk_t clk_tx, clk_tx_parent; 1060 const char *tx_parent_name; 1061 char *phy_type; 1062 phandle_t node; 1063 uint32_t reg, tx_delay, rx_delay; 1064 int error; 1065 1066 sc = device_get_softc(dev); 1067 node = ofw_bus_get_node(dev); 1068 1069 if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type) == 0) 1070 return (0); 1071 1072 if (bootverbose) 1073 device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type, 1074 sc->res[_RES_SYSCON] != NULL ? "reg" : "clk"); 1075 1076 if (sc->res[_RES_SYSCON] != NULL) { 1077 reg = bus_read_4(sc->res[_RES_SYSCON], 0); 1078 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 1079 if (strcmp(phy_type, "rgmii") == 0) 1080 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 1081 else if (strcmp(phy_type, "rmii") == 0) 1082 reg |= EMAC_CLK_RMII_EN; 1083 else 1084 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 1085 1086 if (OF_getencprop(node, "tx-delay", &tx_delay, 1087 sizeof(tx_delay)) > 0) { 1088 reg &= ~EMAC_CLK_ETXDC; 1089 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 1090 } 1091 if (OF_getencprop(node, "rx-delay", &rx_delay, 1092 sizeof(rx_delay)) > 0) { 1093 reg &= ~EMAC_CLK_ERXDC; 1094 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 1095 } 1096 1097 if (sc->type == EMAC_H3) { 1098 if (OF_hasprop(node, "allwinner,use-internal-phy")) { 1099 reg |= EMAC_CLK_EPHY_SELECT; 1100 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 1101 if (OF_hasprop(node, 1102 "allwinner,leds-active-low")) 1103 reg |= EMAC_CLK_EPHY_LED_POL; 1104 else 1105 reg &= ~EMAC_CLK_EPHY_LED_POL; 1106 1107 /* Set internal PHY addr to 1 */ 1108 reg &= ~EMAC_CLK_EPHY_ADDR; 1109 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 1110 } else { 1111 reg &= ~EMAC_CLK_EPHY_SELECT; 1112 } 1113 } 1114 1115 if (bootverbose) 1116 device_printf(dev, "EMAC clock: 0x%08x\n", reg); 1117 bus_write_4(sc->res[_RES_SYSCON], 0, reg); 1118 } else { 1119 if (strcmp(phy_type, "rgmii") == 0) 1120 tx_parent_name = "emac_int_tx"; 1121 else 1122 tx_parent_name = "mii_phy_tx"; 1123 1124 /* Get the TX clock */ 1125 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx); 1126 if (error != 0) { 1127 device_printf(dev, "cannot get tx clock\n"); 1128 goto fail; 1129 } 1130 1131 /* Find the desired parent clock based on phy-mode property */ 1132 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent); 1133 if (error != 0) { 1134 device_printf(dev, "cannot get clock '%s'\n", 1135 tx_parent_name); 1136 goto fail; 1137 } 1138 1139 /* Set TX clock parent */ 1140 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent); 1141 if (error != 0) { 1142 device_printf(dev, "cannot set tx clock parent\n"); 1143 goto fail; 1144 } 1145 1146 /* Enable TX clock */ 1147 error = clk_enable(clk_tx); 1148 if (error != 0) { 1149 device_printf(dev, "cannot enable tx clock\n"); 1150 goto fail; 1151 } 1152 } 1153 1154 error = 0; 1155 1156 fail: 1157 OF_prop_free(phy_type); 1158 return (error); 1159 } 1160 1161 static int 1162 awg_setup_extres(device_t dev) 1163 { 1164 struct awg_softc *sc; 1165 hwreset_t rst_ahb, rst_ephy; 1166 clk_t clk_ahb, clk_ephy; 1167 regulator_t reg; 1168 phandle_t node; 1169 uint64_t freq; 1170 int error, div; 1171 1172 sc = device_get_softc(dev); 1173 node = ofw_bus_get_node(dev); 1174 rst_ahb = rst_ephy = NULL; 1175 clk_ahb = clk_ephy = NULL; 1176 reg = NULL; 1177 1178 /* Get AHB clock and reset resources */ 1179 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb); 1180 if (error != 0) { 1181 device_printf(dev, "cannot get ahb reset\n"); 1182 goto fail; 1183 } 1184 if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0) 1185 rst_ephy = NULL; 1186 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb); 1187 if (error != 0) { 1188 device_printf(dev, "cannot get ahb clock\n"); 1189 goto fail; 1190 } 1191 if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0) 1192 clk_ephy = NULL; 1193 1194 /* Configure PHY for MII or RGMII mode */ 1195 if (awg_setup_phy(dev) != 0) 1196 goto fail; 1197 1198 /* Enable clocks */ 1199 error = clk_enable(clk_ahb); 1200 if (error != 0) { 1201 device_printf(dev, "cannot enable ahb clock\n"); 1202 goto fail; 1203 } 1204 if (clk_ephy != NULL) { 1205 error = clk_enable(clk_ephy); 1206 if (error != 0) { 1207 device_printf(dev, "cannot enable ephy clock\n"); 1208 goto fail; 1209 } 1210 } 1211 1212 /* De-assert reset */ 1213 error = hwreset_deassert(rst_ahb); 1214 if (error != 0) { 1215 device_printf(dev, "cannot de-assert ahb reset\n"); 1216 goto fail; 1217 } 1218 if (rst_ephy != NULL) { 1219 error = hwreset_deassert(rst_ephy); 1220 if (error != 0) { 1221 device_printf(dev, "cannot de-assert ephy reset\n"); 1222 goto fail; 1223 } 1224 } 1225 1226 /* Enable PHY regulator if applicable */ 1227 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) { 1228 error = regulator_enable(reg); 1229 if (error != 0) { 1230 device_printf(dev, "cannot enable PHY regulator\n"); 1231 goto fail; 1232 } 1233 } 1234 1235 /* Determine MDC clock divide ratio based on AHB clock */ 1236 error = clk_get_freq(clk_ahb, &freq); 1237 if (error != 0) { 1238 device_printf(dev, "cannot get AHB clock frequency\n"); 1239 goto fail; 1240 } 1241 div = freq / MDIO_FREQ; 1242 if (div <= 16) 1243 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1244 else if (div <= 32) 1245 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1246 else if (div <= 64) 1247 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1248 else if (div <= 128) 1249 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1250 else { 1251 device_printf(dev, "cannot determine MDC clock divide ratio\n"); 1252 error = ENXIO; 1253 goto fail; 1254 } 1255 1256 if (bootverbose) 1257 device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n", 1258 (uintmax_t)freq, sc->mdc_div_ratio_m); 1259 1260 return (0); 1261 1262 fail: 1263 if (reg != NULL) 1264 regulator_release(reg); 1265 if (clk_ephy != NULL) 1266 clk_release(clk_ephy); 1267 if (clk_ahb != NULL) 1268 clk_release(clk_ahb); 1269 if (rst_ephy != NULL) 1270 hwreset_release(rst_ephy); 1271 if (rst_ahb != NULL) 1272 hwreset_release(rst_ahb); 1273 return (error); 1274 } 1275 1276 static void 1277 awg_get_eaddr(device_t dev, uint8_t *eaddr) 1278 { 1279 struct awg_softc *sc; 1280 uint32_t maclo, machi, rnd; 1281 u_char rootkey[16]; 1282 1283 sc = device_get_softc(dev); 1284 1285 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1286 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1287 1288 if (maclo == 0xffffffff && machi == 0xffff) { 1289 /* MAC address in hardware is invalid, create one */ 1290 if (aw_sid_get_rootkey(rootkey) == 0 && 1291 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1292 rootkey[15]) != 0) { 1293 /* MAC address is derived from the root key in SID */ 1294 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1295 (rootkey[3] << 8) | 0x02; 1296 machi = (rootkey[15] << 8) | rootkey[14]; 1297 } else { 1298 /* Create one */ 1299 rnd = arc4random(); 1300 maclo = 0x00f2 | (rnd & 0xffff0000); 1301 machi = rnd & 0xffff; 1302 } 1303 } 1304 1305 eaddr[0] = maclo & 0xff; 1306 eaddr[1] = (maclo >> 8) & 0xff; 1307 eaddr[2] = (maclo >> 16) & 0xff; 1308 eaddr[3] = (maclo >> 24) & 0xff; 1309 eaddr[4] = machi & 0xff; 1310 eaddr[5] = (machi >> 8) & 0xff; 1311 } 1312 1313 #ifdef AWG_DEBUG 1314 static void 1315 awg_dump_regs(device_t dev) 1316 { 1317 static const struct { 1318 const char *name; 1319 u_int reg; 1320 } regs[] = { 1321 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1322 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1323 { "INT_STA", EMAC_INT_STA }, 1324 { "INT_EN", EMAC_INT_EN }, 1325 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1326 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1327 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1328 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1329 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1330 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1331 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1332 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1333 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1334 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1335 { "MII_CMD", EMAC_MII_CMD }, 1336 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1337 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1338 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1339 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1340 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1341 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1342 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1343 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1344 { "RGMII_STA", EMAC_RGMII_STA }, 1345 }; 1346 struct awg_softc *sc; 1347 unsigned int n; 1348 1349 sc = device_get_softc(dev); 1350 1351 for (n = 0; n < nitems(regs); n++) 1352 device_printf(dev, " %-20s %08x\n", regs[n].name, 1353 RD4(sc, regs[n].reg)); 1354 } 1355 #endif 1356 1357 #define GPIO_ACTIVE_LOW 1 1358 1359 static int 1360 awg_phy_reset(device_t dev) 1361 { 1362 pcell_t gpio_prop[4], delay_prop[3]; 1363 phandle_t node, gpio_node; 1364 device_t gpio; 1365 uint32_t pin, flags; 1366 uint32_t pin_value; 1367 1368 node = ofw_bus_get_node(dev); 1369 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop, 1370 sizeof(gpio_prop)) <= 0) 1371 return (0); 1372 1373 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop, 1374 sizeof(delay_prop)) <= 0) 1375 return (ENXIO); 1376 1377 gpio_node = OF_node_from_xref(gpio_prop[0]); 1378 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) 1379 return (ENXIO); 1380 1381 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1, 1382 gpio_prop + 1, &pin, &flags) != 0) 1383 return (ENXIO); 1384 1385 pin_value = GPIO_PIN_LOW; 1386 if (OF_hasprop(node, "allwinner,reset-active-low")) 1387 pin_value = GPIO_PIN_HIGH; 1388 1389 if (flags & GPIO_ACTIVE_LOW) 1390 pin_value = !pin_value; 1391 1392 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 1393 GPIO_PIN_SET(gpio, pin, pin_value); 1394 DELAY(delay_prop[0]); 1395 GPIO_PIN_SET(gpio, pin, !pin_value); 1396 DELAY(delay_prop[1]); 1397 GPIO_PIN_SET(gpio, pin, pin_value); 1398 DELAY(delay_prop[2]); 1399 1400 return (0); 1401 } 1402 1403 static int 1404 awg_reset(device_t dev) 1405 { 1406 struct awg_softc *sc; 1407 int retry; 1408 1409 sc = device_get_softc(dev); 1410 1411 /* Reset PHY if necessary */ 1412 if (awg_phy_reset(dev) != 0) { 1413 device_printf(dev, "failed to reset PHY\n"); 1414 return (ENXIO); 1415 } 1416 1417 /* Soft reset all registers and logic */ 1418 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1419 1420 /* Wait for soft reset bit to self-clear */ 1421 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1422 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1423 break; 1424 DELAY(10); 1425 } 1426 if (retry == 0) { 1427 device_printf(dev, "soft reset timed out\n"); 1428 #ifdef AWG_DEBUG 1429 awg_dump_regs(dev); 1430 #endif 1431 return (ETIMEDOUT); 1432 } 1433 1434 return (0); 1435 } 1436 1437 static void 1438 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1439 { 1440 if (error != 0) 1441 return; 1442 *(bus_addr_t *)arg = segs[0].ds_addr; 1443 } 1444 1445 static int 1446 awg_setup_dma(device_t dev) 1447 { 1448 struct awg_softc *sc; 1449 struct mbuf *m; 1450 int error, i; 1451 1452 sc = device_get_softc(dev); 1453 1454 /* Setup TX ring */ 1455 error = bus_dma_tag_create( 1456 bus_get_dma_tag(dev), /* Parent tag */ 1457 DESC_ALIGN, 0, /* alignment, boundary */ 1458 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1459 BUS_SPACE_MAXADDR, /* highaddr */ 1460 NULL, NULL, /* filter, filterarg */ 1461 TX_DESC_SIZE, 1, /* maxsize, nsegs */ 1462 TX_DESC_SIZE, /* maxsegsize */ 1463 0, /* flags */ 1464 NULL, NULL, /* lockfunc, lockarg */ 1465 &sc->tx.desc_tag); 1466 if (error != 0) { 1467 device_printf(dev, "cannot create TX descriptor ring tag\n"); 1468 return (error); 1469 } 1470 1471 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring, 1472 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map); 1473 if (error != 0) { 1474 device_printf(dev, "cannot allocate TX descriptor ring\n"); 1475 return (error); 1476 } 1477 1478 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map, 1479 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb, 1480 &sc->tx.desc_ring_paddr, 0); 1481 if (error != 0) { 1482 device_printf(dev, "cannot load TX descriptor ring\n"); 1483 return (error); 1484 } 1485 1486 for (i = 0; i < TX_DESC_COUNT; i++) 1487 sc->tx.desc_ring[i].next = 1488 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1489 1490 error = bus_dma_tag_create( 1491 bus_get_dma_tag(dev), /* Parent tag */ 1492 1, 0, /* alignment, boundary */ 1493 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1494 BUS_SPACE_MAXADDR, /* highaddr */ 1495 NULL, NULL, /* filter, filterarg */ 1496 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */ 1497 MCLBYTES, /* maxsegsize */ 1498 0, /* flags */ 1499 NULL, NULL, /* lockfunc, lockarg */ 1500 &sc->tx.buf_tag); 1501 if (error != 0) { 1502 device_printf(dev, "cannot create TX buffer tag\n"); 1503 return (error); 1504 } 1505 1506 sc->tx.queued = TX_DESC_COUNT; 1507 for (i = 0; i < TX_DESC_COUNT; i++) { 1508 error = bus_dmamap_create(sc->tx.buf_tag, 0, 1509 &sc->tx.buf_map[i].map); 1510 if (error != 0) { 1511 device_printf(dev, "cannot create TX buffer map\n"); 1512 return (error); 1513 } 1514 awg_setup_txdesc(sc, i, 0, 0, 0); 1515 } 1516 1517 /* Setup RX ring */ 1518 error = bus_dma_tag_create( 1519 bus_get_dma_tag(dev), /* Parent tag */ 1520 DESC_ALIGN, 0, /* alignment, boundary */ 1521 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1522 BUS_SPACE_MAXADDR, /* highaddr */ 1523 NULL, NULL, /* filter, filterarg */ 1524 RX_DESC_SIZE, 1, /* maxsize, nsegs */ 1525 RX_DESC_SIZE, /* maxsegsize */ 1526 0, /* flags */ 1527 NULL, NULL, /* lockfunc, lockarg */ 1528 &sc->rx.desc_tag); 1529 if (error != 0) { 1530 device_printf(dev, "cannot create RX descriptor ring tag\n"); 1531 return (error); 1532 } 1533 1534 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring, 1535 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map); 1536 if (error != 0) { 1537 device_printf(dev, "cannot allocate RX descriptor ring\n"); 1538 return (error); 1539 } 1540 1541 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map, 1542 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb, 1543 &sc->rx.desc_ring_paddr, 0); 1544 if (error != 0) { 1545 device_printf(dev, "cannot load RX descriptor ring\n"); 1546 return (error); 1547 } 1548 1549 error = bus_dma_tag_create( 1550 bus_get_dma_tag(dev), /* Parent tag */ 1551 1, 0, /* alignment, boundary */ 1552 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1553 BUS_SPACE_MAXADDR, /* highaddr */ 1554 NULL, NULL, /* filter, filterarg */ 1555 MCLBYTES, 1, /* maxsize, nsegs */ 1556 MCLBYTES, /* maxsegsize */ 1557 0, /* flags */ 1558 NULL, NULL, /* lockfunc, lockarg */ 1559 &sc->rx.buf_tag); 1560 if (error != 0) { 1561 device_printf(dev, "cannot create RX buffer tag\n"); 1562 return (error); 1563 } 1564 1565 for (i = 0; i < RX_DESC_COUNT; i++) { 1566 error = bus_dmamap_create(sc->rx.buf_tag, 0, 1567 &sc->rx.buf_map[i].map); 1568 if (error != 0) { 1569 device_printf(dev, "cannot create RX buffer map\n"); 1570 return (error); 1571 } 1572 if ((m = awg_alloc_mbufcl(sc)) == NULL) { 1573 device_printf(dev, "cannot allocate RX mbuf\n"); 1574 return (ENOMEM); 1575 } 1576 error = awg_setup_rxbuf(sc, i, m); 1577 if (error != 0) { 1578 device_printf(dev, "cannot create RX buffer\n"); 1579 return (error); 1580 } 1581 } 1582 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1583 BUS_DMASYNC_PREWRITE); 1584 1585 /* Write transmit and receive descriptor base address registers */ 1586 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1587 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1588 1589 return (0); 1590 } 1591 1592 static int 1593 awg_probe(device_t dev) 1594 { 1595 if (!ofw_bus_status_okay(dev)) 1596 return (ENXIO); 1597 1598 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1599 return (ENXIO); 1600 1601 device_set_desc(dev, "Allwinner Gigabit Ethernet"); 1602 return (BUS_PROBE_DEFAULT); 1603 } 1604 1605 static int 1606 awg_attach(device_t dev) 1607 { 1608 uint8_t eaddr[ETHER_ADDR_LEN]; 1609 struct awg_softc *sc; 1610 phandle_t node; 1611 int error; 1612 1613 sc = device_get_softc(dev); 1614 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1615 node = ofw_bus_get_node(dev); 1616 1617 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) { 1618 device_printf(dev, "cannot allocate resources for device\n"); 1619 return (ENXIO); 1620 } 1621 1622 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 1623 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0); 1624 TASK_INIT(&sc->link_task, 0, awg_link_task, sc); 1625 1626 /* Setup clocks and regulators */ 1627 error = awg_setup_extres(dev); 1628 if (error != 0) 1629 return (error); 1630 1631 /* Read MAC address before resetting the chip */ 1632 awg_get_eaddr(dev, eaddr); 1633 1634 /* Soft reset EMAC core */ 1635 error = awg_reset(dev); 1636 if (error != 0) 1637 return (error); 1638 1639 /* Setup DMA descriptors */ 1640 error = awg_setup_dma(dev); 1641 if (error != 0) 1642 return (error); 1643 1644 /* Install interrupt handler */ 1645 error = bus_setup_intr(dev, sc->res[_RES_IRQ], 1646 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih); 1647 if (error != 0) { 1648 device_printf(dev, "cannot setup interrupt handler\n"); 1649 return (error); 1650 } 1651 1652 /* Setup ethernet interface */ 1653 sc->ifp = if_alloc(IFT_ETHER); 1654 if_setsoftc(sc->ifp, sc); 1655 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev)); 1656 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1657 if_setstartfn(sc->ifp, awg_start); 1658 if_setioctlfn(sc->ifp, awg_ioctl); 1659 if_setinitfn(sc->ifp, awg_init); 1660 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1); 1661 if_setsendqready(sc->ifp); 1662 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); 1663 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM); 1664 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp)); 1665 #ifdef DEVICE_POLLING 1666 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0); 1667 #endif 1668 1669 /* Attach MII driver */ 1670 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change, 1671 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 1672 MIIF_DOPAUSE); 1673 if (error != 0) { 1674 device_printf(dev, "cannot attach PHY\n"); 1675 return (error); 1676 } 1677 1678 /* Attach ethernet interface */ 1679 ether_ifattach(sc->ifp, eaddr); 1680 1681 return (0); 1682 } 1683 1684 static device_method_t awg_methods[] = { 1685 /* Device interface */ 1686 DEVMETHOD(device_probe, awg_probe), 1687 DEVMETHOD(device_attach, awg_attach), 1688 1689 /* MII interface */ 1690 DEVMETHOD(miibus_readreg, awg_miibus_readreg), 1691 DEVMETHOD(miibus_writereg, awg_miibus_writereg), 1692 DEVMETHOD(miibus_statchg, awg_miibus_statchg), 1693 1694 DEVMETHOD_END 1695 }; 1696 1697 static driver_t awg_driver = { 1698 "awg", 1699 awg_methods, 1700 sizeof(struct awg_softc), 1701 }; 1702 1703 static devclass_t awg_devclass; 1704 1705 DRIVER_MODULE(awg, simplebus, awg_driver, awg_devclass, 0, 0); 1706 DRIVER_MODULE(miibus, awg, miibus_driver, miibus_devclass, 0, 0); 1707 1708 MODULE_DEPEND(awg, ether, 1, 1, 1); 1709 MODULE_DEPEND(awg, miibus, 1, 1, 1); 1710